Manual

MAX5556–MAX5559
Low-Cost Stereo Audio DACs
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Clock and Data Interface
The MAX5556–MAX5559 strobe serial data (SDATA) in
on the rising edge of SCLK. LRCLK routes data to the
left or right outputs and, along with SCLK, defines the
number of bits per sample transferred. The digital inter-
polators filter data at internal clock rates derived from
the MCLK frequency. Each device supports both inter-
nal and external serial clock (SCLK) modes.
SDATA Input
The serial interface strobes data (SDATA) in on the ris-
ing edge of SCLK, MSB first. The MAX5556–MAX5559
support four different data formats, as detailed in
Figures 4–7.
MSB
MSBLSB LSB
-2 -3 -4 -5 +5 +4 +3 +2 +1 -1 -2 -3 -4 +5 +4 +3 +2 +1
LRCLK
SCLK
SDATA
DATA DIRECTED TO OUTL
-1
INTERNAL SERIAL CLOCK MODE EXTERNAL SERIAL CLOCK MODE
• I
2
S, 16-BIT DATA AND INTERNAL SCLK =
32 x f
S
IF MCLK/ LRCLK = 256 OR 512
• I
2
S, UP TO 24 BITS OF DATA AND INTERNAL
SCLK = 48 X f
S
IF MCLK/ LRCLK = 384
• I
2
S, UP TO 24 BITS OF DATA
• DATA VALID ON RISING EDGE OF SCLK
DATA DIRECTED TO OUTR
Figure 4. MAX5556 Data Format Timing
INTERNAL SERIAL CLOCK MODE EXTERNAL SERIAL CLOCK MODE
MSB MSBLSB LSB
-2
-3 -4 -5 +5 +4 +3 +2 +1 -1 -2 -3 -4 +5 +4 +3 +2 +1
LRCLK
SCLK
SDATA
DATA DIRECTED TO OUTL
DATA DIRECTED TO OUTR
• LEFT-JUSTIFIED, UP TO 24 BITS OF DATA
• DATA VALID ON RISING EDGE OF SCLK
-1
• LEFT-JUSTIFIED, UP TO 24 BITS OF DATA
• INTERNAL SCLK = 64 x f
S IF MCLK / LRCLK = 256 OR 512
• INTERNAL SCLK = 48 x f
S
IF MCLK / LRCLK = 384
Figure 5. MAX5557 Data Format Timing