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General Description

The MAX5886 is an advanced, 12-bit, 500Msps digital-

to-analog converter (DAC) designed to meet the

demanding performance requirements of signal synthe-

sis applications found in wireless base stations and

other communications applications. Operating from a

single 3.3V supply, this DAC offers exceptional dyna-

mic performance such as 76dBc spurious-free dynamic

range (SFDR) at f

OUT

= 30MHz. The DAC supports

update rates of 500Msps and a power dissipation of

only 230mW.

The MAX5886 utilizes a current-steering architecture,

which supports a full-scale output current range of 2mA

to 20mA, and allows a differential output voltage swing

between 0.1V

P-P

and 1V

P-P

The MAX5886 features an integrated 1.2V bandgap ref-

erence and control amplifier to ensure high accuracy

and low noise performance. Additionally, a separate

reference input pin enables the user to apply an exter-

nal reference source for optimum flexibility and to

improve gain accuracy.

The digital and clock inputs of the MAX5886 are

designed for differential low-voltage differential signal

(LVDS)-compatible voltage levels. The MAX5886 is

available in a 68-pin QFN package with an exposed

paddle (EP) and is specified for the extended industrial

temperature range (-40°C to +85°C).

Refer to the MAX5887 and MAX5888 data sheets for

pin-compatible 14- and 16-bit versions of the MAX5886.

Applications

Base Stations: Single/Multicarrier UMTS,

CDMA, GSM

Communications: LMDS, MMDS, Point-to-Point

Microwave

Digital Signal Synthesis

Automated Test Equipment (ATE)

Instrumentation

Features

♦ 500Msps Output Update Rate

♦ Single 3.3V Supply Operation

♦ Excellent SFDR and IMD Performance

SFDR = 76dBc at f

OUT

= 30MHz (to Nyquist)

IMD = -85dBc at f

OUT

= 10MHz

ACLR = 70dB at f

OUT

= 61MHz

♦ 2mA to 20mA Full-Scale Output Current

♦ Differential, LVDS-Compatible Digital and Clock

Inputs

♦ On-Chip 1.2V Bandgap Reference

♦ Low 130mW Power Dissipation

♦ 68-Pin QFN-EP Package

MAX5886

3.3V, 12-Bit, 500Msps High Dynamic

Performance DAC with Differential LVDS Inputs

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2776; Rev 0; 4/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX5886EGK -40°C to +85°C 68 QFN-EP*

5859606162 5455565763

VCLK

AGND

B2P

QFN

TOP VIEW

DGND

B3N

B3P

B4N

B4P

B5N

B5P

5253

B6N

B6P

FSADJ

REFIO

N.C.

DACREF

AGND

IOUTP

IOUTN

AGND

B9N

B9P

B10N

B10P

B11N

B11P

DGND

SEL0

N.C.

DGND

N.C.

VCLK

CLKGND

CLKN

CLKP

CLKGND

N.C.

48 B8P

N.C.

B2N

656667

B0P

B1N

B1P

B0N

2322212019 2726252418 2928 323130

AGND

N.C.

3433

B7P

B8N

51 B7N

PD 17

MAX5886

Pin Configuration

*EP = Exposed paddle.

Summary of content (18 pages)

PAGE 1
9-2776; Rev 0; 4/03 3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 76dBc at fOUT = 30MHz (to Nyquist) IMD = -85dBc at fOUT = 10MHz ACLR = 70dB at fOUT = 61MHz ♦ 2mA to 20mA Full-Scale Output Current ♦ Differential, LVDS-Compatible Digital and Clock Inputs ♦ On-Chip 1.
PAGE 2
MAX5886 3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) 68-Pin QFN-EP (derate 41.7mW/°C above +70°C) ......3333mW Thermal Resistance (θJA) ..............................................+24°C/W Operating Temperature Range ..........................-40°C to +85°C Junction Temperature .....................................................+150°C Storage Temperature Range ............................
PAGE 3
.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs (AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 4
MAX5886 3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 5
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs (AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL Power Dissipation PDISS Power-Supply Rejection Ratio PSRR CONDITIONS MIN fCLK = 100Msps, fOUT = 1MHz TYP MAX 130 .
PAGE 6
Typical Operating Characteristics (continued) (AVDD = DVDD = VCLK = 3.3V, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, TA = +25°C, unless otherwise noted.) SFDR vs. OUTPUT FREQUENCY (fCLK = 300MHz, AOUT = -6dB FS) fOUT = 10MHz 77 MAX5886 toc09 0.3 MAX5886 toc08 85 MAX5886 toc07 IOUT = 20mA 80 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE SFDR vs. TEMPERATURE (fCLK = 300MHz, AOUT = -6dB FS, IOUT = 20mA) 100 0.2 fOUT = 40MHz IOUT = 5mA 69 fOUT = 120MHz 61 -0.
PAGE 7
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs PIN NAME FUNCTION 1–8, 23, 34, 35–38 N.C. 9, 41, 60, 62 DGND Digital Ground 10, 40, 61 DVDD Digital Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a 0.1µF capacitor to the nearest DGND. 11, 16 VCLK Clock Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a 0.1µF capacitor to the nearest CLKGND.
PAGE 8
3.
PAGE 9
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs DGND SEL0 FUNCTION SELECTION BLOCK 1.2V REFERENCE MAX5886 DVDD PD AGND AVDD MAX5886 REFIO IOUTP IOUTN CURRENT-STEERING DAC FSADJ CLKN CLKP SEGMENT SHUFFLING/LATCH DECODER LVDS RECEIVER/INPUT LATCH 12 DIFFERENTIAL DIGITAL INPUTS B0 THROUGH B11 Figure 1. Simplified MAX5886 Block Diagram Table 1. IOUT and RSET Selection Matrix Based on a Typical 1.
PAGE 10
MAX5886 3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs AVDD 1.2V REFERENCE AVDD CURRENT SOURCES 10kΩ CURRENT SWITCHES REFIO 0.1µF IOUTP FSADJ IREF RSET CURRENT-STEERING DAC IOUT IOUTN IOUTN DACREF IOUT IOUTP IREF = VREFIO/RSET Figure 2. Reference Architecture, Internal Reference Configuration Figure 3 displays a simplified diagram of the MAX5886’s internal output structure. Figure 3.
PAGE 11
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs N N-1 N+1 tSETUP tHOLD MAX5886 B0 TO B11 N+2 tCH tCL CLKP tPD IOUT N-6 N-3 N-4 N-3 N-2 Figure 5. Detailed Timing Relationship A common-mode level of 1.25V and an 800mV differential input swing can be applied to these inputs. Segment Shuffling (SEL0) Segment shuffling can improve the SFDR of the MAX5886. The improvement is most pronounced at higher output frequencies and amplitudes.
PAGE 12
MAX5886 3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs AVDD DVDD VCLK 50Ω T2, 1:1 VOUT, SINGLE ENDED IOUTP B0–B11 100Ω MAX5886 IOUTN 12 T1, 1:1 AGND DGND WIDEBAND RF TRANSFORMER T2 PERFORMS THE DIFFERENTIAL TO SINGLE-ENDED CONVERSION. 50Ω CLKGND Figure 7. Differential to Single-Ended Conversion Using a Wideband RF Transformer AVDD DVDD VCLK 50Ω OUTP IOUTP B0–B11 100Ω MAX5886 IOUTN 12 AGND DGND CLKGND OUTN 50Ω Figure 8.
PAGE 13
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs ANALOG OUTPUT POWER (dBm) The transmitter sections of multicarrier base station transceiver systems for GSM/EDGE usually present -25 -30 -40 -50 fCENTER = 61.44MHz fCLK = 184.32Mbps ACLR = 70dB -60 -70 -80 -90 -100 -110 -120 -130 -140 -145 3.5MHz/div Figure 9. ACLR for W-CDMA Modulation, Single Carrier The number of carriers and their signal levels with respect to the full scale of the DAC are important as well.
PAGE 14
MAX5886 3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs individual carrier must be operated at less than -12dB FS/-18dB FS to avoid waveform clipping. The noise density requirements (Table 2) for a GSM/EDGE-based system can again be derived from the system’s Tx mask. With a worst-case noise level of -80dBc at frequency offsets of ≥6MHz and a measurement bandwidth of 100kHz, the minimum noise density per hertz is calculated as follows: Table 2.
PAGE 15
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5886 4-TONE MULTITONE POWER RATIO PLOT (fCLK = 300MHz, fCENTER = 31.604MHz) 0 MEASUREMENT BANDWIDTH -30 30kHz 100kHz -60 OUTBAND IMD REQUIREMENT: < -70dBc -70 -73 -75 -80 AOUT = -12dB FS BW = 12MHz -20 WORST-CASE NOISE LEVEL -90 OUTPUT POWER (dBm) INBAND TRANSMITTER EDGE AMPLITUDE (dBc) O -10 fT3 fT1 -30 fT4 fT2 -40 -50 -60 -70 -80 -90 -100 0.2 0.4 0.6 1.2 1.8 6.
PAGE 16
MAX5886 3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the PC board with standard infrared (IR) flow soldering techniques.
PAGE 17
3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs Dynamic Performance Parameter Definitions Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog output (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum can be derived from the DAC’s resolution (N bits): SNRdB = 6.02dB ✕ N + 1.
PAGE 18
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 68L QFN.EPS MAX5886 3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 PACKAGE OUTLINE, 68L QFN, 10x10x0.