Instruction Manual

0V to 16V, Dual Hot-Swap Controller with 10-Bit
Current and Voltage Monitor and 4 LED Drivers
MAX5970
______________________________________________________________________________________ 27
Table 30. status3 Register Format
Table 31a. Power-Good Assertion Delay-Time Register Format
Table 31b. Power-Good Assertion Delay
Power-Good Detection and PG_ Outputs
The PG_ output for a given channel is asserted when
the voltage at MON_ is between the undervoltage and
overvoltage critical limits. The status of the power-good
signals is maintained in register status3[3:0]. A value of
1 in any of the pg[] bits indicates a power-good condi-
tion, regardless of the POL setting, which only affects the
PG_ output polarity. The open-drain PG_ output can be
configured for active-high or active-low status indication
by the state of the POL input (see Table 30).
The POL input sets the value of status3[5], which is a
read-only bit; the state of the POL input can be changed
at any time during operation and the polarity of the PG_
outputs changes accordingly.
The assertion of the PG_ output is delayed by a user-
selectable time delay of 50ms, 100ms, 200ms, or 400ms
(see Tables 31a and 31b).
Description: Power-good status register; LATCH, POL, ALERT and Power Good bits
Register Title: status3
Register Address: 0x34
R R R R/W R R R R
RESET
VALUE
— RETRY POL ALERT pg[1] pg[0] 0x00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Description: Power-good assertion delay-time register
Register Title: pgdly
Register Address: 0x38
R R R R R/W R/W R/W R/W
RESET
VALUE
— — — —
pgdly1
(CH1)
pgdly0
(CH1)
pgdly1
(CH0)
pgdly0
(CH0)
0x00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
pgdly1 (CH_) pgdly0 (CH_) PG_ ASSERTION DELAY (ms)
0 0 50
0 1 100
1 0 200
1 1 400