9-5335; Rev 0; 6/10 TION KIT EVALUA BLE IL AVA A Stereo Audio Codec with FLEXSOUND Technology Features S S S S Class D speaker amplifiers provide efficient amplification for two speakers. Low radiated emissions enable completely filterless operation. Integrated bypass switches optionally connect an external amplifier to the transducer when the Class D amplifiers are disabled.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stereo Audio Codec with FLEXSOUND Technology Record Path Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Microphone AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Noise Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX98088 Stereo Audio Codec with FLEXSOUND Technology TABLE OF CONTENTS (continued) Battery Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D8 INB2 E7 INB1 E9 INA2/EXTMICN F9 INA1/EXTMICP G8 MIC2N G9 MIC2P MIC2BYP MIC1N/ F8 DIGMICCLK MIC1P/ E8 DIGMICDATA F7 MICBIAS E6 JACKSNS INABYP MBEN JDETEN JACK DETECTION I2C REG + + EXTMIC EXTMIC PGAINB: +20dB TO -6dB INBDIFF PGAINB: +20dB TO -6dB PGAINA: +20dB TO -6dB INADIFF PGAINA: +20dB TO -6dB PA2EN: 0/20/30dB PGAM2: +20dB TO 0dB PA1EN: 0/20/30dB PGAM1: +20dB TO 0dB CLOCK CONTROL E2 MIXADR MIX MIXADL MIX D1 ADREN ADCR ADCL ADLEN BCLKS1 SIDETONE BIT CLOCK MI
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Absolute Maximum Ratings (Voltages with respect to AGND.) DVDD, AVDD, HPVDD..........................................-0.3V to +2.2V SPKLVDD, SPKRVDD, DVDDS1, DVDDS2...........-0.3V to +6.0V DGND, HPGND, SPKLGND, SPKRGND...............-0.1V to +0.1V HPVSS................................ (HPGND - 2.2V) to (HPGND + 0.3V) C1N..................................... (HPVSS - 0.3V) to (HPGND + 0.3V) C1P......................................(HPGND - 0.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Digital Input/Output Characteristics (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.4 V BCLKS1, LRCLKS1, SDOUTS1—OUTPUT Output Low Voltage VOL VDVDDS1 = 1.65V, IOL = 3mA Output High Voltage VOH VDVDDS1 = 1.65V, IOH = 3mA Input Leakage Current IIH, IIL VDVDD = 2.0V, VIN = 0V, 5.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.4 V DIGMICCLK—OUTPUT Output Low Voltage Output High Voltage VOL VOH VDVDD = 1.65V, IOL = 1mA VDVDD = 1.65V, IOH = 1mA DVDD 0.4 V Input Clock Characteristics (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Audio Interface Timing Characteristics (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.
Stereo Audio Codec with FLEXSOUND Technology MAX98088 tBCLK tF tR tBCLKH BCLK (OUTPUT) tBCLKL BCLK (INPUT) tCLKSYNC tSYNCSET tCLKSYNC LRCLK (OUTPUT) tSYNCHOLD LRCLK (INPUT) tCLKTX tHIZOUT SDOUT (OUTPUT) LSB SDOUT (OUTPUT) MSB HI-Z tCLKTX tHIZOUT LSB HI-Z MSB tSETUP tHOLD SDIN (INPUT) LSB tSETUP tHOLD SDIN (INPUT) MSB LSB MSB MASTER MODE SLAVE MODE Figure 2.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology 1/fMICCLK tHD,MIC tSU,MIC tHD,MIC tSU,MIC LEFT RIGHT LEFT RIGHT Figure 4. Digital Microphone Timing Diagram I2C Timing Characterstics (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. TA = +25NC, unless otherwise noted.) (Note 1) SDA tLOW tBUF tSU,STA tSU,DAT tHD,STA tHD,DAT tSP tSU,STO tHIGH SCL tHD,STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 5. I2C Interface Timing Diagram Note 1: The IC is 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Power Consumption (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.8V, VSPKLVDD = VSPKRVDD = 3.7V) IAVDD (mA) IPVDD (mA) ISPKVDD + ISPKLVDD (mA) IDVDD (mA) IDVDDS1 + IDVDDS2 (mA) POWER (W) DYNAMIC RANGE (dB) DAC Playback 48kHz Stereo HP DAC ª HP 24-bit, music filters, 256Fs 2.04 1.27 0.00 1.53 0.01 8.72 101 DAC Playback 48kHz Stereo HP DAC ª HP 24-bit, music filters, 256Fs, 0.1mW/ channel, RHP = 32I 2.04 2.11 0.00 1.74 0.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.8V, VSPKLVDD = VSPKRVDD = 3.7V) IAVDD (mA) IPVDD (mA) ISPKVDD + ISPKLVDD (mA) IDVDD (mA) IDVDDS1 + IDVDDS2 (mA) POWER (W) DYNAMIC RANGE (dB) DAC Playback 48kHz Mono SPK DAC ª SPK 24-bit, music filters 1.35 0.00 3.23 1.84 0.01 17.69 86 Line Playback Mono SPK INA ª SPKL Differential inputs 1.01 0.00 3.24 0.03 0.00 13.83 83 Full-Duplex 8kHz Mono RCV MIC1 ª ADC DAC ª REC 16-bit, voice filters 6.
Typical Operating Characteristics (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF.
Stereo Audio Codec with FLEXSOUND Technology TOP VIEW (BUMP SIDE DOWN) 1 2 3 4 5 6 7 8 9 A SPKRN SPKRGND SPKLVDD SPKLP SPKLN RECP/ LOUTL/ RXINP PVDD HPVSS HPGND B SPKRN SPKRGND SPKLVDD SPKLP SPKLN RECN/ LOUTR/ RXINN C1P C1N HPVDD C SPKRP SPKRP SPKRVDD SPKLGND SPKLGND N.C N.C. HPSNS HPL MAX98088 D BCLKS1 SDOUTS1 SPKRVDD LRCLKS1 N.C. N.C. N.C. INB2 HPR E DVDDS1 MCLK N.C.
Stereo Audio Codec with FLEXSOUND Technology MAX98088 Pin Description PIN NAME A1, B1 SPKRN FUNCTION A2, B2 SPKRGND Right-Speaker Ground A3, B3 SPKLVDD Left-Speaker, REF, Receiver Amp Power Supply. Bypass to SPKLGND with a 1FF and a 10FF capacitor. Negative Right-Channel Class D Speaker Output A4, B4 SPKLP Positive Left-Channel Class D Speaker Output A5, B5 SPKLN Negative Left-Channel Class D Speaker Output A6 RECP/LOUTL/ RXINP Positive Receiver Amplifier Output or Left Line Output.
Stereo Audio Codec with FLEXSOUND Technology PIN NAME FUNCTION E5 IRQ Hardware Interrupt Output. IRQ can be programmed to pull low when bits in status register 0x00 change state. Read status register 0x00 to clear IRQ once set. Repeat faults have no effect on IRQ until it is cleared by reading the I2C status register 0x00. Connect a 10kI pullup resistor to DVDD for full output swing. E6 JACKSNS Jack Sense. Detects the insertion of a jack. See the Jack Detection section.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Detailed Description The MAX98088 is a fully integrated stereo audio codec with FLEXSOUND technology and integrated amplifiers. Two differential microphone amplifiers can accept signals from three analog inputs. One input can be retasked to support two digital microphones. Any combination of two microphones (analog or digital) can be recorded simultaneously. The analog signals are amplified up to 50dB and recorded by the stereo ADC.
Stereo Audio Codec with FLEXSOUND Technology Registers Table 1 lists all of the registers, their addresses, and power-on-reset states. Registers 0x00 to 0x03 and 0xFF are read-only while all of the other registers are read/ write. Write zeros to all unused bits in the register table when updating the register, unless otherwise noted. Table 1.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 1.
Stereo Audio Codec with FLEXSOUND Technology REGISTER B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE LEVEL CONTROL Sidetone DSTS 0 DVST 0x2E 0x00 R/W 74 DV1 0x2F 0x00 R/W 91 DAI1 Playback Level DV1M 0 DAI1 Playback Level 0 0 0 EQCLP1 DVEQ1 0x30 0x00 R/W 90 DAI2 Playback Level DV2M 0 0 0 DV2 0x31 0x00 R/W 91 DAI2 Playback Level 0 0 0 EQCLP2 DVEQ2 0x32 0x00 R/W 90 Left ADC Level 0 0 AVLG AVL 0x33 0x00 R/W 73 Right ADC Level 0 0 AVRG AVR 0
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 1.
Stereo Audio Codec with FLEXSOUND Technology REGISTER B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE DSP COEFFICIENTS EQ Band 1 (DAI1/DAI2) EQ Band 2 (DAI1/DAI2) EQ Band 3 (DAI1/DAI2) EQ Band 4 (DAI1/DAI2) K_1[15:8] 0x52/0x84 0xXX R/W 89 K_1[7:0] 0x53/0x85 0xXX R/W 89 K1_1[15:8] 0x54/0x86 0xXX R/W 89 K1_1[7:0] 0x55/0x87 0xXX R/W 89 K2_1[15:8] 0x56/0x88 0xXX R/W 89 K2_1[7:0] 0x57/0x89 0xXX R/W 89 c1_1[15:8] 0x58/0x8A 0xXX R/W 89 c1_1[7:0] 0x59/0x8B 0xXX
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 1.
Stereo Audio Codec with FLEXSOUND Technology Table 2. Power Management Registers REGISTER 0x51 BIT NAME DESCRIPTION 7 SHDN Global Shutdown. Disables everything except the headset detection circuitry, which is controlled separately. 0 = Device Shutdown 1 = Device Enabled 6 VBATEN 3 PERFMODE Performance Mode. Selects DAC to headphone playback performance mode. 0 = High performance playback mode 1 = Low power playback mode.. HPPLYBCK Headphone Only Playback Mode.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 2. Power Management Registers (continued) REGISTER BIT NAME 7 HPLEN 6 HPREN Right Headphone Enable 0 = Disabled 1 = Enabled 5 SPLEN Left Speaker Enable 0 = Disabled 1 = Enabled 4 SPREN Right Speaker Enable 0 = Disabled 1 = Enabled 0x4D 3 RECLEN Receiver/Left Line Output Enable. Use this bit to enable the differential receiver output or left line output. 0 = Disabled 1 = Enabled 2 RECREN Right Line Output Enable.
Stereo Audio Codec with FLEXSOUND Technology In the typical application, one microphone input is used for the handset microphone and the other is used as an accessory microphone. In systems using a background noise microphone, INA can be retasked as another microphone input. In systems where the codec is not the only device recording microphone signals, connect microphones to MIC2P/MIC2N and EXTMICP/EXTMICN. MIC1P/MIC1N then become outputs that route the microphone signals to an external device as needed.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 3.
Stereo Audio Codec with FLEXSOUND Technology REGISTER BIT NAME 7 INABYP 4 MIC2BYP 1 RECBYP 0x4A MAX98088 Table 3. Microphone Input Registers (continued) DESCRIPTION INA_/EXTMIC_ to MIC1_ Bypass Switch 0 = Disabled 1 = Enabled MIC1_ to MIC2_ Bypass Switch 0 = Disabled 1 = Enabled See the Output Bypass Switches section. 0 SPKBYP Line Inputs The device includes two sets of line inputs (Figure 7). Each set can be configured as a stereo single-ended input or as a mono differential input.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 4. Line Input Registers REGISTER BIT 6 0x37/0x38 NAME DESCRIPTION INAEXT/INBEXT 2 1 PGAINA/PGAINB 0 7 INADIFF 6 INBDIFF 0x47 Line Input A/B External Gain Switches out the internal input resistor and selects a trimmed 20kI feedback resistor. Use an external input resistor to set the gain of the line input.
Stereo Audio Codec with FLEXSOUND Technology REGISTER BIT NAME DESCRIPTION 7 Left/Right ADC Input Mixer Selects which analog inputs are recorded by the left/right ADC. 1xxxxxxx = MIC1 x1xxxxxx = MIC2 xx1xxxxx = INA1 pin direct xxx1xxxx = INA2 pin direct xxxx1xxx = INA1 xxxxx1xx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1) xxxxxx1x = INB1 xxxxxxx1 = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1) 6 5 0x23/0x24 4 3 MAX98088 Table 5.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 6. Record Path Signal Processing Registers REGISTER BIT NAME 7 6 NG 5 AGC Gain Reports the current AGC gain setting.
Stereo Audio Codec with FLEXSOUND Technology REGISTER BIT NAME DESCRIPTION AGCATK AGC Attack Time Defined as the time required to reduce gain by 63% of the total gain reduction (one time constant of the exponential response). Attack times are longer for low AGC threshold levels. See Figure 12 for details. 00 = 2ms 01 = 7.2ms 10 = 31ms 11 = 123ms 3 2 0x3F 1 AGCHLD 0 AGC Hold Time The delay before the AGC release begins.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology ATTACK TIME HOLD TIME RELEASE TIME Figure 12. AGC Timing ADC Record Level Control range, use analog gain to adjust the signal level and set the digital level control to 0dB whenever possible. Digital level control is primarily used when adjusting the record level for digital microphones. The IC includes separate digital level control for the left and right ADC outputs (Figure 13).
Stereo Audio Codec with FLEXSOUND Technology REGISTER BIT NAME DESCRIPTION Left/Right ADC Gain 00 = 0dB 01 = 6dB 10 = 12dB 11 = 18dB 5 AVLG/AVRG 4 Left/Right ADC Level 3 0x33/0x34 MAX98088 Table 7.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 8. Sidetone Register REGISTER BIT NAME 7 DSTS 6 3 0x2E 1 0 Sidetone Source Selects which ADC output is fed back as sidetone. When mixing the left and right ADC outputs, each is attenuated by 6dB to prevent full-scale signals from clipping. 00 = Sidetone disabled 01 = Left ADC 10 = Right ADC 11 = Left + Right ADC Sidetone Level Adjusts the sidetone signal level. All levels are referenced to the ADC’s full-scale output.
Stereo Audio Codec with FLEXSOUND Technology LRCLKS1 SDOUTS1 SDINS1 DVDDS1 BCLKS2 SDOUTS2 SDINS2 DVDDS2 DAI1 SDIN2 SDOUT2 BCLK2 SDIN1 SDOUT1 LRCLK1 SEL2 BCLK1 SEL1 LRCLKS2 LRCLK2 BCLKS1 not be the same. This allows the IC to route audio data from one device to another, converting the data format as needed. Figure 15 shows the available digital signal routing options.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 10. Digital Audio Interface Registers REGISTER BIT 7 6 5 NAME MAS1/MAS2 WCI1/WCI2 DAI1/DAI2 Word Clock Invert TDM1/TDM2 = 0: 0 = Left-channel data is transmitted while LRCLK is low. 1 = Right-channel data is transmitted while LRCLK is low. TDM1/TDM2 = 1: Always set WCI = 0. BCI1/BCI2 DAI1/DAI2 Bit Clock Invert BCI1/BCI2 must be set to 1 when TDM1/TDM2 = 1. 0 = SDIN is accepted on the rising edge of BCLK.
Stereo Audio Codec with FLEXSOUND Technology REGISTER BIT NAME 7 OSR1 6 5 DAC_OSR1/ DAC_OSR2 0x15/0x1D 2 1 BSEL1/ BSEL2 0 7 SEL1/SEL2 6 5 4 3 DESCRIPTION ADC Oversampling Ratio Use the higher setting for maximum performance. Use the lower setting for reduced power consumption at the expense of performance.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 10. Digital Audio Interface Registers (continued) REGISTER BIT NAME 2 HIZOFF1/ HIZOFF2 1 SDOEN1/ SDOEN2 DAI1/DAI2 Record Path Output Enable DAI2 outputs data only if LBEN1 = 1.
Stereo Audio Codec with FLEXSOUND Technology MAX98088 WCI_ = 0, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT RIGHT LEFT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK SDIN WCI_ = 1, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT
MAX98088 Stereo Audio Codec with FLEXSOUND Technology WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1 LRCLK SDOUT HI-Z L15 L14 L13 L12 L11 L10 L9 L8 L7 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z BCLK SDIN L6 L5 WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 1, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1
Stereo Audio Codec with FLEXSOUND Technology The MAX98088/MAX98089 includes two digital audio signal paths, both capable of supporting any sample rate from 8kHz to 96kHz. Each path is independently configured to allow different sample rates. To accommodate a wide range of system architectures, three main clocking modes are supported: U PLL Mode: When operating in slave mode, enable the PLL to lock onto any LRCLK input. This mode requires the least configuration, but provides the lowest performance.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 11. Clock Control Registers (continued) REGISTER BIT NAME DESCRIPTION Exact Integer Mode Overrides PLL1 and NI1 and configures a specific PCLK to LRCLK ratio.
Stereo Audio Codec with FLEXSOUND Technology REGISTER BIT NAME DESCRIPTION DAI_ DAC Low Power Select. These bits setup the clocks to be generated from fixed counters that bypass the PLL for DAC low power mode.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 12. Common NI1/NI2 Values LRCLK (kHz) PCLK (MHz) DHF1/2 = 0 10 DHF1/2 = 1 8 11.025 12 16 22.05 24 32 44.1 48 64 88.2 96 13A9 1B18 1D7E 2752 3631 3AFB 4EA5 6C61 75F7 4EA5 6C61 75F7 11 11E0 18A2 1ACF 23BF 3144 359F 477E 6287 6B3E 477E 6287 6B3E 11.2896 116A 1800 1A1F 22D4 3000 343F 45A9 6000 687D 45A9 6000 687D 624E 12 1062 1694 1893 20C5 2D29 3127 4189 5A51 624E 4189 5A51 12.
Stereo Audio Codec with FLEXSOUND Technology REGISTER 0x21 BIT NAME MAX98088 Table 13. Sample Rate Converter DESCRIPTION 4 SRMIX_MODE 3 SRMIX_ENL 2 SRMIX_ENR 1 SRC_ENL 0 SRC_ENR Sample Rate Mix Mode 0 = (DAI1 + DAI2) 1 = (DAI1 + DAI2)/2 Sample Rate Mix Enable 0 = SRC mix disable 1 = SRC mix enable Sample Rate Converter Enable 0 = Sample rate converter disable 1 = Sample rate converter enable Passband Filtering Use music mode when processing high-fidelity audio content.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 14. Passband Filtering Registers REGISTER BIT 7 NAME MODE1 6 DAI1 ADC Highpass Filter Mode 5 MODE1 AVFLT1 4 0x18 3 DHF1 2 0 1 Select a nonzero value to enable the DC-blocking filter. DAI1 High Sample Rate Mode Selects the sample rate range. 0 = 8kHz P LRCLK P 48kHz 1 = 48kHz P LRCLK P 96kHz DVFLT1 0 See Table 15 1 Select a nonzero value to enable the DC-blocking filter.
Stereo Audio Codec with FLEXSOUND Technology AVFTL/DVFLT VALUE INTENDED SAMPLE RATE FILTER RESPONSE 000 N/A Disabled MAX98088 Table 15.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Playback Path Signal Processing The IC playback signal path includes automatic level control (ALC) and a 5-band parametric equalizer (EQ) (Figure 20). The DAI1 and DAI2 playback paths include separate ALCs controlled by a single set of registers. Two completely separate parametric EQs are included for the DAI1 and DAI2 playback paths.
Stereo Audio Codec with FLEXSOUND Technology BIT 7 NAME ALCEN ALC and Excursion Limiter Release Time Sets the release time for both the ALC and Excursion Limiter. See the Excursion Limiter section for Excursion Limiter release times. ALC release time is defined as the time required to adjust the gain from 12dB to 0dB. 6 5 0x43 ALCRLS 4 3 0 VALUE 000 001 010 011 100 101 110 111 ALC RELEASE TIME (s) 8 4 2 1 0.5 0.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Use the attenuator at the EQ’s input to avoid clipping the signal. The attenuator can be programmed for fixed attenuation or dynamic attenuation based on signal level. If the dynamic EQ clip detection is enabled, the signal level from the EQ is fed back to the attenuator circuit to determine the amount of gain reduction necessary to avoid clipping. The MAX98088/MAX98089 EV kit software includes a graphic interface for generating the EQ coefficients.
Stereo Audio Codec with FLEXSOUND Technology allows boost when MODE1 = 0 and attenuation in any mode. The DAI2 signal path allows attenuation only. DV1G: 0/6/12/18dB + MULTI BAND ALC DVEQ1: 0dB TO -15dB DVEQ2: 0dB TO -15dB 5-BAND PARAMETRIC EQ 5-BAND PARAMETRIC EQ EQ1EN EQ2EN EXCURSION LIMITER DV2: 0dB TO -15dB DV1: 0dB TO -15dB MIX AUDIO/ FILTERS MIXDAL DACL DALEN DCB2 AUDIO/ VOICE FILTERS MIX MODE1 DVFLT MIXDAR DACR DAREN Figure 23. Playback Level Control Block Diagram Table 18.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology DAC Input Mixers The IC’s stereo DAC accepts input from two digital audio paths. The DAC mixer routes any audio path to the left and right DACs (Figure 24).
Stereo Audio Codec with FLEXSOUND Technology RECVOLL: +8dB TO -62dB RECP/ LOUTL/ RXINP 0dB MIX RECLEN MIXRECL RECBYP RECVOLR: +8dB TO -62dB MIX 0dB LINEMODE RECREN MIXRECR RECN/ LOUTR/ RXINN SPKBYP SPKLP +6dB SPKLN SPLEN DACL DALEN DACR DAREN Figure 25. Receiver Amplifier Block Diagram 93 MAX98088 Receiver Amplifier The IC includes a single differential receiver amplifier. The receiver amplifier is designed to drive a 32I earpiece speaker.
MAX98088/MAX98089 Stereo Audio Codecs with FLEXSOUND Technology Receiver Output Mixer The IC’s receiver amplifier accepts input from the stereo DAC, the line inputs (single-ended or differential), and the MIC inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixed signal can be configured to attenuate 6dB, 9dB, or 12dB. Table 20.
Stereo Audio Codecs with FLEXSOUND Technology MAX98088/MAX98089 Receiver Output Volume Table 21.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Speaker Amplifiers The IC integrates a stereo filterless Class D amplifier that offers much higher efficiency than Class AB without the typical disadvantages. The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors. In a Class D amplifier, the output transistors act as current steering switches and consume negligible additional power.
Stereo Audio Codec with FLEXSOUND Technology Table 22.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Speaker Output Volume Table 23.
Stereo Audio Codec with FLEXSOUND Technology b + b1z -1 + b 2z -2 H(z) = 0 1 + a 1z -1 + a 2z -2 The coefficients b0, b1, b2, a1, and a2 are sample rate dependent and stored in registers 0xB4 through 0xC7. Store b0, b1, and b2 as positive numbers. Store a1 and a2 as negated two’s complement numbers. Separate filters can be stored for the DAI1 and DAI2 playback paths. The MAX98088/MAX98089 EV kit software includes a graphic interface for generating the user-programmable biquad coefficients.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 24. Excursion Limiter Registers REGISTER BIT NAME 6 5 DHPUCF 4 0x41 1 0 6 5 ALCRLS 4 3 2 0x42 DHPTH 1 0 100 800Hz — 011 00 1kHz Programmable using biquad 200Hz 400Hz — 100Hz — 100 000 001 00 11 01 — 010 10 400Hz DHPLCF 0x43 DESCRIPTION Excursion Limiter Corner Frequency The excursion limiter has limited sliding range and minimum corner frequencies. Listed below are all the valid filter combinations.
Stereo Audio Codec with FLEXSOUND Technology Loudspeakers are typically damaged when the voice coil overheats due to extended operation above the rated power. During normal operation, heat generated in the voice coil is transferred to the speaker’s magnet, which transfers heat to the surrounding air. For the voice coil to overheat, both the voice coil and the magnet must overheat.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 25. Power Limiter Registers (continued) REGISTER BIT NAME Power Limiter Time Constant 2 Select a value that matches the thermal time constant of the loudspeaker’s magnet. 7 6 PWRT2 5 4 0x45 2 PWRT1 0 VALUE TIME CONSTANT (min) VALUE TIME CONSTANT (min) 0x0 Disabled 0x8 3.75 0x1 0.50 0x9 5.00 0x2 0.67 0xA 6.66 0x3 0.89 0xB 8.88 0x4 1.19 0xC Reserved 0x5 1.58 0xD Reserved 0x6 2.11 0xE Reserved 0x7 2.
Stereo Audio Codec with FLEXSOUND Technology REGISTER BIT NAME Distortion Limit Measured in % THD+N.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology VDD VDD/2 Class H Operation A Class H amplifier uses a Class AB output stage with power supplies that are modulated by the output signal. In the case of the ICs, two nominal power-supply differentials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V to -1.8V) are available from the charge pump. Figure 29 shows the operation of the output-voltage-dependent power supply GND CONVENTIONAL AMPLIFIER BIASING SCHEME +VDD 1.8V 0.
Stereo Audio Codec with FLEXSOUND Technology one signal is selected, the mixer can be configured to attenuate the signal by 6dB, 9dB, or 12dB. The stereo DAC can bypass the headphone mixers, and be connected directly to the headphone amplifiers to provide lower power consumption. Table 27.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Headphone Output Volume Table 28.
Stereo Audio Codec with FLEXSOUND Technology an external receiver amplifier is used, route its output to the left speaker through RECP/RXINP and RECN/RXINN, bypassing the Class D amplifier. In systems where an external amplifier drives both the receiver and the IC's line input, one of the differential signals can be disconnected from the receiver when not needed by passing it through the analog switch that connects RECP/RXINP to RECN/RXINN.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Click-and-Pop Reduction The IC includes extensive click-and-pop reduction circuitry. The circuitry minimizes clicks and pops at turn-on, turn-off, and during volume changes. Zero-crossing detection is implemented on all analog PGAs and volume controls to prevent large glitches when volume changes are made. Instead of making a volume change immediately, the change is made when the audio signal crosses the midpoint.
Stereo Audio Codec with FLEXSOUND Technology Jack Detection and Removal When the IC is in normal operation and the MICBIAS is enabled, jack insertion and removal can be detected through JACKSNS. To detect a jack insertion and removal, the ICs must be powered on and MICBIAS enabled. Set JDETEN, MBEN, BIASEN, and VCMEN bits to enable jack detection circuitry. JACKSNS is pulled up by MICBIAS as long as no load is applied to JACKSNS.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Table 33. Jack Detection Registers REGISTER 0x02 (Read Only) 0x4B BIT NAME 6 JKSNS 7 JDETEN 1 JDEB 0 DESCRIPTION JACKSNS State Reports the status of JACKSNS when JDETEN = 1, MBEN = 1, BIASEN = 1, and VCMEN = 1. 0 = JACKSNS low 1 = JACKSNS high Jack Detection Enable 0 = Disabled 1 = Enabled Jack Detection Debounce Configures the debounce time for setting JDET.
Stereo Audio Codec with FLEXSOUND Technology either by poling register 0x00 or configuring the IRQ to pull low when specific events occur. IRQ is an opendrain output that requires a pullup resistor for proper operation. Register 0x0F determines which bits in the status register trigger IRQ to pull low. Table 35. Status and Interrupt Registers REGISTER BIT NAME DESCRIPTION CLD Full Scale 0 = All digital signals are less than full scale. 1 = The DAC or ADC signal path has reached or exceeded full scale.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Device Revision Table 36. Device Revision Register REGISTER BIT NAME DESCRIPTION 7 6 5 0xFF (Read Only) 4 3 Device Revision Code REV is always set to 0x40. REV 2 1 0 I2C Serial Interface The IC features an I2C/SMBusK-compatible, 2-wire serial interface comprising a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the IC and the master at clock rates up to 400kHz.
Stereo Audio Codec with FLEXSOUND Technology is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master retries communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the IC is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the IC, followed by a STOP condition.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology The slave address with the R/W bit set to 0 indicates that the master intends to write data to the ICs. The ICs acknowledge receipt of the address byte during the master-generated 9th SCL pulse. The first byte transmitted from the ICs is the content of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte.
Stereo Audio Codec with FLEXSOUND Technology Typical Operating Circuits Figures 39 and 40 provide example operating circuits for the ICs. sThe external components shown are the minimum required for the ICs to operate. Additional components may be required by the application. 2.8V TO 5.5V 1.8V 10FF 1.8V TO 3.6V 1FF 1.8V TO 5.5V DVDDS1 DVDD 1FF PVDD 1FF AVDD 1.8V TO 3.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology 2.8V TO 5.5V 1.8V 10FF 1.8V TO 3.6V 1FF 1.8V TO 5.5V DVDDS1 DVDD 1FF PVDD 1FF 1.8V TO 3.6V 1FF AVDD 1FF SPKLVDD 1FF SPKRVDD 1FF DVDDS2 10kI TO MICROCONTROLLER BCLKS2 IRQ 10MHz TO 60MHz CLOCK INPUT LRCLKS2 MCLK BCLKS1 DIGITAL AUDIO PORT 1 DATA DIGITAL MIC 1 DIGITAL MIC 2 I2C CONTROL PORT SDINS2 LRCLKS1 SDOUTS2 SDINS1 JACKSNS SDOUTS1 RECP/RXINP SDA RECN/RXINN SCL DATA MIC1N/DIGMICCLK 2.
Stereo Audio Codec with FLEXSOUND Technology The IC does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, more efficient solution.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Many configuration options in the ICs can be made while the devices are operating, however, some registers should only be adjusted when the corresponding audio path is disabled. Table 38 lists the registers that are sensitive during operation. Either disable the corresponding audio path or set SHDN = 0 while changing these registers.
Stereo Audio Codec with FLEXSOUND Technology Charge-Pump Holding Capacitor The holding capacitor (bypassing HPVSS) value and ESR directly affect the ripple at HPVSS. Increasing the capacitor’s value reduces output ripple. Likewise, decreasing the ESR reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Recommended PCB Routing The IC uses a 63-bump WLP package. Figure 42 provides an example of how to connect to all active bumps using 3 layers of the PCB. To ensure uninterrupted ground returns, use layer 2 as a connecting layer between layer 1 and layer 2 and flood the remaining area with ground. Supply Bypassing, Layout, and Grounding Proper layout and grounding are essential for optimum performance.
Stereo Audio Codec with FLEXSOUND Technology MAX98088 Route microphone signals from the microphone to the ICs as a differential pair, ensuring that the positive and negative signals follow the same path as closely as possible with equal trace length. When using single-ended microphones or other single-ended audio sources, ground the negative microphone input as close as possible to the audio source and then treat the positive and negative traces as differential pairs. 0.
MAX98088 Stereo Audio Codec with FLEXSOUND Technology Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 122 PACKAGE TYPE PACKAGE CODE OUTLINE No. LAND PATTERN NO.
Stereo Audio Codec with FLEXSOUND Technology REVISION NUMBER REVISION DATE 0 6/10 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.