Instruction Manual

NUC130 Series DATA SHEET

5.3 Clock Controller

The clock controller generates the clock sources for the whole chip, including all AMBA interface

modules and all peripheral clocks. The clock controller also implements the power control function with

the individually clock on or off control, clock source selection and a 4-bit clock divider next to clock

source selection. The chip will into power-down mode after set the Power-Down bit and then the CPU

Cortex-M0 execute the WFI or the WFE instruction. On the power down mode, the controller turns off

the external crystal and internal oscillator to reduce the power consumption to minimum.

5.3.1 Clock Generator

The clock generator consists of 5 sources which list below:

• One external 32kHz crystal

• One external 12 MHz crystal

• One programmable PLL FOUT(PLL source consists of 12M and 22M)

• One internal 22 MHz oscillator

• One internal 10 kHz oscillator

XT_OUT

XTL12M

12M

XTL12M_EN(PWRCON[0])

XT_IN

OSC22M

22M

OSC22M_EN(PWRCON[6])

PLL

PLL_SRC(PLLCON[19])

PLL FOUT

X32O

XTL32K

32K

XTL32K_EN(PWRCON[1])

X32I

OSC10K

10K

OSC10K_EN(PWRCON[3])

12M

22M

10K

Figure 5-2 Clock generator block diagram

Publication Release Date: May 31, 2010

- 30 - Revision V1.02