Instruction Manual

NUC130 Series DATA SHEET
Publication Release Date: May 31, 2010
- 42 - Revision V1.02
5.9 Timer Controller
5.9.1 General Timer Controller
The timer module includes four channels, TIMER0~TIMER3 (TIMER0 and TIMER1 are at APB1 and
TIMER2 and TIMER3 are at APB2), which allow user to easily implement a counting scheme or timing
control for applications. The timer can perform functions like frequency measurement, event counting,
interval measurement, clock generation, delay timing, and so on. The timer can generates an interrupt
signal upon timeout, or provide the current value of count during operation.
5.9.2 Features
y Independent clock source for each channel (TMR0_CLK, TMR1_CLK, TMR2_CLK, TMR3_CLK).
y Time out period = (Period of timer clock input) * (8-bit Prescale + 1) * (24-bit TCMP)
y Maximum counting cycle time = (1 / 25 MHz) * (2^8) * (2^24), if TCLK = 25 MHz.
y Internal 24-bit up counter is readable through TDR (Timer Data Register).