Instruction Manual

NUC130 Series DATA SHEET
Publication Release Date: May 31, 2010
- 8 - Revision V1.02
I
2
C
Two sets of I
2
C device.
Master/Slave up to 1Mbit/s
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allows devices with different bit rates to communicate vian one
serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and resume
serial transfer.
Programmable clocks allow versatile rate control.
I2C-bus controllers support multiple address recognition ( two slave address with mask option)
I
2
S
Interface with external audio CODEC
Operate as either master or slave mode
Capable of handling 8, 16, 24, and 32 bit word sizes
Mono and stereo audio data supported
I
2
S and MSB justified data format supported
Two 8 word FIFO data buffers are provided, one for transmit and one for receive
Generates interrupt requests when buffer levels cross a programmable boundary
Support two DMA requests, one for transmit and one for receive
CAN 2.0
CAN 2.0B protocol compatible device
Support 11-bit identifier as well as 29-bit identifier
Bit rates up to 1Mbits/s
NRZ bit Coding/ Encoding
Error Detection & Status Report
Bit error, Form error, Stuffing error, 15-bit CRC detection, and Acknowledge error
Interrupt
Each CAN-bus error and Transmission/Receive Done.
Bit Timing Synchronization
Acceptance filter extension
Sleep mode wake up
ADC
12-bit SAR ADC with 800ksps
Up to 8-ch single-end mode or 4-ch differential mode
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
Threshold voltage detection
Conversion start by S/W, external pins
Support PDMA Mode
Analog Comparator
Two analog comparator modules
External input or internal bandgap voltage selectable at negative node
Interrupt when compare result change
Power down wake up