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RA01

Version: 1.0 Date: 10/8/2008

RA01 Universal ISM

Band OOK Receiver

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

LNA

DESCRIPTION

HopeRF’s RA01 is a single chip, low power,

multi-channel OOK receiver designed for use in

applications requiring FCC or ETSI conformance for

unlicensed use in the 433, 868 and 915 MHz bands.

Used in conjunction with HopeRF’s transmitters, the

RA01 is a flexible, low cost, and highly integrated

solution that does not require production alignments.

All required RF functions are integrated. Only an

external crystal and few capacitors are needed for

operation.

The RA01 has a completely integrated PLL for easy

RF design, and its rapid settling time allows for fast

frequency hopping, bypassing multipath fading, and

interference to achieve robust wireless links. The

PLL’s high resolution allows the usage of multiple

channels in any of the bands. The baseband

bandwidth (BW) is programmable to accommodate

various deviation, data rate, and crystal tolerance

requirements. The receiver employs the low-IF

approach; therefore, no external components (except

crystal and filtering capacitors) are needed in a typical

application. The RA01 is a complete analog RF and

baseband receiver, including a multi-band PLL

synthesizer with an LNA, down converter mixers,

baseband filters and amplifiers, and demodulator.

The chip dramatically reduces the load on the

microcontroller with integrated digital data processing:

data filtering, clock recovery, data pattern recognition

and integrated FIFO. To minimize the system cost, the

chip can provide a clock signal for the microcontroller,

avoiding the need for two crystals.

BLOCK DIAGRAM

CRYSTAL

OSC

PLL

SYNTHESIZER

LOW BAT

DETECT

CHANNEL

FILTER

RSSI

GAIN

CONTROL

DETECTOR

DATA SLICER

CONTROL/STATUS

RX DATA

FIFO

WAKE UP

TIMER

POWER ON

RESET

DIGITAL

CONTROLER

CLOCK

RECOVERY

RFP

RFN

XTAL

nSEL SCK SDI SDO MODE nIRQ CLK nRES

RSSI

DATA

DCLK

PIN ASSIGNMENT

RA01

Stand alone mode

RA01

FEATURES

• Fully integrated (low BOM, easy design-in)

• No alignment required in production

• Fast settling, programmable, high-resolution PLL

• Fast frequency hopping capability

• Programmable bit rate (up to 40 kbps)

• Direct differential antenna input

• Programmable baseband bandwidth (85 to 340 kHz)

• Analog and digital RSSI outputs

• Data filtering and clock recovery

• RX pattern recognition

• SPI compatible serial control interface

• Readable registers

• Clock and reset signals for microcontroller

• 64 bit RX data FIFO

• Standard 10 MHz crystal reference

• Accurate Wake-up timer

• Low battery detector

• 2.2 to 3.8 V supply voltage

• Low power consumption

• Low standby current (typ. 0.2 μA)

TYPICAL APPLICATIONS

• Remote control

• Home security and alarm

• Wireless keyboard/mouse and other PC peripherals

• Toy control

• Remote keyless entry

• Tire pressure monitoring

• Telemetry

• Personal/patient data logging

• Remote automatic meter reading

Summary of content (19 pages)

PAGE 1
RA01 RA01 Universal ISM Band OOK Receiver Version: 1.0 Date: 10/8/2008 PIN ASSIGNMENT RA01 DESCRIPTION HopeRF’s RA01 is a single chip, low power, multi-channel OOK receiver designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the 433, 868 and 915 MHz bands. Used in conjunction with HopeRF’s transmitters, the RA01 is a flexible, low cost, and highly integrated solution that does not require production alignments. All required RF functions are integrated.
PAGE 2
RA01 DETAILED DESCRIPTION General The RA01 OOK receiver is a counterpart to the HopeRF transmitter (e.g. RF02). It covers the unlicensed frequency bands at 434, 868 and 915 MHz. The device facilitates compliance with FCC and ETSI requirements. The programmable PLL synthesizer determines the operating frequency while preserving accuracy based on the on-chip crystal controlled reference oscillator. The PLL’s high resolution allows for the use of multiple channels in any of the bands.
PAGE 3
RA01 Version: 1.0 Low Battery Voltage Detector The low battery detector circuit monitors periodically (typ. 8 ms) the supply voltage and generates an interrupt if it falls below a programmable threshold level. Wake-Up Timer The wake-up timer has very low current consumption (4 μA max) and can be programmed from 1 ms to several hours. It calibrates itself to the crystal oscillator at every startup and then at every 30 seconds with an accuracy of ±0.5%.
PAGE 4
RA01 Version: 1.
PAGE 5
RA01 Version: 1.0 Date: 10/8/2008 Typical Application Typical application with FIFO usage Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.
PAGE 6
RA01 Version: 1.
PAGE 7
RA01 Version: 1.0 Date: 10/8/2008 GENERAL DEVICE SPECIFICATIONS All voltages are referenced to Vss, the potential on the ground reference pin VSS. Absolute Maximum Ratings (non-operating) Symbol Vdd Vin Iin ESD Parameter Positive supply voltage Voltage on any pad Input current into any pad except VDD and VSS Electrostatic discharge with human body model Min -0.5 -0.5 25 Max 6.0 Vdd+0.
PAGE 8
RA01 Version: 1.
PAGE 9
RA01 Version: 1.0 Date: 10/8/2008 Note 1: See matching circuit parameters and antenna design guide for information, and Application Notes available from http://www.hoperf.com. Note 2: Using other than a 10 MHz crystal is not recommended because the crystal referred timing and frequency parameters will change accordingly. Note 3: During this period, commands are not accepted by the chip. Note 4: Autocalibration can be turned off. CONTROL INTERFACE Commands to the receiver are sent serially.
PAGE 10
RA01 Version: 1.0 Date: 10/8/2008 Control Commands Control Word Related Parameters/Functions Related control bits 1 Configuration Setting Command 2 3 4 5 6 Frequency Setting Command Frequency band, crystal oscillator load capacitance, baseband filter bandwidth, etc. Frequency of the local oscillator b1 to b0, eb, et, x3 to x0, i2 to i0.
PAGE 11
RA01 Version: 1.0 Date: 10/8/2008 2. Frequency Setting Command bit 15 1 14 0 13 1 12 0 11 f11 10 f10 9 f9 8 f8 7 f7 The 12-bit Frequency Setting Command has the value F. The value F should be in the range of 96 and 3903. When F is out of range, the previous value is kept.
PAGE 12
RA01 Version: 1.0 Date: 10/8/2008 6. Low Battery Detector and Microcontroller Clock Divider Command bit 15 1 14 1 13 0 12 0 11 0 10 0 9 1 8 0 7 d2 6 d1 5 d0 4 elfc 3 t3 2 t2 1 t1 0 t0 POR C213h 1 1 0 0 POR C462h Bit 7-5 : Clock divider configuration (valid only if the crystal oscillator is on): d2 0 0 0 0 1 1 1 1 d1 0 0 1 1 0 0 1 1 d0 0 1 0 1 0 1 0 1 Clock Output Frequency [MHz] 1 1.25 1.66 2 2.5 3.
PAGE 13
RA01 Version: 1.0 Date: 10/8/2008 8. Data Rate Command bit 15 1 14 1 13 0 12 0 11 1 10 0 9 0 8 0 7 cs 6 r6 5 r5 4 r4 3 r3 2 r2 1 r1 0 r0 POR C813h The expected bit rate of the received data stream is determined by the 7-bit value R (bits r6 to r0) and the 1 bit cs. BR = 10 MHz / 29 / (R+1) / (1 + cs*7) In the receiver set R according the next function: R= (10 MHz / 29 /(1 + cs*7)/ BR) – 1 Apart from setting custom values, the standard bit rates from 600 bps to 115.
PAGE 14
RA01 Version: 1.0 Date: 10/8/2008 10. Extended Features Command bit 15 1 14 0 13 1 12 1 11 0 10 0 9 0 8 0 7 exlp 6 ctls 5 0 4 dcal 3 bw1 2 bw0 1 f5 0 f4 POR B0CAh Bit 7 : Enables low power mode for the crystal oscillator. Bit 6 : Clock tail selection bit. Setting this bit selects 512 bit long clock tail instead of the default 128 bit length. Bit 4 : Disables the wake-up timer auto calibration. Bit 3-2 : Select the bandwidth of the PLL.
PAGE 15
RA01 Version: 1.0 Date: 10/8/2008 13. Status Read Command The read command starts with a zero, whereas all other control commands start with a one. Therefore, after receiving the first bit of the control command the RA01 identifies it as a read command.
PAGE 16
RA01 Version: 1.0 Date: 10/8/2008 Interrupt Controlled Mode: The user can define the FIFO level (the number of received bits) which will generate the nFFIT when exceeded. The status bits report the changed FIFO status in this case. FIFO Read Example with FFIT Polling: nSEL 0 1 2 3 4 SCK SDI nFFS FIFO read out FIFO OUT FO+1 FO+2 FO+3 FO+4 SDO FFIT Note: During FIFO access the fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency.
PAGE 17
RA01 Version: 1.0 Date: 10/8/2008 Dual Clock Output When the chip is switched into idle mode, the 10 MHz crystal oscillator starts. After oscillation ramp-up a 1 MHz clock signal is available on the CLK pin. This (fast) clock frequency can be reprogrammed during operation with the Low Battery and Microcontroller Clock Divider Command (page12). During startup and in sleep or standby mode (crystal oscillator disabled), the CLK output is pulled to logic low.
PAGE 18
RA01 Version: 1.0 Date: 10/8/2008 Wake-Up Timer Calibration By default the wake-up timer is calibrated each time it is enabled by setting the et bit in the Configuration Setting Command. After timeout the timer restarts automatically and can be stopped by resetting the et bit. If the timer is programmed to run for longer periods, at app. every 30 seconds it performs additional self-calibration. This feature can be disabled to avoid sudden changes in the actual wake-up time period.
PAGE 19
RA01 Version: 1.0 Date: 10/8/2008 This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope HOPE MICROELECTRONICS CO.,LTD Address: 4/F, Block B3, East Industrial Area, Huaqiaochen, Shenzhen, Guangdong, China. 518052 Microelectronics assumes no responsibility or liability for any use of the information contained herein.