User Manual

RA01
Version: 1.0 Date: 10/8/2008
Interrupt Controlled Mode:
The user can define the FIFO level (the number of received bits) which will generate the nFFIT when exceeded. The
status bits report the changed FIFO status in this case.
FIFO Read Example with FFIT Polling:
Tel: [phone] Fax: [phone] E-mail: [e-mail] http://www.hoperf.com
16
01234
FIFO read out
FIFO OUT
FO+1 FO+2 FO+3 FO+4
nSEL
SCK
nFFS
SDO
FFIT
SDI
Note: During FIFO access the fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency.
Power Saving Modes
The different operating modes of the chip depend on the following control bits:
Operating Mode eb or et or elfc
(Configuration Setting
Comand, Low Battery
Detector command)
en
(Receiver
Setting
Command
)
ex
(Configuration
Setting
Command)
Idd
(typ.)
Active X 1 1 9.6 mA
Idle X 0 1 0.5 mA
Sleep 1 0 0 4 uA
Standby 0 0 0 0.2 uA