RF12 RF12 Universal ISM Band FSK Transceiver RF12 DESCRIPTION Hope’s RF12 is a single chip, low power, multi-channel FSK transceiver designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the 315, 433, 868 and 915 MHz bands. The RF12 transceiver produces a flexible, low cost, and highly integrated solution that does not require production alignments.
RF12 FEATURES Fully integrated (low BOM, easy design-in) No alignment required in production Fast-settling, programmable, high-resolution PLL synthesizer Fast frequency-hopping capability High bit rate (up to 115.
RF12 DETAILED FEATURE-LEVEL DESCRIPTION The RF12 FSK transceiver is designed to cover the unlicensed frequency bands at 315, 433, 868 and 915 MHz. The devices facilitate compliance with FCC and ETSI requirements. The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external components in a typical application.
RF12 Data Filtering and Clock Recovery Output data filtering can be completed by an external capacitor or by using digital filtering according to the final application. Analog operation: The filter is an RC type low-pass filter followed by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are integrated on the chip. An (external) capacitor can be chosen according to the actual bit rate. In this mode, the receiver can handle up to 256 kbps data rate.
RF12 1, Inexpensive, low accuracy crystals 2, Narrower receiver bandwidth (i.e. increased sensitivity) 3, Higher data rate Crystal Oscillator The RF12 has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet.
RF12 PACKAGE PIN DEFINITIONS Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output Pin Name Type Function 1 SDI DI Data input of the serial control interface (SPI compatible) 2 SCK DI Clock input of the serial control interface 3 nSEL DI Chip select input of the serial control interface (active low) 4 SDO DO Serial data output with bus hold 5 nIRQ DO Interrupt request output (active low) FSK DI Transmit FSK data input DATA DO Received data output (FIF
RF12 8 CLK DO XTL AIO REF AIO External reference input.
RF12 Pin 6 Pin 7 Transmit mode el=0 in Configuration Setting Command TX Data input - Transmit mode el=1 in Configuration Setting Command Connect to logic high - Receive mode ef=0 in Configuration Setting Command RX Data output RX Data clock output Receive mode ef=1 in Configuration Setting Command nFFS input FFIT output GENERAL DEVICE SPECIFICATION All voltages are referenced to Vss, the potential on the ground reference pin VSS.
RF12 Idd_RX Supply current (RX mode) Standby current (Sleep Ipd mode) 315/433 MHz bands 11 13 868 MHz band 12 14 915 MHz band 13 15 All blocks disabled 0.3 µA 0.5 µA 1.5 µA mA Low battery voltage detector current Ilb consumption Wake-up timer current Iwt consumption Ix Crystal oscillator and Idle current Vlb Vlba 3 baseband parts are on Low battery detect Programmable in 0.1 V threshold steps 2.2 accuracy 5.3 V mV ±75 0.
RF12 AC Characteristics (Receiver) Symbol BW Parameter Conditions/Notes Min Typ Max mode 0 60 67 75 mode 1 120 134 150 Receiver mode 2 180 200 225 bandwidth mode 3 240 270 300 mode 4 300 350 375 400 mode 5 360 BR FSK bit rate With internal digital filters 0.6 BRA FSK bit rate With analog filter Pmin AFCrange IIP3inh IIP3outh IIP3inl IIP3outl Pmax Cin -3 Receiver BER 10 , BW=67kHz, BR=1.
RF12 Co Output capacitance (set by the In low bands 2 2.6 3.2 automatic antenna tuning In high bands 2.1 2.7 3.
RF12 Note 4: Optimal antenna admittance/impedance: RF12 Yantenna [S] Zantenna [Ohm] Lantenna [nH] 315 MHz 1.5E-3 -j5.14E-3 52 + j179 98.00 433 MHz 1.4E-3 -j7.1E-3 27 + j136 52.00 868 MHz 2E-3 -j1.5E-2 8.7 + j66 12.50 915 MHz 2.2E-3 -j1.55E-2 9 + j63 11.20 Note 5: Adjustable in 8 steps. Note 6: With selective resonant antennas Note 7: During this period, commands are not accepted by the chip. CONTROL INTERFACE Commands to the transmitter are sent serially.
RF12 Timing Diagram Control Commands 1 2 3 4 5 Related control Control Command Related Parameters/Functions Configuration Setting Frequency band, crystal oscillator load el, ef, b1 to b0, Command capacitance, baseband filter bandwidth, etc.
RF12 Low Battery Detector and Microcontroller Clock Divider 14 Command 15 Status Read Command LBD voltage and microcontroller clock division d2 to d0, v4 to ratio v0 Status bits can be read out In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default values of the command registers after power-on. Description of the Control Commands 1.
RF12 Logic connections between power control bits: 3. Frequency Setting Command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 0 1 0 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 A680h The 12-bit parameter F (bits f11 to f0) should be in the range of 96 and 3903. When F value sent is out of range, the previous value is kept.
RF12 4. Data Rate Command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 0 0 0 1 1 0 cs r6 r5 r4 r3 r2 r1 r0 C623h The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit parameter R (bits r6 to r0) and bit cs. BR = 10000 / 29 / (R+1) / (1+cs*7) [kbps] In the receiver set R according to the next function: R= (10000 / 29 / (1+cs*7) / BR) – 1, where BR is the expected bit rate in kbps.
RF12 Bits 7-5 (i2 to i0): Receiver baseband bandwidth (BW) select: i2 i1 i0 BW [kHz] 0 0 0 reserved 0 0 1 400 0 1 0 340 0 1 1 270 1 0 0 200 1 0 1 134 1 1 0 67 1 1 1 reserved Bits 2-0 (r2 to r0): RSSI detector threshold: Bits 4-3 (g1 to g0): LNA gain select: g1 g0 relative to maximum [dB] 0 0 0 0 1 -6 1 0 -14 1 1 -20 r2 r1 r0 RSSIsetth [dBm] 0 0 0 -103 0 0 1 -97 0 1 0 -91 0 1 1 -85 1 0 0 -79 1 0 1 -73 1 1 0 -67 1 0 1 -61
RF12 Bits 2-0 (f2 to f0): DQD threshold parameter. Note: To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bit-rate is close to the deviation. At higher deviation/bit-rate settings higher threshold parameter can report "good signal quality" as well. 7. FIFO and Reset Mode Command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 0 0 1 0 1 0 f3 f2 f1 f0 0 al ff dr CA80h Bits 7-4 (f4 to f0): FIFO IT level.
RF12 Note: The transceiver is in receive (RX) mode when bit er is set using the Power Management Command 9.
RF12 Note: Lock bit is high when the AFC loop is locked, f same bit indicates when two subsequent measuring results are the same, toggle bit changes state in every measurement cycle. In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register) the AFC circuit is automatically enabled when the VDI indicates potential incoming signal during the whole measurement cycle and the circuit measures the same result in two subsequent cycles.
RF12 10.
RF12 12. Wake-Up Timer Command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 1 r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 E196h The wake-up time period can be calculated by (m7 to m0) and (r4 to r0): Twake-up = M * 2R [ms] Note: • For continual operation the et bit should be cleared and set at the end of every cycle. • For future compatibility, use R in a range of 0 and 29. 13.
RF12 1 0 0 2.5 1 0 1 3.33 1 1 0 5 1 1 1 10 The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management Command. 15. Status Read Command The read command starts with a zero, whereas all other control commands start with a one.
RF12 TX REGISTER BUFFERED DATA TRANSMISSION In this operating mode (enabled by bit el, the Configuration Control Command) the TX data is clocked into one of the two 8-bit data registers. The transmitter starts to send out the data from the first register (with the given bit rate) when bit et is set with the Power Management Command. The initial value of the data registers (AAh) can be used to generate preamble.
RF12 RX FIFO BUFFERED DATA READ In this operating mode, incoming data are clocked into a 16 bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data Indicator (VDI) bit and the synchron pattern recognition circuit indicates potentially real incoming data. This prevents the FIFO from being filled with noise and overloading the external microcontroller. Polling Mode: The nFFS signal selects the buffer directly and its content can be clocked out through pin SDO by SCK.
RF12 allowable local oscillator frequency error. Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to the accurate frequency by changing the load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the “midrange”, for example 16 pF. The “pull-ability” of the crystal is defined by its motional capacitance and C0.
RF12 REFERENCE DESIGNS Schematic PCB layout Top view Bottom view Tel: +86-755-86096587 Fax: +86-755-86096602 E-mail: sales@hoperf.com http://www.hoperf.
RF12 SGS Reports Tel: +86-755-86096587 Fax: +86-755-86096602 E-mail: sales@hoperf.com http://www.hoperf.
RF12 Tel: +86-755-86096587 Fax: +86-755-86096602 E-mail: sales@hoperf.com http://www.hoperf.
RF12 RF12 BONDING DIAGRAM Pad Opening: 85um square, except 76um octagon pads (AN1, AN2) Die Size: 2910 X 3315 um Tel: +86-755-86096587 Fax: +86-755-86096602 E-mail: sales@hoperf.com http://www.hoperf.
RF12 This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express HOPE MICROELECTRONICS CO.,LTD or implied license or indemnity under the intellectual property rights of 4/F, Block B3, East Industrial Area, Hope Microelectronics or third parties.