EMBEDDED AND NETWORK COMPUTING TECHNOLOGIES USERS GUIDE SBC35-A9260-B01 Calao Systems 334 rue des Vingt Toises Le Magistère II 38950 Saint Martin Le Vinoux France Phone = +33 (0)4 76 56 38 05 Fax = +33 (0)4 76 56 38 06 E-mail = sales@calao-systems.com = support@calao-systems.
TABLE OF CONTENTS Section 1...............................................................................................................................................3 1.Overview.......................................................................................................................................3 1.1.Scope.....................................................................................................................................3 1.2.Synoptic..................................
SECTION 1 1. Overview 1.1. Scope The SBC35-A9260 is a single board computer which runs a full linux environment. It allows to develop applications on a host computer using cross-compilation toolchain and install the results on the SBC35-A9260. SBC35-A9260 This guide focuses on the SBC35-A9260 board as an industrial board. The board is equiped with an AT91SAM9260 processor in an LFBGA217 package. 1.2.
1.3.
SECTION 2 1. Setting Up the SBC35-A9260 Board 1.1. Electrostatic Warning The SBC35-A9260 board is shipped in protective anti-static packaging. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element. 1.2. Requirements In order to set up the SBC35-A9260 board, the following items are needed: ● ● the SBC35-A9260 board itself.
1.4. Powering Up the Board The SBC35-A9260 requires 5V DC (±5%). DC power is supplied to the board via J3. Coaxial plug center positive standard. 1.5. Getting Started The SBC35-A9260 board is delivered with a pre-installed U-Boot boot loader and an Embedded Linux operating system. These two components are stored in the NAND Flash. You can update your board by downloading all the available sources and tools on the calao website www.calao-systems.com in order to adapt your system to your needs.
SECTION 3 1.
Reset Controller (RSTC) ✔ Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control Clock Generator (CKGR) ✔ Selectable 32768Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock ✔ 3 to 20 MHz On-chip Oscillator, One up to 240 MHz PLL and One up to 130 MHz PLL Power Management Controller (PMC) ✔ Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities ✔ Two Programmable E
Four Universal Synchronous/Asynchronous Receiver Transmitters (USART) ✔ Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding ✔ Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support ✔ Full Modem Signal Control on USART0 Two 2-wire UARTs Two Master/Slave Serial Peripheral Interfaces (SPI) ✔ 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects ✔ Synchronous Communications Two Three-channel 16-bit Timer/Co
AT91SAM9260 Block Diagram Datasheet USG-00001-B01 10/28
1.1. Microcontroller 1x LFBGA 217-ball fitted on board 1.2.
1.6. Remote Communication 1x complete modem serial interface (COM Port 0) via RS232 DB9 male connector 2x additional serial interfaces with RTS/CTS handshake control via HE10-2x5 connector (TTL level signals) 1x DBGU serial port TTL via HE10-2x5 (TTL level signals) 2x USB Host ports V2.0 full speed compliant, 12Mbits per second (UHP) 1x USB V2.0 full speed compliant, 12Mbits per second (UDP) 1x Ethernet 100-base TX with three status LED 1.7.
SECTION 4 1. Configuration 1.1. Solder pads & switch configuration Designation Default setting JP1 2-3 Feature Xin OSC Input level voltage 1-2 : 3.3V 2-3: 1.8V J9 2-3 Slow Clock OSCSEL 1-2: internal RC osc. 2-3: Ext crystal osc. J14 1-2 VDDBU 1-2: Lithium 3V Battery 2-3: 1.
S2 opened Nand write protect: opened: write protection disabled closed: write protection enabled 1.2. Memory Memory configuration Designation Default setting Feature R60 Soldered Enables U4 (D[16..31])chip select access R65 Soldered Enables U8 (D[0..15]) chip select access J15 closed Enables the use of NANDFlash R71 Soldered Enables the use of Ready/busy signal S2 Opened Disables write protect SDRAM U4 & U8 NANDFlash U7 1.3.
1.4. Ethernet The Ethernet PHY DP83848 is wired in RMII mode. 1.5.
57 GND 58 GND 59 D5 60 D4 61 GND 62 GND 63 D3 64 D2 65 GND 66 GND 67 D1 68 D0 69 GND 70 GND 71 A12 72 A15 73 GND 74 GND 75 A20 76 A18 77 GND 78 GND 79 A19 80 A21 81 GND 82 GND 83 PC9/NCS5/CFCS1 84 A22 85 GND 86 GND 87 PC12/IRQ0/NCS7 88 CFWE_NWE_NWR0 89 +3.3V 90 +3.3V 91 CFOE_NRD 92 NCS0 93 +3.3V 94 +3.3V 95 NRST 96 PC15/NWAIT/IRQ1 97 +3.3V 98 +3.
● Pin GPIO expansion connector (J10) Description Pin Description 1 GND 2 GND 3 +3.3V 4 +3.3V 5 GND 6 GND 7 +3.3V 8 +3.
67 GND 68 GND 69 PC2/PCK1/AD2 70 NC 71 GND 72 GND 73 NC 74 NC 75 GND 76 GND 77 WKUP 78 NC 79 GND 80 GND 81 SHDN 82 NC 83 GND 84 GND 85 PB11 86 NC 87 GND 88 GND 89 PB31/PCK1 90 NC 91 GND 92 GND 93 NC 94 NC 95 GND 96 GND 97 NC 98 NC 99 GND 100 GND 1.6. TTL serial port pinout J7, J8, J12 ● Debug Port: J12 Pin Description ● Pin Description 1 NC 2 NC 3 DRXD 4 NC 5 DTXD 6 NC 7 NC 8 NC 9 GND 10 +3.
● COM2 Port: J8 Pin Description Pin Description 1 NC 2 NC 3 RXD2 4 RTS2 5 TXD2 6 CTS2 7 NC 8 NC 9 GND 10 +3V3 Datasheet USG-00001-B01 19/28
SECTION 5 1. Schematics 1.1.
Datasheet USG-00001-B01 21/28
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SECTION 6 1. Errata SECTION 7 1. Revision History 1.1. Revision History Date Version Remarks 2008-10-10 B01 first version SECTION 8 1. COPYRIGHT Notice: The products specifications provided in this datasheet are subject to change without notice. ©2007 CALAO SYSTEMS-All Rights Reserved. The CALAO SYSTEMS logo is a registered trademark of CALAO SYSTEMS. All other names are the property of their respective owners.
