Owner manual

Table Of Contents
54
T48C862-R8
4590B–4BMCU–02/03
Timer 2 COmpare Register 2
(T2CO2) Byte Write
Address: "7"hex - Subaddress: "5"hex
Timer 3
Features Two Compare Registers
Capture Register
Edge Sensitive Input with Zero Cross Detection Capability
Trigger and Single Action Modes
Output Control Modes
Automatically Modulation and Demodulation Modes
FSK Modulation
Pulse Width Modulation (PWM)
Manchester Demodulation Together with SSI
Biphase Demodulation Together with SSI
Pulse-width Demodulation Together with SSI
Figure 49. Timer 3
First write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: 1111b
Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b
8-bit comparator
Compare register 1
RES
Capture register
8-bit counter
Compare register 2
Control
C31
C32
Control
T3SM1
NQ
D
T3RM1 T3IM1 T3TM1
TOG2 T3I
T3TM2T3IM2T3RM2T3SM2
NQ
D
CL3
T3EIM
TOG3
INT5
CM31
CM32
: T3M1
: T3M2