User Manual

105
T89C51AC2
Rev. B – 19-Dec-01
This diagram indicates when s ignals a re c locked internally. The time it takes the signals
to propagat e to the pins, however, ranges from 25 to 125 ns. T his propagation delay is
dependent on variables such as temperature and pin loading. Propagation also varies
from output to output and com ponent . Typically though (T
A
=25°C fully loaded) RD an d
WR
pr opagat ion delays a re a pproximately 50ns . The other si gnals a re typicall y 85 ns.
Propagation delays a re incorporated in the AC spec ifications.
DATA PCL OUT DATA PCL O UT DATA PCL O UT
SAMPLED SAMPLED SAMPLED
STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
FLOAT FLOAT FLOAT
THESE SIGNALS AR E NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
INDICATES ADDRESS TRANSITIONS
EXTE RNAL PROGRAM MEMORY FET CH
FLOAT
DATA
SAMPLED
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM
MEMORY IS EXT ERNAL
OLD DATA
NEW DATA
P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED
P0 PINS SAMPLED
RXD SAMPLED
INTERNAL
CLOCK
XTAL2
ALE
PSEN
P0
P2 (EXT)
READ CYCLE
WRITE CYCLE
RD
P0
P2
WR
PORT OPERATION
MOV PORT SRC
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
(INCLUDES INTO. INT1. TO T1)
SERIAL PORT SHIFT CLO CK
TXD (MODE 0)
DATA OUT
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P0
P2
RXD SAMPLED