T89C51CC02 8-bit MCU with CAN controller and Flash 1. Description Part of the CANaryTM family of microcontrollers dedicated to CAN network applications, the T89C51CC02 is a low pin count 8-bit Flash microcontroller. Besides the full CAN controller T89C51CC02 provides 16 Kbytes of Flash memory including In-system Programming (ISP), 2-Kbyte Boot Flash Memory, 2Kbyte EEPROM and 512 bytes RAM. While remaining fully compatible with the 80C51 it offers a superset of this standard microcontroller.
T89C51CC02 * At BRP = 1 sampling point will be fixed. ** Ask for availability UART XTAL1 XTAL2 RAM 256x8 C51 CORE Flash 16kx 8 ERAM Boot EE loader PROM 256x8 2kx8 2kx8 PCA Timer2 TxDC RxDC T2 T2EX PCA ECI Vss Vcc TxD RxD 3. Block Diagram CAN CONTROLLER IB-bus CPU Timer 0 Timer 1 INT Ctrl Parallel I/O Ports & Ext.
T89C51CC02 4. Pin Configuration VAREF 1 28 P1.0/AN0/T2 VAGND 2 P1.1/AN1/T2EX VAVCC P4.1/RxDC P4.0/TxDC 3 4 27 26 P2.1 6 P3.7 P3.6 P3.5/T1 P3.4/T0 P3.3/INT1 7 8 25 P1.2/AN2/ECI P1.3/AN3/CEX0 24 23 22 21 P1.4/AN4/CEX1 P1.5/AN5 9 20 P2.0 10 19 18 5 SO28 P1.6/AN6 P1.7/AN7 P3.1/TxD 13 16 XTAL1 P3.0/RxD 14 15 XTAL2 4 3 2 1 28 27 26 VAVCC VAGND VAREF P1.0 / AN 0 / T2 P1.1 / AN1 / T2EX P1.2 / AN2 / ECI 17 RESET VSS VCC P4.1 / TxDC P3.
T89C51CC02 Table 1. Pin Description Pin Name Type VSS GND VCC Description Circuit ground potential. Supply voltage during normal, idle, and power-down operation. VAREF Reference Voltage for ADC VAVCC Supply Voltage for ADC VAGND Reference Ground for ADC / Analog Ground Port 1: is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for the Analog Digital Converter (ADC).
T89C51CC02 Pin Name P4.0:1 Type Description I/O Port 4: Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pullup transistor.
T89C51CC02 4.1. I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal.
T89C51CC02 4.3. Read-Modify-Write Instructions Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify the data and then rewrite the latch. These are called "Read-Modifiy-Write" instructions. Below is a complete list of these special instructions (see Table 2). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin: Table 2.
T89C51CC02 2 Osc. PERIODS VCC VCC VCC p1 p2 p3 P1.x P2.x P3.x P4.x OUTPUT DATA n INPUT DATA READ PIN Figure 2. Internal Pull-Up Configurations 8 Rev.
T89C51CC02 5. SFR Mapping The Special Function Registers (SFRs) of the T89C51CC02 fall into the following categories: Table 3. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h PSW D0h Program Status Word SP 81h Stack Pointer LSB of SPX DPL 82h Data Pointer Low byte LSB of DPTR DPH 83h Data Pointer High byte MSB of DPTR 7 6 5 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 B Register Table 4.
T89C51CC02 Table 7.
T89C51CC02 Mnemonic Add Name 7 6 5 4 3 2 1 0 CANTIM 6 CANTIM 5 CANTIM 4 CANTIM 3 CANTIM 2 CANTIM 1 CANTIM 0 CANTIML ACh CAN Timer low CANTIM 7 CANSTMH AFh CAN Timer Stamp high TIMSTMP TIMSTMP TIMSTMP TIMSTMP TIMSTMP TIMSTMP TIMSTMP TIMSTMP 15 14 13 12 11 10 9 8 CANSTML AEh CAN Timer Stamp low TIMSTMP TIMSTMP TIMSTMP TIMSTMP TIMSTMP TIMSTMP TIMSTMP TIMSTMP 7 6 5 4 3 2 1 0 CANTTCH A5h CAN Timer TTC high TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC 9 TIM
T89C51CC02 Table 12.
T89C51CC02 6. Clock 6.1. Introduction The T89C51CC02 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages: • • • • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. Saves power consumption while keeping the same CPU power (oscillator power saving). Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. Increases CPU power by 2 while keeping the same crystal frequency.
T89C51CC02 PCON.0 X2 IDL CKCON.0 X2B Hardware byte ÷2 XTAL1 CPU Core Clock 0 1 XTAL2 CPU CLOCK PD CPU Core Clock Symbol PCON.1 ÷2 1 FT0 Clock 0 ÷2 1 FT1 Clock 0 ÷2 1 FT2 Clock 0 ÷2 1 FUart Clock 0 ÷2 1 FPca Clock 0 ÷2 1 FWd Clock 0 ÷2 1 FCan Clock 0 PERIPH CLOCK X2 CKCON.0 Peripheral Clock Symbol CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 CKCON.7 CKCON.6 CKCON.5 CKCON.4 CKCON.3 CKCON.2 CKCON.1 Figure 3. Clock CPU Generation Diagram 14 Rev.
T89C51CC02 XTAL1 XTAL2 X2 bit CPU clock STD Mode X2 Mode STD Mode Figure 4. Mode Switching Waveforms The X2 bit in the CKCON register (See Table 5) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode).
T89C51CC02 6.3. Register CKCON (S:8Fh) Clock Control Register 7 6 5 4 3 2 1 0 CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number Bit Mnemonic Description 7 CANX2 CAN clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 6 WDX2 Watchdog clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
T89C51CC02 7. Program/Code Memory 7.1. Introduction The T89C51CC02 implement 16 Kbytes of on-chip program/code memory. The FLASH memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing FLASH cells is generated on-chip using the standard VDD voltage. Thus, the FLASH Memory can be programmed using only one voltage and allows in application software programming commonly known as IAP.
T89C51CC02 7.2. FLASH Memory Architecture T89C51CC02 features two on-chip flash memories: • Flash memory FM0: containing 16 Kbytes of program memory (user space) organized into 128 byte pages, • Flash memory FM1: 2 Kbytes for boot loader and Application Programming Interfaces (API). The FM0 supports both parallel programming and Serial In-System Programming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP mode is detailed in the "In-System Programming" section.
T89C51CC02 7.2.1.3. Hardware security space The Hardware security space is a part of FM0 and has a size of 1 byte. The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode. 7.2.1.4. Column latches The column latches, also part of FM0, have a size of full page (128 bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte). Rev.
T89C51CC02 7.3. Overview of FM0 operations The CPU interfaces to the flash memory through the FCON register and AUXR1 register. These registers are used to: • • • • Map the memory spaces in the adressable space Launch the programming of the memory spaces Get the status of the flash memory (busy/not busy) Select the flash memory FM0/FM1. 7.3.1. Mapping of the memory space By default, the user space is accessed by MOVC instruction for read only.
T89C51CC02 The FLASH memory enters a busy state as soon as programming is launched. In this state, the memory is no more available for fetching code. Thus to avoid any erratic execution during programming, the CPU enters Idle mode. Exit is automatically performed at the end of programming. Caution: Interrupts that may occur during programming time must be disable to avoid any spurious exit of the idle mode. 7.3.3.
T89C51CC02 7.3.5. Loading the Column Latches Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page or by any number of bytes in a page. When programming is launched, an automatic erase of the locations loaded in the column latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page.
T89C51CC02 7.3.6. Programming the FLASH Spaces User The following procedure is used to program the User space and is summarized in Figure 9: • Load data in the column latches from address 0000h to 3FFFh1. • Disable the interrupts. • Launch the programming by writing the data sequence 50h followed by A0h in FCON register. The end of the programming indicated by the FBUSY flag cleared. • Enable the interrupts. Note: 1.
T89C51CC02 FLASH Spaces Programming Column Latches Loading see Figure 8 Disable IT EA= 0 Launch Programming FCON= 5xh FCON= Axh FBusy Cleared? Erase Mode FCON = 00h End Programming Enable IT EA= 1 Figure 9. Flash and Extra row Programming Procedure 24 Rev.
T89C51CC02 Hardware Security The following procedure is used to program the Hardware Security space and is summarized in Figure 10: • • • • • • Set FPS and map Harware byte (FCON = 0x0C) Disable the interrupts. Load DPTR at address 0000h. Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction. Launch the programming by writing the data sequence 54h followed by A4h in FCON register. The end of the programming indicated by the FBusy flag cleared. • Enable the interrupts.
T89C51CC02 7.3.7. Reading the FLASH Spaces User The following procedure is used to read the User space and is summarized in Figure 11: • Map the User space by writing 00h in FCON register. • Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h to FFFFh. Extra Row The following procedure is used to read the Extra Row space and is summarized in Figure 11: • Map the Extra Row space by writing 02h in FCON register.
T89C51CC02 7.4. Registers FCON (S:D1h) FLASH Control Register 7 6 5 4 3 2 1 0 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY Bit Number Bit Mnemonic 7-4 FPL3:0 3 FPS 2-1 FMOD1:0 0 FBUSY Description Programming Launch Command Bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (see Table 14.) FLASH Map Program Space Set to map the column latch space in the data memory space. Clear to re-map the data memory space. FLASH Mode See Table 13 or Table 14.
T89C51CC02 8. Data Memory 8.1. Introduction The T89C51CC02 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 bytes RAM segment. • the upper 128 bytes RAM segment. • the expanded 256 bytes RAM segment (ERAM). A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 13 shows the internal data memory spaces organization.
T89C51CC02 8.2. Internal Space 8.2.1. Lower 128 Bytes RAM The lower 128 bytes of RAM (see Figure 13) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 16) select which bank is in use according to Table 15.
T89C51CC02 8.3. Dual Data Pointer 8.3.1. Description The T89C51CC02 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 17) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 15).
T89C51CC02 8.4. Registers PSW (S:8Eh) Program Status Word Register. 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic Description 7 CY Carry Flag Carry out from bit 1 of ALU operands. 6 AC Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5 F0 User Definable Flag 0. 4-3 RS1:0 Register Bank Select Bits Refer to Table 15 for bits description. 2 OV Overflow Flag Overflow set by arithmetic operations. 1 F1 User Definable Flag 1.
T89C51CC02 9. EEPROM data memory 9.1. General description The 2k byte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming).
T89C51CC02 9.4. Read Data The following procedure is used to read the data stored in the EEPROM memory: • • • • Set bit EEE of EECON register Stretch the MOVX to accommodate the slow access time of the column latch Load DPTR with the address to read Execute a MOVX A, @DPTR Rev.
T89C51CC02 9.5. Registers EECON (S:0D2h) EEPROM Control Register 7 6 5 4 3 2 1 0 EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY Bit Number Bit Mnemonic 7-4 EEPL3-0 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 EEE 0 EEBUSY Description Programming Launch command bits Write 5Xh followed by AXh to EEPL to launch the programming.
T89C51CC02 10. In-System-Programming (ISP) 10.1. Introduction With the implementation of the User ROM and the Boot ROM in Flash technology the T89C51CC02 allows the system engineer the development of applications with a very high level of flexibility.
T89C51CC02 10.2. Flash Programming and Erasure There are three methods of programming the Flash memory: • The Atmel bootloader located in FM1 is activated by the application. Low level API routines (located in FM1) to program FM0 will be used. The interface used for serial downloading to FM0 is the UART or the CAN. API can be called also by user’s bootloader located in FM0 at [SBV]00h. • A further method exist in activating the Atmel boot loader by hardware activation.
T89C51CC02 10.2.1. Flash Parallel Programming The three lock bits in Hardware byte are programmed according to Table, will provide different level of protection for the on-chip code and data located in FM0 and FM1. The only way for write this bits are the parallel mode. Table 16. Program Lock bit Program Lock Bits Protection description Security level LB0 LB1 LB2 1 U U U No program lock features enabled. MOVC instruction executed from external program memory returns non encrypted data.
T89C51CC02 10.3 Boot Process 10.3.1. Software boot process example Many algorithms can be used for the software boot process. Before describing them, some explanations are needed for the utility of different flags and bytes available. Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants jump on his application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - BLJB = 0 on parts delivered with bootloader programmed.
T89C51CC02 bit ENBOOT in AUXR1 register is initialized with BLJB. Hardware RESET FCON = F0h ENBOOT = 0 PC = 0000h BLJB == 0 ? Software USER APPLICATION ENBOOT = 1 PC = F800h Boot Loader in FM1 Figure 20. Hardware Boot Process Algorithm Rev.
T89C51CC02 bit ENBOOT in AUXR1 register is initialized with BLJB (Fuse bit). RESET Hardware boot process FCON = F0h BLJB == 0 ? ENBOOT = 1 PC = F800h USER APPLICATION Software boot process FCON == 00h ? EB == 0 ? SBV == FFh ? USER BOOT LOADER DEFAULT BOOT LOADER Figure 21. Example of Software Boot process 40 Rev.
T89C51CC02 10.4. 2 Application-Programming-Interface Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of FLASH pages. All calls are made by functions. All these APIs will be described in an application note.
T89C51CC02 10.5. Application remarks • After loading a new program using by the boot loader, the BLJB bit must be set to allow user application to start at RESET. • A user bootloader can be mapped at address [SBV]00h. The byte SBV contains the high byte of the boot address, and can be read and written by API. • The API can be called during user application, without disabling interrupt. The interrupts are disabled by some APIs, for complex operations. 42 Rev.
T89C51CC02 10.6. XROW Bytes Mnemonic Description Default value Address SBV Boot Vector Address F8h 01h SSB Software Security Byte FFh 05h EB Extra Byte FFh 06h Copy of the Manufacturer Code 58h 30h Copy of the Device ID#1: Family code D7h 31h Copy of the Device ID#2:Memories size and type F7h 60h Copy of the Device ID#3:Name and Revision FFh 61h Table 17.
T89C51CC02 10.7. Hardware Byte 7 6 5 4 3 2 1 0 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic Description 7 X2B X2 Bit Set this bit to start in standard mode Clear this bit to start in X2 mode. 6 BLJB Boot Loader Jump Bitt Clear (=1)this bit to start the user’s application on next RESET (@0000h) located in FM0, Set (=0)this bit to start the boot loader(@F800h) located in FM1. 5-3 - 2-0 LB2:0 Reserved The value read from these bits are indeterminate.
T89C51CC02 11. Serial I/O Port The T89C51CC02 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3).
T89C51CC02 The software may examine the FE bit after each reception to check for data errors. Once set, only software or a reset clears the FE bit. Subsequently received frames with valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the stop bit instead of the last data bit (See Figure 27. and Figure 28.). RXD D0 D1 D2 Start bit D3 D4 D5 D6 D7 Data byte Stop bit RI SMOD0=X FE SMOD0=1 Figure 27.
T89C51CC02 11.3. Given Address Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
T89C51CC02 11.5. REGISTERS SCON (S:98h) Serial Control Register 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Number Bit Mnemonic 7 FE Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SM0 Serial port Mode bit 0 (SMOD0=0) Refer to SM1 for serial port mode selection.
T89C51CC02 SADEN (S:B9h) Slave Address Mask Register 7 6 5 4 3 Bit Number Bit Mnemonic 7-0 2 1 0 2 1 0 2 1 0 Description Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Figure 30. SADEN Register SADDR (S:A9h) Slave Address Register 7 6 5 4 3 Bit Number Bit Mnemonic 7-0 Description Slave Individual Address Reset Value = 0000 0000b Not bit addressable Figure 31.
T89C51CC02 PCON (S:87h) Power Control Register 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
T89C51CC02 12. Timers/Counters 12.1. Introduction The T89C51CC02 implements two general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin.
T89C51CC02 PERIPH CLOCK ÷6 0 THx (8 bits) 1 TLx (5 bits) Overflow TFx TCON reg Timer x Interrupt Request Tx C/Tx# TMOD reg INTx# GATEx TRx TMOD reg TCON reg Figure 34. Timer/Counter x (x= 0 or 1) in Mode 0 12.3.2. Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 35). The selected input increments TL0 register.
T89C51CC02 12.3.4. Mode 3 (Two 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (see Figure 37). This mode is provided for applications requiring an additional 8-bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD register, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a Timer function (counting FPER /6) and takes over use of the Timer 1 interrupt (TF1) and run control (TR1) bits.
T89C51CC02 12.4.2. Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 35). The selected input increments TL1 register. 12.4.3. Mode 2 (8-bit Timer with Auto-Reload) Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 register on overflow (see Figure 36). TL1 overflow sets TF1 flag in TCON register and reloads TL1 with the contents of TH1, which is preset by software.
T89C51CC02 12.6. Registers TCON (S:88h) Timer/Counter Control Register. 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7 TF1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. 6 TR1 Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1.
T89C51CC02 TMOD (S:89h) Timer/Counter Mode Control Register. 7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Number Bit Mnemonic 7 GATE1 6 C/T1# 5 M11 4 M01 3 GATE0 2 C/T0# 1 M10 0 M00 Description Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock.
T89C51CC02 TL0 (S:8Ah) Timer 0 Low Byte Register. 7 6 5 4 3 Bit Number Bit Mnemonic 7:0 2 1 0 2 1 0 2 1 0 Description Low Byte of Timer 0. Reset Value= 0000 0000b Figure 42. TL0 Register TH1 (S:8Dh) Timer 1 High Byte Register. 7 6 5 4 3 Bit Number Bit Mnemonic 7:0 Description High Byte of Timer 1. Reset Value= 0000 0000b Figure 43. TH1 Register TL1 (S:8Bh) Timer 1 Low Byte Register. 7 6 5 4 Bit Number Bit Mnemonic 7:0 3 Description Low Byte of Timer 1.
T89C51CC02 13. Timer 2 13.1. Introduction The T89C51CC02 timer 2 is compatible with timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascadeconnected. It is controlled by T2CON register (See Table 47) and T2MOD register (See Table 48). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/6 (timer operation) or external pin T2 (counter operation) as timer register input.
T89C51CC02 FT2 CLOCK :6 0 1 TR2 T2CON.2 CT/2 T2CON.1 T2 (DOWN COUNTING RELOAD VALUE) FFh FFh (8-bit) (8-bit) T2EX: 1=UP 2=DOWN TOGGLE T2CONreg EXF2 TL2 TH2 (8-bit) (8-bit) RCAP2L (8-bit) TF2 TIMER 2 INTERRUPT T2CONreg RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) Figure 45. Auto-Reload Mode Up/Down Counter 13.3. Programmable Clock-Output In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 46).
T89C51CC02 • Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or different depending on the application. • To start the timer, set TR2 run control bit in T2CON register. It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. FT2 CLOCK 0 1 TR2 T2CON.
T89C51CC02 13.4. Registers T2CON (S:C8h) Timer 2 Control Register 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number Bit Mnemonic 7 TF2 Description Timer 2 overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on timer 2 overflow. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
T89C51CC02 T2MOD (S:C9h) Timer 2 Mode Control Register 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
T89C51CC02 TL2 (S:CCh) Timer 2 Low Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic 7-0 Description Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Figure 50. TL2 Register RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic 7-0 Description High Byte of Timer 2 Reload/Capture. Reset Value = 0000 0000b Not bit addressable Figure 51.
T89C51CC02 14. WatchDog Timer 14.1. Introduction T89C51CC02 contains a powerful programmable hardware WatchDog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc = 12MHz. This WDT consist of a 14-bit counter plus a 7-bit programmable counter, a WatchDog Timer reset register (WDTRST) and a WatchDog Timer programming (WDTPRG) register.
T89C51CC02 14.2. WatchDog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permits to program the WDT duration. Table 18.
T89C51CC02 14.3. WatchDog Timer during Power down mode and Idle In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware reset, servicing the WDT should occur as it normally does whenever T89C51CC02 is reset.
T89C51CC02 14.4. Register WDTPRG (S:A7h) WatchDog Timer Duration Programming register 7 6 5 4 3 2 1 0 - - - - - S2 S1 S0 Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
T89C51CC02 15. Atmel CAN Controller 15.1. Introduction The Atmel CAN Controller provides all the features required to implement the serial communication protocol CAN as defined by the BOSCH GmbH. The CAN specifications as referred to in ISO/11898 (2.0A & 2.0B) for high speed and ISO/11519-2 for low speed are applied. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/s at 8MHz1 Crystal frequency in X2 mode. NOTE: 1.
T89C51CC02 15.3. CAN Controller Mailbox and Registers Organization A pagination allows management of the 48 registers and the 32 (4x8) bytes of the mailbox via 28SFR’s. All actions on message object window SFRs are reflected to the corresponding message object registers.
T89C51CC02 15.3.1. Working on message objects The Page message object register (CANPAGE) is used to select one of the 4 message objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected message object number in the corresponding SFRs. A single register (CANMSG) is used for the message. The maibox pointer is managed by the Page message object register with an auto-incrementation at the end of each access. The range of this counter is 8.
T89C51CC02 15.3.3. Buffer mode Any message object can be used to define the buffer, including non-consecutive message objects, and with no limitation on length. Each message object of the buffer must be initialized CONCH2 = 1 and CONCH1 = 1; Block buffer buffer 1 buffer 0 message object 3 message object 2 message object 1 message object 0 Figure 58. Buffer mode The same acceptance filter must be defined for each message object of the buffer.
T89C51CC02 15.4. IT CAN management The different interrupts are: • • • • • Transmission interrupt, Reception interrupt, Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error), Interrupt when Buffer receive is full, Interrupt on overrun of CAN Timer. CANGIE.5 CANGIE.4 CANGIE.3 ENRX ENTX ENERCH RXOK i CANSTCH.5 TXOK i CANSTCH.6 BERR i CANIE1/2 EICH i CANSTCH.4 SERR i CANSTCH.3 i=0 SIT i CERR i i=14 CANSTCH.2 FERR i CANSTCH.1 AERR i CANGIE.2 ENBUF IEN1.
T89C51CC02 To enable a transmission interrupt: • Enable General CAN IT in the interrupt system register, • Enable interrupt by message object, EICHi, • Enable tranmission interrupt, ENTX. To enable a reception interrupt: • Enable General CAN IT in the interrupt system register, • Enable interrupt by message object, EICHi, • Enable reception interrupt, ENRX.
T89C51CC02 15.5. Bit Timing and BaudRate The baud rate selection is made by Tbit calculation: Tbit = Tsyns + Tprs + Tphs1 + Tphs2 1. Tsyns = Tscl = (BRP[5..0]+ 1) / Fcan. 2. Tprs = (1 to 8) * Tscl = (PRS[2..0]+ 1) * Tscl 3. Tphs1 = (1 to 8) * Tscl = (PHS1[2..0]+ 1) * Tscl 4. Tphs2 = (1 to 8) * Tscl = (PHS2[2..0]+ 1) * Tscl 5. Tsjw = (1 to 4) * Tscl = (SJW[1..0]+ 1) * Tscl The total number of Tscl (Time Quanta) in a bit time is from 8 to 25.
T89C51CC02 15.6. Fault Confinement With respect to fault confinement, a unit may be in one of the three following statuses: • error active, • error passive, • bus off. An error active unit takes part in bus communication and can send an active error frame when the CAN macro detects an error. An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent.
T89C51CC02 15.7. Acceptance filter Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received and an ID+RTR+RB+IDE specified while taking the comparison mask into account) the ID+RTR+RB+IDE received are written over the ID TAG Registers. RxDC Rx Shift Register (internal) ID RTR IDE 13/32 13/32 = 13/32 Write Enable 13/32 ID TAG Registers (Ch i) & CanConch ID Hit (Ch i) 1 13/32 ID MSK Registers (Ch i) RTR IDE ID RTR IDE Figure 62.
T89C51CC02 15.8.
T89C51CC02 15.9. Time Trigger Communication (TTC) and Message Stamping The T89C51CC02 has a programmable 16-bit Timer (CANTIMH&CANTIML) for message stamp and TTC. This CAN Timer starts after the CAN controller is enabled by the ENA bit in the CANGCON register.
T89C51CC02 15.10. CAN Autobaud and Listening mode To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register is set. In this mode, the CAN controller is only listening to the line without acknowledging the received messages. It cannot send any message. The error flags are updated. The bit timing can be adjusted until no error occurs (good configuration find). In this mode, the error counters are frozen. To go back to the standard mode, the AUTOBAUD bit must be cleared by the software.
T89C51CC02 15.11. CAN SFR’s Table 21.
T89C51CC02 15.12. Registers CANGCON (S:ABh) CAN General Control Register 7 6 5 4 3 2 1 0 ABRQ OVRQ TTC SYNCTTC AUTOBAUD TEST ENA GRES Bit Number Bit Mnemonic Description 7 ABRQ Abort request Not an auto-resettable bit. A reset of the ENCH bit (message object control & DLC register) is done for each message object. The pending communications are immediately disabled and the on-going communication will be terminated normally, setting the appropriate status flags, TXOK or RXOK.
T89C51CC02 CANGSTA (S:AAh) CAN General Status Register 7 6 5 4 3 2 1 0 - OVFG - TBSY RBSY ENFG BOFF ERRP Bit Number Bit Mnemonic 7 - 6 OVFG 5 - Description Reserved The values read from this bit isindeterminate. Do not set this bit. Overload frame flag (1) This status bit is set by the hardware as long as the produced overload frame is sent. This flag does not generate an interrupt Reserved The values read from this bit isindeterminate. Do not set this bit.
T89C51CC02 CANGIT (S:9Bh) CAN General Interrupt 7 6 5 4 3 2 1 0 CANIT - OVRTIM OVRBUF SERG CERG FERG AERG Bit Number Bit Mnemonic Description General interrupt flag (1) This status bit is the image of all the CAN controller interrupts sent to the interrupt controller. It can be used in the case of the polling method. 7 CANIT 6 - 5 OVRTIM Overrun CAN Timer This status bit is set when the CAN timer switches 0xFFFF to 0x0000.
T89C51CC02 CANTEC (S:9Ch Read Only) CAN Transmit Error Counter 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 Bit Number Bit Mnemonic 7-0 TEC7:0 Description Transmit Error Counter see Figure 61 Reset Value: 00h Figure 68. CANTEC Register CANREC (S:9Dh Read Only) CAN Reception Error Counter 7 6 5 4 3 2 1 0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 Bit Number Bit Mnemonic 7-0 REC7:0 Description Reception Error Counter see Figure 61 Reset Value: 00h Figure 69.
T89C51CC02 CANGIE (S:C1h) CAN General Interrupt Enable 7 6 5 4 3 2 1 0 - - ENRX ENTX ENERCH ENBUF ENERG - Bit Number Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do not set these bits.
T89C51CC02 CANSIT (S:BBh Read Only) CAN Status Interrupt message object Registers 7 6 5 4 3 2 1 0 - - - - SIT3 SIT2 SIT1 SIT0 Bit Number Bit Mnemonic 7-4 3-0 Description - Reserved The value read from these bit are indeterminate. Do not set these bits. SIT3:0 Status of interrupt by message object 0 - no interrupt. 1 - IT turned on. Reset when interrupt condition is cleared by user. example: CANSIT = 0b 0000 1001 -> IT’s on message objects 3 & 0. see Figure 59.
T89C51CC02 CANBT1 (S:B4h) CAN Bit Timing Registers 1 7 6 5 4 3 2 1 0 - BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 - Bit Number Bit Mnemonic 7 - Description Reserved The value read from this bit is indeterminate. Do not set this bit. Baud rate prescaler The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing.
T89C51CC02 CANBT2 (S:B5h) CAN Bit Timing Registers 2 7 6 5 4 3 2 1 0 - SJW 1 SJW 0 - PRS 2 PRS 1 PRS 0 - Bit Number Bit Mnemonic 7 6-5 - SJW1:0 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Re-synchronization jump width To compensate for phase shifts between clock oscillators of different bus controllers, the controller must re-synchronize on any relevant signal edge of the current transmission.
T89C51CC02 CANBT3 (S:B6h) CAN Bit Timing Registers 3 7 6 5 4 3 2 1 0 - PHS2 2 PHS2 1 PHS2 0 PHS1 2 PHS1 1 PHS1 0 SMP Bit Number Bit Mnemonic 7 6-4 - PHS2 2:0 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Phase segment 2 This phase is used to compensate for phase edge errors. This segment can be shortened by the resynchronization jump width.
T89C51CC02 CANCONCH (S:B3h) CAN message object Control and DLC Register 7 6 5 4 3 2 1 0 CONCH 1 CONCH 0 RPLV IDE DLC 3 DLC 2 DLC 1 DLC 0 Bit Number Bit Mnemonic 7-6 CONCH1:0 5 RPLV 4 IDE 3-0 DLC3:0 Description Configuration of message object CONCH1 CONCH0 0 0: disable 0 1: Transmitter 1 0: Receiver 1 1: Receiver Buffer NOTE: The user must re-write the configuration to enable the corresponding bit in the CANEN1:2 registers.
T89C51CC02 CANSTCH (S:B2h) CAN message object Status Register 7 6 5 4 3 2 1 0 DLCW TXOK RXOK BERR SERR CERR FERR AERR Bit Number Bit Mnemonic Description DLCW Data length code warning The incoming message does not have the DLC expected. Whatever the frame type, the DLC field of the CANCONCH register is updated by the received DLC. TXOK Transmit OK The communication enabled by transmission is completed.
T89C51CC02 CANIDT1 for V2.0 part A (S:BCh) CAN Identifier Tag Registers 1 7 6 5 4 3 2 1 0 IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 IDT 4 IDT 3 Bit Number Bit Mnemonic 7-0 IDT10:3 Description IDentifier tag value See Figure 62. No default value after reset. Figure 80. CANIDT1 Register for V2.0 part A CANIDT2 for V2.
T89C51CC02 CANIDT4 for V2.0 part A (S:BFh) CAN Identifier Tag Registers 4 7 6 5 4 3 2 1 0 - - - - - RTRTAG - RB0TAG Bit Number Bit Mnemonic 7-3 - 2 RTRTAG 1 - 0 RB0TAG Description Reserved The values read from these bits are indeterminate. Do not set these bits. Remote transmission request tag value. Reserved The values read from this bit are indeterminate. Do not set these bit. Reserved bit 0 tag value. No default value after reset. Figure 83. CANIDT4 Register for V2.
T89C51CC02 CANIDT3 for V2.0 part B (S:BEh) CAN Identifier Tag Registers 3 7 6 5 4 3 2 1 0 IDT 12 IDT 11 IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 Bit Number Bit Mnemonic 7-0 IDT12:5 Description IDentifier tag value See Figure 62. No default value after reset. Figure 86. CANIDT3 Register for V2.0 part B CANIDT4 for V2.
T89C51CC02 CANIDM2 for V2.0 part A (S:C5h) CAN Identifier Mask Registers 2 7 6 5 4 3 2 1 0 IDMSK 2 IDMSK 1 IDMSK 0 - - - - - Bit Number Bit Mnemonic 7-5 IDTMSK2:0 4-0 - Description IDentifier mask value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 62. Reserved The values read from these bits are indeterminate. Do not set these bits. No default value after reset. Figure 89. CANIDM2 Register for V2.0 part A CANIDM3 for V2.
T89C51CC02 CANIDM4 for V2.0 part A (S:C7h) CAN Identifier Mask Registers 4 7 6 5 4 3 2 1 0 - - - - - RTRMSK - IDEMSK Bit Number Bit Mnemonic 7-3 - 2 RTRMSK 1 - 0 IDEMSK Description Reserved The values read from these bits are indeterminate. Do not set these bits. Remote transmission request mask value 0 - comparison true forced. 1 - bit comparison enabled. Reserved The value read from this bit is indeterminate. Do not set this bit.
T89C51CC02 CANIDM2 for V2.0 part B (S:C5h) CAN Identifier Mask Registers 2 7 6 5 4 3 2 1 0 IDMSK 20 IDMSK 19 IDMSK 18 IDMSK 17 IDMSK 16 IDMSK 15 IDMSK 14 IDMSK 13 Bit Number Bit Mnemonic 7-0 IDMSK20:13 Description IDentifier mask value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 62. NOTE: The ID Mask is only used for reception. No default value after reset. Figure 93. CANIDM2 Register for V2.0 part B CANIDM3 for V2.
T89C51CC02 CANIDM4 for V2.0 part B (S:C7h) CAN Identifier Mask Registers 4 7 6 5 4 3 2 1 0 IDMSK 4 IDMSK 3 IDMSK 2 IDMSK 1 IDMSK 0 RTRMSK - IDEMSK Bit Number Bit Mnemonic Description 7-3 IDMSK4:0 IDentifier mask value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 62. 2 RTRMSK Remote transmission request mask value 0 - comparison true forced. 1 - bit comparison enabled. 1 - 0 IDEMSK Reserved The value read from this bit is indeterminate. Do not set this bit.
T89C51CC02 CANTCON (S:A1h) CAN Timer ClockControl 7 6 5 4 3 2 1 0 TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0 1 0 Bit Number Bit Mnemonic 7-0 TPRESC7:0 Description Timer Prescaler of CAN Timer This register is a prescaler for the main timer upper counter range = 0 to 255. See Figure 63. Reset Value: 00h Figure 97.
T89C51CC02 CANSTMPH (S:AFh Read Only) CAN Stamp Timer High 7 6 5 4 3 2 1 0 TIMSTMP 15 TIMSTMP 14 TIMSTMP 13 TIMSTMP 12 TIMSTMP 11 TIMSTMP 10 TIMSTMP 9 TIMSTMP 8 Bit Number Bit Mnemonic 7-0 TIMSTMP15:8 Description High byte of Time Stamp See Figure 63. No default value after reset Figure 100.
T89C51CC02 CANTTCL (S:A4h Read Only) CAN TTC Timer Low 7 6 5 4 3 2 1 0 TIMTTC 7 TIMTTC 6 TIMTTC 5 TIMTTC 4 TIMTTC 3 TIMTTC 2 TIMTTC 1 TIMTTC 0 Bit Number Bit Mnemonic 7-0 TIMTTC7:0 Description Low byte of TTC Timer See Figure 63. Reset Value: 0000 0000b Figure 103. CANTTCL Register Rev.
T89C51CC02 16. Programmable Counter Array PCA 16.1. Introduction The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/ counter which serves as the time base for an array of two compare/capture modules.
T89C51CC02 To PCA modules FPca/6 overflow FPca / 2 CH T0 OVF It CL 16 bit up/down counter P1.2 CIDL WDTE CF CR CPS1 CPS0 ECF CMOD 0xD9 CCF1 CCF0 CCON 0xD8 Idle Figure 104. PCA Timer/Counter Rev.
T89C51CC02 16.2. PCA Interrupt CF CR CCF1 CCF0 CCON 0xD8 PCA Timer/Counter Module 0 Module 1 CMOD.0 To Interrupt ECF ECCFn CCAPMn.0 EC EA Figure 105. PCA Timer Interrupts 104 Rev.
T89C51CC02 16.3. PCA Capture Mode To use one of the PCA modules in capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’s capture registers (CCAPnL and CCAPnH).
T89C51CC02 16.4. 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set.
T89C51CC02 16.5. High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set.
T89C51CC02 16.6. Pulse Width Modulator Mode All the PCA modules can be used as PWM outputs. The output frequency depends on the source for the PCA timer. All the modules will have the same output frequency because they all share the PCA timer. The duty cycle of each module is independently variable using the module’s capture register CCAPLn.
T89C51CC02 16.7. PCA Registers CMOD (S:D8h) PCA Counter Mode Register 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description 7 CIDL PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. 6 WDTE Watchdog Timer Enable Clear to disable Watchdog Timer function on PCA Module 4, Set to enable it. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit.
T89C51CC02 CCON (S:D8h) PCA Counter Control Register 7 6 5 CF CR - Bit Number Bit Mnemonic 4 3 2 1 0 CCF1 CCF0 Description 7 CF PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. 6 CR PCA Timer/Counter Run Control bit Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on.
T89C51CC02 CCAP0H (S:FAh) CCAP1H (S:FBh ) PCA High Byte Compare/Capture Module n Register (n=0..1) 7 6 5 4 3 2 1 0 CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 CCAPnH 3 CCAPnH 2 CCAPnH 1 CCAPnH 0 Bit Number Bit Mnemonic 7:0 CCAPnH 7:0 Description High byte of EWC-PCA comparison or capture values Reset Value = 0000 0000b Figure 112. CCAPnH Registers CCAP0L (S: EAh) CCAP1L (S:EBh ) PCA Low Byte Compare/Capture Module n Register (n=0..
T89C51CC02 CCAPM0 (S:DAh) CCAPM1 (S:DBh) PCA Compare/Capture Module n Mode registers (n=0..1) 7 6 5 4 3 2 1 0 - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Bit Number Bit Mnemonic 7 - Description Reserved The Value read from this bit is indeterminate. Do not set this bit. 6 ECOMn Enable Compare Mode Module x bit Clear to disable the Compare function. Set to enable the Compare function.
T89C51CC02 CH (S:F9h) PCA Counter Register High value 7 6 5 4 3 2 1 0 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 Bit Number Bit Mnemonic 7:0 CH 7:0 Description High byte of Timer/Counter Reset Value = 0000 00000b Figure 115. CH Register CL (S:E9h) PCA counter Register Low value 7 6 5 4 3 2 1 0 CL 7 CL 6 CL 5 CL 4 CL 3 CL 2 CL 1 CL 0 Bit Number Bit Mnemonic 7:0 CL0 7:0 Description Low byte of Timer/Counter Reset Value = 0000 00000b Figure 116. CL Register Rev.
T89C51CC02 17. Analog-to-Digital Converter (ADC) 17.1. Introduction This section describes the on-chip 10 bit analog-to-digital converter of the T89C51CC02. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bitcascaded potentiometric ADC. Two kind of conversion are available: - Standard conversion (8 bits).
T89C51CC02 ADCON.5 ADCON.3 ADEN ADSST ADC Interrupt Request ADCON.4 ADEOC ADC CLOCK CONTROL EADC AN0/P1.0 000 AN1/P1.1 001 AN2/P1.2 010 AN3/P1.3 011 AN4/P1.4 100 AN5/P1.5 101 AN6/P1.6 110 AN7/P1.7 111 IEN1.1 ADCIN 8 ADDH 2 ADDL + SAR - AVSS Sample and Hold 10 R/2R DAC SCH2 SCH1 SCH0 ADCON.2 ADCON.1 ADCON.0 VAREF VAGND Figure 117. ADC Description Figure 118 shows the timing diagram of a complete conversion.
T89C51CC02 17.4. ADC Converter Operation A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). The busy flag ADSST(ADCON.3) is automatically set when an A/D conversion is running. After completion of the A/D conversion, it is cleared by hardware. This flag can be read only, a write has no effect. The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and ADDL, it is cleared by software. If the bit EADC (IEN1.
T89C51CC02 17.6. Clock Selection The maximum clock frequency for ADC is 700KHz. A prescaler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency. conversion clock fADC CPU CLOCK ÷2 Prescaler ADCLK A/D CPU Core Clock Symbol Converter Figure 119. A/D Converter clock 17.7. ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode the power dissipation is about 1uW. Rev.
T89C51CC02 17.8. IT ADC management An interrupt end-of-conversion will occurs when the bit ADEOC is actived and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. ADCI ADEOC ADCON.2 EADC IEN1.1 Figure 120. ADC interrupt structure 118 Rev.
T89C51CC02 17.9. Registers ADCF (S:F6h) ADC Configuration 7 6 5 4 3 2 1 0 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 Bit Number Bit Mnemonic 7-0 CH 0:7 Description Channel Configuration Set to use P1.x as ADC input. Clear tu use P1.x as standart I/O port. Reset Value=0000 0000b Figure 121.
T89C51CC02 ADCLK (S:F2h) ADC Clock Prescaler 7 6 5 4 3 2 1 0 - - - PRS 4 PRS 3 PRS 2 PRS 1 PRS 0 Bit Number Bit Mnemonic 7-5 - 4-0 PRS4:0 Description Reserved The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler fADC = fosc / (4 (or 2 in X2 mode)* PRS) Reset Value: XXX0 0000b Figure 123.
T89C51CC02 18. Interrupt System 18.1. Introduction The CAN Controller has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a PCA, a CAN interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below. 00 01 10 11 External Interrupt 0 INT0# Highest Priority Interrupts EX0 00 01 10 11 IEN0.0 Timer 0 ET0 00 01 10 11 IEN0.1 External Interrupt 1 INT1# EX1 00 01 10 11 IEN0.
T89C51CC02 Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each combination.
T89C51CC02 18.2. Registers IEN0 (S:A8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7 EA Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6 EC PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt.
T89C51CC02 IEN1 (S:E8h) Interrupt Enable Register 7 6 5 4 - - - - Bit Number Bit Mnemonic 3 2 1 0 ETIM EADC ECAN Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
T89C51CC02 IPL0 (S:B8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 - PPC PT2 PS PT1 PX1 PT0 PX0 Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7 - 6 PPC EWC Counter Interrupt Priority bit Refer to PPCH for priority level 5 PT2 Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. 4 PS Serial port Priority bit Refer to PSH for priority level.
T89C51CC02 IPL1 (S:F8h) Interrupt Priority Low Register 1 7 6 5 4 - - - - Bit Number Bit Mnemonic 3 2 1 0 POVRL PADCL PCANL Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
T89C51CC02 IPH0 (B7h) Interrupt High Priority Register 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number Bit Mnemonic 7 6 5 4 3 2 1 0 - Description Reserved The value read from this bit is indeterminate. Do not set this bit.
T89C51CC02 IPH1 (S:F7h) Interrupt high priority Register 1 7 6 5 4 - - - - Bit Number Bit Mnemonic 3 2 1 0 POVRH PADCH PCANH Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
T89C51CC02 19. Electrical Characteristics 19.1. Absolute Maximum Ratings (1) Ambiant Temperature Under Bias: I = industrial -40°C to 85°C Storage Temperature -65°C to + 150°C Voltage on VCC to VSS-0.5 V to + 6V Voltage on Any Pin to VSS-0.5 V to VCC + 0.2 V Power Dissipation 1 W(2) NOTES 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device.
T89C51CC02 19.2. DC Parameters for Standard Voltage TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz. Symbol Parameter VIL Input Low Voltage VIH Input High Voltage except XTAL1, RST VIH1 Input High Voltage, XTAL1, RST VOL Output Low Voltage, ports 1, 2, 3 and 4(6) VOH Min Output High Voltage, ports 1, 2, 3, 4 and 5 Typ Max Unit -0.5 0.7(7) V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V 0.3 0.45 1.0 V V V VCC - 0.3 V V V VCC - 0.7 VCC - 1.
T89C51CC02 7. Lower than standart C51 product independant from Vcc supply. VCC ICC VCC VCC RST XTAL2 XTAL1 (NC) CLOCK SIGNAL VSS All other pins are disconnected. Figure 133. ICC Test Condition, Active Mode VCC ICC VCC RST XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL All other pins are disconnected. Figure 134. ICC Test Condition, Idle Mode VCC ICC VCC RST (NC) XTAL2 XTAL1 VSS All other pins are disconnected. Figure 135. ICC Test Condition, Power-Down Mode Rev.
T89C51CC02 VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1 Figure 136. Clock Signal Waveform for ICC Tests in Active and Idle Modes 19.3. DC Parameters for A/D Converter Table 26. DC Parameters for AD Converter Symbol Parameter AVin Analog input voltage Rref Resistance between Vref and Vss Reference voltage Analog input Capacitance Integral non linearity Differential non linearity Offset error Vref Cai INL DNL OE Min Typ Vref + 0.2 Vss- 0.2 12 2.40 Max 18 60 1 0.
T89C51CC02 19.4. AC Parameters 19.4.1. Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ±10% ; F = 0 to 40 MHz. TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%. (Load Capacitance for all outputs = 60 pF.
T89C51CC02 Table 29. AC Parameters for a Variable Clock Units Symbol Type Standard Clock X2 Clock X parameter for -M range TXLXL Min 12 T 6T TQVHX Min 10 T - x 5T-x 50 ns TXHQX Min 2T-x T-x 20 ns TXHDX Min x x 0 ns TXHDV Max 10 T - x 5 T- x 133 ns ns 19.4.3.
T89C51CC02 19.4.5. External Clock Drive Waveforms VCC-0.5V 0.45V 0.7VCC 0.2VCC-0.1 TCHCX TCLCH TCLCX TCHCL TCLCL 19.4.6. AC Testing Input/Output Waveforms VCC -0.5 V 0.2 VCC + 0.9 INPUT/OUTPUT 0.2 VCC - 0.1 0.45 V AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. 19.4.7. Float Waveforms FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.
T89C51CC02 20. Ordering Information T -RL 89C51CC02 Packages: SI: PLCC28 TI: SOW28 TD: SOW24 6K: TSSOP28 M C S Temperature Range I:Industrial -40 to 85oC E:Enginering Sample 89C51CC02 ( 16 Kbytes Flash ) Conditioning S: Stick T: Tray 136 -M: VCC: 5V 40 MHz, X1 mode 20 MHz, X2 mode -L: VCC: 3V 40 MHz, X1 mode 20 MHz, X2 mode Rev.
T89C51CC02 Table 31. Possible order entries Extension -SISIM -TISIM -TDSIM -6KSIM -SISIL -TISIL -TDSIL -6KSIL -SISEM -TISEM Type Stick, Stick, Stick, Stick, Stick, Stick, Stick, Stick, Stick, Stick, PLCC28, Ind, 5V SOIC28, Ind, 5V SOIC24, Ind, 5V TSSOP28, Ind, 5V PLCC28, Ind, 3V SOIC28, Ind, 3V SOIC24, Ind, 3V TSSOP28, Ind, 3V PLCC28, Sample SOIC28, Sample Rev.
