Owner manual
73 Rev. F - 15 February, 2001
T89C51RD2
9.4. DC Parameters for Low Voltage
TA =0°Cto+70°C; V
SS
=0V;V
CC
=2.7Vto3.6V;F=0to25MHz.
TA = -40°Cto+85°C; V
SS
=0V;V
CC
=2.7Vto3.6V;F=0to25MHz.
Table 37. DC Parameters for Low Voltage
NOTES
1. Operating I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns (see Figure 27.), V
IL
= V
SS
+ 0.5 V,
V
IH
= V
CC
- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V
CC
. I
CC
would be slightly higher if a crystal oscillator used (see Figure 24.).
2. Idle I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
,T
CHCL
= 5 ns, V
IL
=V
SS
+ 0.5 V, V
IH
=V
CC
- 0.5 V; XTAL2
N.C; Port 0 = V
CC
; EA = RST = V
SS
(see Figure 25.).
3. Power Down I
CC
is measured with all output pins disconnected; EA=V
SS
,PORT0=V
CC
; XTAL2 NC.; RST = V
SS
(see Figure 26.). In addition,
the WDT must be inactive and the POF flag must be set.
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
OL
s of ALE and Ports 1 and 3. The noise is
due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi V
OL
peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature..
6. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin: 10 mA
Maximum I
OL
per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I
OL
for all output pins: 71 mA
If I
OL
exceedsthe test condition, V
OL
may exceed the relatedspecification. Pins arenot guaranteed to sink current greaterthanthe listed test conditions.
Symbol Parameter Min
Typ
(5)
Max Unit Test Conditions
V
IL
Input Low Voltage -0.5 0.2 V
CC
- 0.1 V
V
IH
Input High Voltage except XTAL1, RST 0.2 V
CC
+ 0.9 V
CC
+ 0.5 V
V
IH1
Input High Voltage, XTAL1, RST 0.7 V
CC
V
CC
+ 0.5 V
V
OL
Output Low Voltage, ports 1, 2, 3, 4 and 5
(6)
0.45 V
I
OL
= 0.8 mA
(4)
V
OL1
Output Low Voltage, port 0, ALE, PSEN
(6)
0.45 V
I
OL
= 1.6 mA
(4)
V
OH
Output High Voltage, ports 1, 2, 3, 4 and 5 0.9 V
CC
V I
OH
= -10 µA
V
OH1
Output High Voltage, port 0, ALE, PSEN 0.9 V
CC
V I
OH
= -40 µA
I
IL
Logical 0 Input Current ports 1, 2, 3, 4 and 5 -50 µA Vin = 0.45 V
I
LI
Input Leakage Current ±10 µA 0.45 V < Vin < V
CC
I
TL
Logical 1 to 0 Transition Current, ports 1, 2, 3,
4 and 5
-650 µA Vin = 2.0 V
R
RST
RST Pulldown Resistor 50 90 200 kΩ
CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz
T
A = 25°C
I
PD
Power Down Current 1 50 µA
V
CC
= 2.7 V to 3.6 V
(3)
I
CCOP
Power Supply Current on normal mode 0.6 Freq
(MHz)+3mA
mA
V
CC
= 3.6 V
(1)
I
CCIDLE
Power Supply Current on idle mode 0.3 Freq
(MHz)+2mA
mA
V
CC
= 3.6 V
(2)