Features • Minimal External Circuitry Requirements, No RF Components on the PC Board Except • • • • • • • • • • • • • • Matching to the Receiver Antenna High Sensitivity, Especially at Low Data Rates Sensitivity Reduction Possible Even While Receiving Fully Integrated VCO Low Power Consumption Due to Configurable Self Polling with a Programmable Time Frame Check Supply Voltage 4.5 V to 5.
System Block Diagram UHF ASK/FSK Remote control receiver UHF ASK/FSK Remote control transmitter 1 Li cell U2741B Encoder ATARx9x U3741BM Demod Control 1...3 µC PLL Antenna Antenna Keys XTO VCO PLL Power amp.
U3741BM Pin Configuration Figure 1.
RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1-MHz IF signal. According to the block diagram, the front end consists of an LNA (low noise amplifier), LO (local oscillator), a mixer and RF amplifier. The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) generates the drive voltage frequency fLO for the mixer.
U3741BM To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter’s corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and fLO that depends on the logic level at pin mode. This is described by the following formulas: f LO MODE = 0 (USA) f IF = --------314 fLO MODE = 0 (Europe) f IF = ----------------432.
Figure 3. Input Matching Network with SAW Filter 8 8 LNAGND L C3 9 C3 LNA_IN C16 100p fRF = 433.92 MHz 27n L2 TOKO LL2012 F33NJ RFIN L3 1 33n C2 2 C16 8.2p 100p OUT OUT_GND f RF = 315 MHz 3, 4 22p TOKO LL2012 F47NJ L2 TOKO LL2012 F82NJ RFIN 5 47n 1 6 C2 82n 2 B3551 IN IN_GND CASE_GND 8.2p C17 L3 TOKO LL2012 27NJ IN_GND LNA_IN 25n C17 B3555 IN 9 L 47p 25n 22p LNAGND U3741BM U3741BM 5 OUT 6 OUT_GND CASE_GND 10p 7, 8 3, 4 7, 8 Figure 4.
U3741BM Analog Signal Processing IF Amplifier The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or fRF = 433.92 MHz is used. For other RF input frequencies, refer to Table 1 to determine the center frequency. The U3741BM is available with 2 different IF bandwidths.
FSK/ASK Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK. Logic 'L' sets the demodulator to FSK, Logic 'H' sets it into ASK mode. In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal-to-noise ratio is achieved.
U3741BM Receiving Characteristics The RF receiver U3741BM can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front end-filter is illustrated in Figure 6. This example relates to ASK mode and the 300-kHz bandwidth version of the U3741BM. FSK mode and the 600-kHz version of the receiver exhibit similar behavior. Note that the mirror frequency is reduced by 40 dB.
Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected the receiver remains active and transfers the data to the connected microcontroller.
U3741BM • USA Applications (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs) • Europe Applications (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs) • Other applications (TClk is dependent on fXTO and on the logical state of pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined in the OPMODE register.
XSleepStd = 1 implies the standard extension factor. The sleep time is always extended. XSleepTemp = 1 implies the temporary extension factor. The extended sleep time is used as long as every bit check is OK. If the bit check fails once, this bit is set back to 0 automatically resulting in a regular sleep time. This functionality can be used to save current in presence of a modulated disturber similar to an expected transmitter signal. The connected microcontroller is rarely activated in that condition.
U3741BM Figure 9. Timing Diagram for a Completely Successful Bit Check Number of Checked Bits: 3 Bit check ok Enable IC Bit check 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit Dem_out DATA Polling mode Receiving mode Bit Check Mode In bit check mode, the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise.
The bit check limits are determined by means of the formula below: TLim_min = Lim_min × TXClk TLim_max = (Lim_max –1) × TXClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using the above formulas, Lim_min and Lim_max can be determined according to the required TLim_min , TLim_max and TXClk. The time resolution when defining TLim_min and TLim_max is TXClk.
U3741BM Figure 13. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max) (Lim_min = 14, Lim_max = 24) Bit check failed (CV_Lim = Lim_max) Enable IC Bit check 1/2 Bit Dem_out Bit check Counter 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 1112 13141516171819 20 21222324 0 Startup Mode Duration of the Bit Check Bit check Mode 0 Sleep Mode If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator delivers random signals.
Figure 14. Synchronization of the Demodulator Output TXClk Clock Bitcheck counter Dem_out DATA tee Figure 15. Debouncing of the Demodulator Output Dem_out DATA Lim_min ≤ CV_Lim < Lim_max tmin1 tee CV_Lim < Lim_min or CV_Lim ≥ Lim_max tmin2 tee Figure 16.
U3741BM If the receiver is set to polling mode via pin ENABLE, an ‘L’ pulse (TDoze) must be issued at that pin. Figure 18 illustrates the timing of that command. After the positive edge of this pulse, the sleep time TSleep elapses. The receiver remains in sleep mode as long as ENABLE is held to ‘L’. If the receiver is polled exclusively by a microcontroller, TSleep can be programmed to 0 to enable a instantaneous response time.
Table 2. Effect of Bit 1 and Bit 2 in Programming the Registers Bit 1 Bit 2 Action 1 x The receiver is set back to polling mode (OFF command) 0 1 The OPMODE register is programmed 0 0 The LIMIT register is programmed Table 4 and the following illustrate the effect of the individual configuration words. The default configuration is highlighted for each word. BR_Range sets the appropriate baud rate range. At the same time it defines XLim.
U3741BM Table 5. Effect of the Configuration Word NBitcheck NBitcheck BitChk1 BitChk0 Number of Bits to be Checked 0 0 0 0 1 3 1 0 6 (Default) 1 1 9 Table 6. Effect of the Configuration Bit VPOUT VPOUT Level of the Multi-purpose Output Port POUT POUT 0 0 (Default) 1 1 Table 7.
Table 9. Effect of the Configuration Word Lim_min Lim_min Lower Limit Value for Bit Check Lim_min < 10 is not applicable (TLim_min = Lim_min × XLim × TClk) 0 0 1 0 1 0 10 0 0 1 0 1 1 11 0 0 1 1 0 0 12 0 0 1 1 0 1 13 0 0 1 1 1 0 14 (Default) (USA: TLim_min = 228 µs, Europe: TLim_min = 232 µs) . . . . . . . . . . . . . . . . . . 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63 Table 10.
U3741BM • fRM is lower than the lowest feasible frequency of a data signal. By this means, RM cannot be misinterpreted by the connected microcontroller. • If the receiver is set back to polling mode via pin DATA, RM cannot be canceled by accident if t1 is applied according to the proposal in the section “Programming the Configuration Register” on page 21. By means of that mechanism, the receiver cannot lose its register information without communicating that condition via the reset marker RM. Figure 19.
To start programming, the serial data line DATA is pulled to ‘L’ for the time period t1 by the microcontroller. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5.
U3741BM Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Max.
Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C) 6.76438-Mhz Osc. (Mode 1) Parameter Test Condition Symbol Min. Typ. Max. 4.90625-Mhz Osc. (Mode 0) Min. Typ. Max. Variable Oscillator Min. Typ. Max.
U3741BM Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C) 6.76438-Mhz Osc. (Mode 1) Parameter Test Condition Symbol Min. Typ. Max. 4.90625-Mhz Osc. (Mode 0) Min. Typ. Max. Variable Oscillator Min. Typ. Max. Unit Delay until the program window starts (Figure 17, Figure 20) t4 131 129 63.
Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C) Parameters Test Conditions Maximum input level Input matched according to Figure 4, BER ≤10-3, ASK mode Symbol Min. Typ. Max. Unit -28 -20 dBm dBm 449 MHz -93 -113 -90 -110 dBC/Hz dBC/Hz -55 -47 dBC Pin_max Local Oscillator Operating frequency range VCO fVCO Phase noise VCO/LO fosc = 432.
U3741BM Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C) Parameters Test Conditions Input sensitivity ASK 600 kHz IF filter Min. Typ. Max. Unit BR_Range0 -108 -110 -112 dBm Input sensitivity ASK 600 kHz IF filter BR_Range1 -106.5 -108.5 -110.
Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.
U3741BM Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max.
Ordering Information Extended Type Number Package Remarks U3741BM-P2FL SO20 2: IF bandwidth of 300 kHz, tube U3741BM-P2FLG3 SO20 2: IF bandwidth of 300 kHz, taped and reeled U3741BM-P3FL SO20 3: IF bandwidth of 600 kHz, tube U3741BM-P3FLG3 SO20 3: IF bandwidth of 600 kHz, taped and reeled Package Information 9.15 8.65 Package SO20 Dimensions in mm 12.95 12.70 7.5 7.3 2.35 0.25 0.25 0.10 0.4 10.50 10.20 1.27 11.
U3741BM Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Changes from Rev. 4662A - 06/03 to Rev. 4662B - 10/04 1. Put datasheet in a new template. 2. Heading rows at Table “Absolute Maximum Ratings” added. 3. Table “Ordering Information” on page 30 changed.
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