Features • IC Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal Strength Indicator) Output • Minimal External Circuitry Requirements, No RF Components on the PC Board Except • • • • • • • • • • • • Matching to the Receiver Antenna High Sensitivity, Especially at Low Data Rates Sensitivity Reduction Possible Even While Receiving Fully Integrated VCO Low Power Consumption Due to Configurable Self-polling with a Programmable Time Frame Check Supply Voltage 4.5 V to 5.
Figure 1. System Block Diagram 1 Li cell UHF ASK/FSK Remote control receiver U3742BM U2741B Demod. Keys Encoder ATARx9x Control PLL 1...3 Microcontroller UHF ASK/FSK Remote control transmitter IF Amp Antenna Antenna XTO VCO PLL Power amp. LNA XTO VCO Figure 2. Block Diagram FSK/ASKDemodulator and data filter FSK/ASK CDEM RSSI VS Dem_out 50 kΩ DATA Limiter out RSSI ENABLE SENS IF Amp AVCC Sensitivity reduction Polling circuit and control logic TEST AGND MODE 4.
U3742BM Pin Configuration Figure 3.
Pin Description (Continued) Pin Symbol Function 16 MODE 17 RSSI Output of the RSSI amplifier 18 TEST Test pin, during operation at GND 19 ENABLE 20 DATA Selecting 433.92 MHz/315 MHz Low: 4.90625 MHz (USA) High: 6.76438 (Europe) Enables the polling mode Low: polling mode off (sleep mode) High: polling mode on (active mode) Data output/configuration input RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1 MHz IF signal.
U3742BM The passive loop filter connected to pin LF is designed for a loop bandwidth of BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of the LO. Figure 4 on page 4 shows the appropriate loop filter components to achieve the desired loop bandwidth. If the filter components are changed for any reason, please note that the maximum capacitive load at pin LF is limited.
Table 1. Calculation of LO and IF Frequency Conditions Local Oscillator Frequency Intermediate Frequency fRF = 315 MHz, MODE = 0 fLO = 314 MHz fIF = 1 MHz fRF = 433.92 MHz, MODE = 1 fLO = 432.92 MHz fIF = 1 MHz 300 MHz < fRF < 365 MHz, MODE = 0 fRF fLO = ------------------1 1 + ---------314 f LO fIF = --------314 365 MHz < fRF < 450 MHz, MODE = 1 f RF fLO = --------------------------1 1 + -----------------432.92 f LO fIF = ----------------432.92 Figure 5.
U3742BM Please note that for all coupling conditions (see Figure 5 on page 6 and Figure 6 on page 6), the bond wire inductivity of the LNA ground is compensated. C3 forms a series resonance circuit together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its value is not critical but must be large enough not to detune the series resonance circuit. For cost reduction, this inductor can be easily printed on the PCB.
Figure 7. Temperature Compensation of VRSSI V RSSI_temp_comp. I ~ Ig(VLNA_IN) 180k RSSI B min = 60 50k I V RSSI 47k U3742BM Figure 8. RSSI Characteristic 1.6 1.5 1.4 max VRSSI (V) 1.3 1.2 1.1 1.0 -40°C 0.9 25°C 0.8 0.7 min 105°C 0.6 0.5 -110 -100 -90 -80 -70 -60 -50 PRef (dBm) If RSense is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of RSense, the maximum sensitivity by the signal-tonoise ratio of the LNA input.
U3742BM Figure 9. Steady L State Limited DATA Output Pattern DATA tmin2 FSK/ASK Demodulator and Data Filter tDATA_L_max The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK. Logic 'L' sets the demodulator to FSK, Logic 'H' sets it into ASK mode.
Receiving Characteristics The RF receiver U3742BM can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front-end filter is illustrated in Figure 10. This example relates to ASK mode. FSK mode exhibits similar behavior. Note that the mirror frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitivity.
U3742BM Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry and the analog filtering is derived from one clock. According to Figure 11, this clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divider. The division factor is controlled by the logical state at pin MODE.
Polling Mode According to Figure 13 on page 14, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode, the signal processing circuitry is disabled for the time period TSleep while consuming low current of IS = ISoff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bit check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal.
U3742BM Bit Check Mode In bit check mode, the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum count of these edge-to-edge tests, before the receiver switches to receiving mode, is also programmable.
Figure 13. Polling Mode Flow Chart Sleep mode: All circuits for signal processing are disabled. Only XTO and polling logic are enabled. IS = ISoff Sleep: 5-bit word defined by Sleep0 to Sleep4 in OPMODE register XSleep: Extension factor defined by XSleepStd and XSleepTemp according to Table 8 TSleep = Sleep × XSleep × 1024 × TClk TCLK: Start-up mode: The signal processing circuits are enabled. After the start-up time (TStartup) all circuits are in stable condition and ready to receive.
U3742BM Figure 14. Timing Diagram for Complete Successful Bit Check (Number of checked bits: 3) Bit check ok Enable IC Bit check 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit Dem_out DATA Bit check mode Startup mode Receiving mode Figure 15.
Figure 17. Timing Diagram for Failed Bit Check (Condition: CV_Lim ³ Lim_max) (Lim_min = 14, Lim_max = 24) Bit check failed (CV_Lim ≥ Lim_max) Enable IC Bit check 1/2 Bit Dem_out 0 Bit check counter Startup mode 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 1011121314151617181920 21222324 Bit check mode 0 Sleep mode Figure 15 to Figure 17 illustrate the bit check for the default bit check limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during TStartup.
U3742BM The minimum time period between two edges of the data signal is limited to tee ³ TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time, it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. TDATA_min is to some extent affected by the preceding edge-to-edge time interval tee as illustrated in Figure 19.
After the end of data transmission, the receiver remains active and random noise pulses appear at pin DATA. The edge-to-edge time period tee of the majority of these noise pulses is equal to or slightly higher than TDATA_min. Switching the Receiver Back to Sleep Mode The receiver can be set back to polling mode via pin DATA or via pin ENABLE. When using pin DATA, this pin must be pulled to Low for the period t1 by the connected microcontroller.
U3742BM Figure 22. Timing Diagram of the OFF-command via Pin ENABLE TSleep TDoze toff ENABLE DATA (U3742BM) X Serial bi-directional data line X Receiving mode Configuration of the Receiver Startup mode The U3742BM receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port.
Table 3.
U3742BM Table 7. Effect of the Configuration Word Sleep Sleep Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 Start Value for Sleep Counter (TSleep = Sleep × Xsleep × 1024 × TClk) 0 0 0 0 0 0 (Receiver is continuously polling until a valid signal occurs) 0 0 0 0 1 1 (TSleep » 2ms for XSleep = 1 in US/European applications) 0 0 0 1 0 2 0 0 0 1 1 3 . . . . . . . . . . . . . . . . . . 0 1 0 1 1 11 (USA: TSleep = 22.96 ms, Europe: TSleep = 23.31 ms) (Default) . . . . . . . . . .
Table 10. Effect of the Configuration Word Lim_max Lim_max Upper Limit Value for Bit Check Lim_max < 12 is not applicable (TLim_max = (Lim_max - 1) × XLim × TClk) 0 0 1 1 0 0 12 0 0 1 1 0 1 13 0 0 1 1 1 0 14 . . . . . . . . . . . . . . . . . . 0 1 1 0 0 0 . . . . . . . . . . . . . . . . . .
U3742BM Figure 24. Timing of the Register Programming t1 t2 t3 t5 t4 t9 TSleep t8 t6 t7 Out1 (microcontroller) DATA (U3742BM) X Serial bi-directional data line X Receiving mode Programming the Configuration Register Bit 1 ("0") (Startbit) Bit 2 ("1") (Registerselect) Programming frame Bit 13 ("0") (Poll8) Bit 14 ("1") (Poll8R) Startup mode The configuration registers are programmed serially via the bi-directional data line according to Figure 24 and Figure 25. Figure 25.
During programming, the LNA, LO, low-pass filter, IF-amplifier and the FSK/ASK Manchester demodulator are disabled. The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to '1', it represents the OFF-command to set the receiver back to polling mode at the same time.
U3742BM Electrical Characteristics All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C) Parameter Test Condition Symbol 6.76438 Mhz Oscillator (Mode 1) 4.90625 Mhz Oscillator (Mode 0) Min. Min. Typ. Max. Typ. Max. Variable Oscillator Min. Typ. Max.
Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C) Parameter Test Condition BR_Range0 Maximum low BR_Range1 period at DATA BR_Range2 (Figure 20) BR_Range3 OFF command at pin ENABLE (Figure 22) Symbol 6.76438 Mhz Oscillator (Mode 1) 4.90625 Mhz Oscillator (Mode 0) Min. Min. Max. 2169 1085 542 271 TDATA_L_max tDoze Typ. Typ. Max.
U3742BM Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C) Parameter Test Condition Symbol 6.76438 Mhz Oscillator (Mode 1) 4.90625 Mhz Oscillator (Mode 0) Min. Min. Typ. Max. Typ. Max. Variable Oscillator Min. Typ. Max.
Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C) Parameters Test Conditions Loop bandwidth of the PLL For best LO noise (design parameter) R1 = 820 W C9 = 4.7 nF C10 = 1 nF BLoop Capacitive load at pin LF The capacitive load at pin LF is limited if bit check is used. The limitation therefore also applies to self-polling.
U3742BM Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C) Parameters Test Conditions Symbol Min. Sensitivity variation FSK for the full operating range compared to Tamb = 25°C, VS = 5 V fin = 433.
Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C) Parameters Reduced sensitivity Reduced sensitivity variation over full operating range Test Conditions Min. Typ. Max. Unit (VS = 5 V, Tamb = 25°C) RSense = 56 kW, fin = 433.92 MHz, -67 -72 -77 dBm RSense = 100 kW, fin = 433.
U3742BM Ordering Information Extended Type Number Package Remarks U3742BM-M3FL SO20 Tube U3742BM-M3FLG3 SO20 Taped and reeled Package Information 9.15 8.65 Package SO20 Dimensions in mm 12.95 12.70 7.5 7.3 2.35 0.25 0.25 0.10 0.4 10.50 10.20 1.27 11.
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