Preliminary W24L257 32K × 8 CMOS STATIC RAM GENERAL DESCRIPTION The W24L257 is a normal-speed, very low-power CMOS static RAM organized as 32768 × 8 bits that operates on a wide voltage range from 3.0V to 3.6V power supply. This device is manufactured using Winbond's high performance CMOS technology. FEATURES • • • • • Low power consumption: − Active: 126 mW (max.) Access time: 70 nS Single 3.
Preliminary W24L257 TRUTH TABLE MODE VDD CURRENT I/O1−I/O8 CS OE WE H X X Not Selected L H H Output Disable High Z IDD L L H Read Data Out IDD L X L Write Data In IDD High Z ISB, ISB1 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential RATING UNIT -0.5 to +4.6 V -0.5 to Allowable Power Dissipation +0.5 V 1.
Preliminary W24L257 Operating Characteristics, continued PARAMETER Standby Power Supply Current SYM. TEST CONDITIONS MIN. MAX. UNIT ISB CS = VIH (min.) or Cycle = min. Duty = 100% - 1 mA ISB1 CS ≥ VDD -0.2V - 15 µA Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 3.3V CAPACITANCE (VDD = 3.3V, TA = 25° C, f = 1 MHz) PARAMETER SYM. CONDITIONS Input Capacitance CIN VIN Input/Output Capacitance CI/O VOUT = 0V = 0V MAX.
Preliminary W24L257 AC Characteristics, continued (VDD = 3.0V to 3.6 V; VSS = 0V; TA (°C) = 0 to 70 for LL, -20 to 85 for LE) Read Cycle PARAMETER SYMBOL W24L257-70LL/LE MIN. MAX.
Preliminary W24L257 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TOH TAA TOH DOUT Read Cycle 2 (Chip Select Controlled) CS1 TACS TCHZ TCLZ D OUT Read Cycle 3 (Output Enable Controlled) T RC Address TAA OE TOH TAOE TOLZ CS TACS DOUT TCHZ TOHZ TCLZ -5- Publication Release Date: May 2000 Revision A1
Preliminary W24L257 Timing Waveforms, continued Write Cycle 1 TWC Address TWR OE TCW CS TAW WE T WP TAS TOHZ (1, 4) DOUT TDW TDH DIN Write Cycle 2 ( OE = VIL Fixed) T WC Address TWR TCW CS TAW WE T WP TAS TOH TWHZ (1, 4) D OUT TDW (2) (3) TOW TDH DIN Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3.
Preliminary W24L257 DATA RETENTION CHARACTERISTICS (TA (°C) = 0 to 70 for LL, -20 to 85 for LE) PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT 2.0 - - V VDD for Data Retention VDR CS ≥ VDD -0.2V Data Retention Current IDDDR CS ≥ VDD -0.2V, VDD = 3V - - 15 µA Chip Deselect to Data Retention Time TCDR See data retention waveform 0 - - nS Operation Recovery Time TR TRC* - - nS * Read Cycle Time DATA RETENTION WAVEFORM VDD 0.9 VDD VDR = > 2V 0.
Preliminary W24L257 BONDING PAD DIAGRAM 6 A4 5 4 A5 A6 3 2 1 30 29 28 27 26 25 24 A7 A12 A14 VDD VDD WEB A13 A8 A9 A11 AC5394 23 7 A3 OEB Y X 8 22 A2 A10 9 10 A1 A0 I/O0 I/O1 I/O2 VSS 11 12 13 14 15 16 17 18 19 20 21 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CSB PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 X -232.25 -351.70 -471.15 -590.60 -710.05 -829.50 -992.79 -992.79 -857.86 -738.41 -594.84 -451.06 -310.67 -171.78 24.45 151.80 298.
Preliminary W24L257 PACKAGE DIMENSIONS 28-pin SOP Wide Body Symbol 28 A A1 A2 b c D E e HE L LE S y θ 15 e1 E HE θ L Detail F 14 1 b Dimension in mm Dimension in Inches Min. Nom. Max. Min. Nom. Max. 2.85 0.112 0.004 0.10 0.093 0.098 2.36 2.49 0.014 0.016 0.020 0.36 0.41 0.51 0.010 0.014 0.20 0.25 0.36 0.713 0.733 18.11 18.62 0.326 0.331 0.336 8.28 8.41 8.53 0.044 0.050 0.056 1.12 1.27 1.42 0.008 0.103 2.62 0.453 0.465 0.477 11.51 11.81 12.12 0.028 0.
Preliminary W24L257 VERSION HISTORY VERSION DATE PAGE A1 May 2000 - Headquarters DESCRIPTION Initial Issued Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd.
