Manual

W27E512
64K × 8 ELECTRICALLY ERASABLE EPROM
Publication Release Date: November 1999
- 1 - Revision A8
GENERAL DESCRIPTION
The W27E512 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 65536
×
8 bits that operates on a single 5 volt power supply. The W27E512
provides an electrical chip erase function.
FEATURES
High speed access time:
45/55/70/90/120/150 nS (max.)
Read operating current: 30 mA (max.)
Erase/Programming operating current
30 mA (max.)
Standby current: 1 mA (max.)
Single 5V power supply
+14V erase/+12V programming voltage
Fully static operation
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available packages: 28-pin 600 mil DIP, 330 mil
SOP, TSOP and 32-pin PLCC
PIN CONFIGURATIONS
26
27
28
1
2
3
4
5
6
7
8
21
22
23
24
25
16
17
18
19
20
9
10
11
12
13
14
15
Q3
CE
Q7
Q6
Q5
Q4
A9
A11
OE/Vpp
A10
A14
A13
A8
GND
Q2
Q1
A0
A1
A2
A3
A4
A5
A6
A7
A12
Q0
V
CC
28-pin
DIP
A15
A6
A5
A4
A3
A2
A1
A0
NC
Q0
5
6
7
8
9
10
11
12
13
1
4
4321
3
2
3
1
3
029
28
27
26
25
24
23
22
21
32-pin
PLCC
Q
1
Q
2
N
C
Q
3
Q
4
Q
5
G
N
D
1
5
1
6
1
7
1
8
1
9
2
0
A
7
N
C
A
1
2
A
1
4
A
1
3
V
C
C
A8
A9
A11
NC
OE/Vpp
A10
Q7
CE
Q6
A
1
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-pin
TSOP
Q3
CE
Q7
Q6
Q5
Q4
A10
GND
Q2
Q1
A0
A1
A2
Q0
A9
A11
OE/Vpp
A14
A13
A8
A3
A4
A5
A6
A7
A12
V
CC
A15
BLOCK DIAGRAM
CE
OE/V
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
Q0
Q7
.
.
A0
.
.
GND
V
CC
PP
A15
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0
A15
Address Inputs
Q0
Q7
Data Inputs/Outputs
CE
Chip Enable
OE
/V
PP
Output Enable, Program/Erase
Supply Voltage
V
CC
Power Supply
GND Ground
NC No Connection

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