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W29C040

512K × 8 CMOS FLASH MEMORY

Publication Release Date: May 1999

- 1 - Revision A5

GENERAL DESCRIPTION

The W29C040 is a 4-megabit, 5-volt only CMOS page mode EEPROM organized as 512K × 8 bits.

The device can be written (erased and programmed) in-system with a standard 5V power supply. A

12-volt VPP is not required. The unique cell architecture of the W29C040 results in fast write (erase/

program) operations with extremely low current consumption compared to other comparable 5-volt

flash memory products. The device can also be written (erased and programmed) by using standard

EPROM programmers.

FEATURES

• Single 5-volt write (erase and program)

operations

• Fast page-write operations

− 256 bytes per page

− Page write (erase/program) cycle: 5 mS

(typ.)

− Effective byte-write (erase/program) cycle

time: 19.5 µS

− Optional software-protected data write

• Fast chip-erase operation: 50 mS

• Two 16 KB boot blocks with lockout

• Typical page write (erase/program) cycles:

1K/10K (typ.)

• Read access time: 90/120 nS

• Ten-year data retention

• Software and hardware data protection

• Low power consumption

− Active current: 25 mA (typ.)

− Standby current: 20 µA (typ.)

• Automatic write (erase/program) timing with

internal VPP generation

• End of write (erase/program) detection

− Toggle bit

− Data polling

• Latched address and data

• All inputs and outputs directly TTL compatible

• JEDEC standard byte-wide pinouts

• Available packages: TSOP and PLCC

Summary of content (20 pages)

PAGE 1
W29C040 512K × 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29C040 is a 4-megabit, 5-volt only CMOS page mode EEPROM organized as 512K × 8 bits. The device can be written (erased and programmed) in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29C040 results in fast write (erase/ program) operations with extremely low current consumption compared to other comparable 5-volt flash memory products.
PAGE 2
W29C040 PIN CONFIGURATIONS BLOCK DIAGRAM VCC VSS CE A 1 2 A 1 5 A A 1 1 6 8 V C C 4 3 2 32 31 30 / W E A 1 7 OE CONTROL WE 1 A7 5 29 A14 A6 6 28 A13 27 A8 A5 7 A4 8 A3 9 A2 32-pin PLCC 26 A9 25 A11 OE A10 10 24 A1 11 23 A0 12 22 DQ0 13 21 16K Byte Boot Block (Optional) A0 . .
PAGE 3
W29C040 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29C040 is controlled by CE and OE , both Chip of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the read cycle timing waveforms for further details.
PAGE 4
W29C040 will remain enabled unless the disable commands are issued. A power transition will not reset the software data protection feature. To reset the device to unprotected mode, a six byte command sequence is required. For information about specific codes, see the Command Codes for Software Data Protection in the Table of Operating Modes. For information about timing waveforms, see the timing diagrams below.
PAGE 5
W29C040 Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W29C040 provides another method for determining the end of a write cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. See Toggle Bit Timing Diagram.
PAGE 6
W29C040 Command Codes for Software Data Protection BYTE SEQUENCE TO ENABLE PROTECTION TO DISABLE PROTECTION ADDRESS DATA 0 Write 5555H AAH ADDRESS 5555H AAH 1 Write 2AAAH 55H 2AAAH 55H 2 Write 5555H A0H 5555H 80H 3 Write - - 5555H AAH 4 Write - - 2AAAH 55H 5 Write - - 5555H 20H Software Data Protection Acquisition Flow Software Data Protection Enable Flow (Optional page-load operation) Software Data Protection Disable Flow Load data AA to address 5555 Load data AA to a
PAGE 7
W29C040 Command Codes for Software Chip Erase BYTE SEQUENCE ADDRESS DATA 0 Write 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H 80H 3 Write 5555H AAH 4 Write 2AAAH 55H 5 Write 5555H 10H Software Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause 50 mS Exit Notes for software chip erase: Data Format: DQ7−DQ0 (Hex) Address Format: A
PAGE 8
W29C040 Command Codes for Product Identification and Boot Block Lockout Detection BYTE SEQUENCE ALTERNATE PRODUCT (7) IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT ADDRESS DATA ADDRESS DATA ADDRESS DATA 0 Write 5555 AA 5555H AAH 5555H AAH 1 Write 2AAA 55 2AAAH 55H 2AAAH 55H 2 Write 5555 90 5555H 80H 5555H F0H 3 Write - - 5555H AAH - -
PAGE 9
W29C040 Command Codes for Boot Block Lockout Enable BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET ON FIRST 16K ADDRESS BOOT BLOCK ADDRESS DATA BOOT BLOCK LOCKOUT FEATURE SET ON LAST 16K ADDRESS BOOT BLOCK ADDRESS DATA 0 Write 5555H AAH 5555H AAH 1 Write 2AAAH 55H 2AAAH 55H 2 Write 5555H 80H 5555H 80H 3 Write 5555H AAH 5555H AAH 4 Write 2AAAH 55H 2AAAH 55H 5 Write 5555H 40H 5555H 40H 6 Write 00000H 00H 3FFFFH FFH Pause 10 mS Pause 10 mS Boot Block Lockout Enable Acqui
PAGE 10
W29C040 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V 0 to +70 °C -65 to +150 °C D.C. Voltage on Any Pin to Ground Potential Except A9 -0.5 to VDD +1.0 V Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V -0.5 to 12.
PAGE 11
W29C040 Power-up Timing PARAMETER SYMBOL Power-up to Read Operation TPU. READ Power-up to Write Operation TPU. WRITE TYPICAL UNIT 100 µS 10 mS CAPACITANCE (VDD = 5.0V, TA = 25° C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS MAX. UNIT DQ Pin Capacitance CDQ VDQ = 0V 12 pF Input Pin Capacitance CIN VIN = 0V 6 pF AC CHARACTERISTICS AC Test Conditions (VDD = 5.
PAGE 12
W29C040 AC Characteristics, continued Read Cycle Timing Parameters (VDD = 5.0V ±10% for 90,120 and 150 nS, VSS = 0V, TA = 0 to 70° C) PARAMETER SYM. W29C040-90 W29C040-12 MIN. MAX. MIN. MAX.
PAGE 13
W29C040 AC Characteristics, continued DATA Polling Characteristics (1) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Data Hold Time TDH 10 - - nS OE Hold Time TOEH 10 - - nS OE to Output Delay (2) TOE - - - nS Write Recovery Time TWR 0 - - nS SYMBOL MIN. TYP. MAX.
PAGE 14
W29C040 Timing Waveforms, continued WE Controlled Write Cycle Timing Diagram TWC TAS TAH Address A18-0 CE TCS TCH TOES T OEH OE TWP WE TWPH TDS DQ7-0 Data Valid TDH Internal write starts CE Controlled Write Cycle Timing Diagram T AS T WC T AH Address A18-0 T WPH T CP CE T OES OE T OEH TCS TCH WE T DS DQ7-0 High Z Data Valid T DH Internal Write Starts - 14 -
PAGE 15
W29C040 Timing Waveforms, continued Page Write Cycle Timing Diagram TWC Address A18-0 DQ7-0 CE OE TWP TWPH TBLC WE Byte 1 Byte 0 Byte 2 Byte N-1 Byte N Internal Write Start DATA Polling Timing Diagram Address A18-0 WE CE TOEH OE TDH DQ7 TWR TOE HIGH-Z - 15 - Publication Release Date: May 1999 Revision A5
PAGE 16
W29C040 Timing Waveforms, continued Toggle Bit Timing Diagram WE CE OE TOEH TDH TOE TWR HIGH-Z DQ6 Page Write Timing Diagram Software Data Protection Mode Address A18-0 2AAA 5555 DQ7-0 AA TWC Byte/page load cycle starts Three-byte sequence for software data protection mode 5555 55 A0 CE OE TBLC TWP WE TWPH SW0 SW1 SW2 Byte 0 Byte N-1 Byte N (Last Byte) Internal write starts - 16 -
PAGE 17
W29C040 Timing Waveforms, continued Reset Software Data Protection Timing Diagram Six-byte sequence for resetting software data protection mode Address A18-0 5555 2AAA 5555 DQ7-0 AA 55 80 5555 AA TWC 2AAA 5555 55 20 SW4 SW5 CE OE TWP TBLC WE TWPH SW0 SW2 SW1 SW3 Internal programming starts 5 Volt-only Software Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A18-0 DQ7-0 5555 2AAA 5555 AA 55 80 5555 AA TWC 2AAA 5555 55 10 SW4 SW5 CE
PAGE 18
W29C040 ORDERING INFORMATION PART NO. ACCESS POWER STANDBY TIME SUPPLY CURRENT VDD CURRENT (nS) MAX. (mA) MAX. (µA) PACKAGE CYCLING W29C040T-90 90 50 100 Type one TSOP 1K W29C040T-12 120 50 100 Type one TSOP 1K W29C040P-90 90 50 100 32-pin PLCC 1K W29C040P-12 120 50 100 32-pin PLCC 1K W29C040T-90B 90 50 100 Type one TSOP 10K W29C040T-12B 120 50 100 Type one TSOP 10K W29C040P-90B 90 50 100 32-pin PLCC 10K W29C040P-12B 120 50 100 32-pin PLCC 10K Notes: 1.
PAGE 19
W29C040 PACKAGE DIMENSIONS 32-pin PLCC HE E 4 1 32 30 Symbol 5 29 A A1 A2 b1 b c D E e GD GE HD HE L y θ GD D HD 21 13 14 c 20 Dimension in Inches Min. Nom. Max. Dimension in mm Min. Nom. Max. 0.140 0.020 3.56 0.50 0.105 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.46 0.018 0.022 0.41 0.008 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 0.447 0.450 0.453 11.35 11.43 11.51 0.044 0.050 0.056 1.12 1.27 1.
PAGE 20
W29C040 VERSION HISTORY VERSION DATE PAGE A1 Apr. 1997 - A2 Nov. 1997 4, 8 A4 A5 June 1998 Oct. 1998 May 1999 Initial Issued Correct the address from 3FFF2 to 7FFF2 9 Correct the boot block from 8K to 16K 15 Modify page write cycle timing diagram waveform 1, 18 A3 DESCRIPTION Delete cycling 100K item 6 Add. pause 10 mS 7 Add. pause 50 mS 8 Correct the time from 10 mS to 10 µS 4 Correct power-on delay from 5 mS to 10 mS 11 Correct TPU.WRITE (Typ.