W29EE512 64K × 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29EE512 is a 512K bit, 5-volt only CMOS flash memory organized as 64K × 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29EE512 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products).
W29EE512 PIN CONFIGURATIONS A 1 2 A 1 5 N C V / N C W N C C E C 4 3 2 1 32 31 30 BLOCK DIAGRAM VDD VSS A7 5 29 A14 A6 6 28 A13 A5 7 27 A8 A4 8 A3 9 A2 A1 32-pin PLCC A9 25 A11 10 24 11 23 OE A10 A0 12 22 DQ0 13 CE DQ7 D Q 3 D D Q Q 4 5 OUTPUT BUFFER . . DQ7 A0 14 15 16 17 18 19 20 D D G Q Q N 1 2 D DQ0 CONTROL WE 26 21 CE OE . D Q 6 DECODER .
W29EE512 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29EE512 is controlled by CE and OE , both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details.
W29EE512 Hardware Data Protection The integrity of the data stored in the W29EE512 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VCC Power Up/Down Detection: The programming operation is inhibited when VCC is less than 2.5V. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods.
W29EE512 TABLE OF OPERATING MODES Operating Mode Selection (Operating Range = 0 to 70° C (Ambient Temperature), VCC = 5V ±10%, VSS = 0V, VHH = 12V) MODE PINS ADDRESS DQ.
W29EE512 Command Codes for Software Data Protection BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write TO ENABLE PROTECTION TO DISABLE PROTECTION ADDRESS DATA ADDRESS DATA 5555H 2AAAH 5555H - AAH 55H A0H - 5555H 2AAAH 5555H 5555H 2AAAH 5555H AAH 55H 80H AAH 55H 20H Software Data Protection Acquisition Flow Software Data Protection Enable Flow Load data AA to address 5555 (Optional page-load operation) Software Data Protection Disable Flow Load data AA to address 5555 Load data 55 to
W29EE512 Command Codes for Software Chip Erase BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H Software Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause 50 mS Exit Notes for software chip erase: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) -7-
W29EE512 Command Codes for Product Identification BYTE SEQUENCE ALTERNATE SOFTWARE (5) PRODUCT IDENTIFICATION ENTRY ADDRESS SOFTWARE PRODUCT IDENTIFICATION ENTRY SOFTWARE PRODUCT IDENTIFICATION EXIT DATA ADDRESS DATA ADDRESS 0 Write 5555H AAH 5555H AAH 5555H DATA 1 Write 2AAAH 55H 2AAAH 55H 2AAAH 55H 2 Write 5555H 90H 5555H 80H 5555H F0H AAH 3 Write - - 5555H AAH - - 4 Write - - 2AAAH 55H - - 5 Write - - 5555H 60H - Pause 10 µS Pause 10 µS - Pause 10 µS
W29EE512 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V 0 to +70 °C -65 to +150 °C D.C. Voltage on Any Pin to Ground Potential except A9 -0.5 to VCC +1.0 V Transient Voltage (¡ Õ20 nS ) on Any Pin to Ground Potential -1.0 to VCC +1.0 V -0.5 to 12.
W29EE512 Power-up Timing PARAMETER Power-up to Read Operation SYMBOL TPU.READ Power-up to Write Operation TPU.WRITE TYPICAL 100 UNIT 5 µS mS MAX. 12 6 UNIT pF pF CAPACITANCE (VCC = 5.0V, TA = 25° C, f = 1 MHz) PARAMETER I/O Pin Capacitance Input Capacitance SYMBOL CI/O CIN CONDITIONS VI/O = 0V VIN = 0V AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time CONDITIONS 0V to 3V < 5 nS 1.5V/1.
W29EE512 Read Cycle Timing Parameters (VCC = 5.0V ±10%, VCC = 5.0 ±5% for 70 nS, VSS = 0V, TA = 0 to 70° C) PARAMETER SYM. W29EE512-70 W29EE512-90 W29EE512-12 MIN. MAX. MIN. MAX. MIN. MAX.
W29EE512 DATA Polling Characteristics (1) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Data Hold Time TDH 10 - - nS OE Hold Time TOEH 10 - - nS OE to Output Delay (2) TOE - - - nS Write Recovery Time TWR 0 - - nS MIN. TYP. MAX. UNIT Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters.
W29EE512 TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A15-0 TCE CE TOE OE WE TOHZ VIH TOH DQ7-0 TCHZ High-Z High-Z Data Valid Data Valid TAA WE Controlled Write Cycle Timing Diagram TWC TAS TAH Address A15-0 CE TCS TCH TOES T OEH OE WE T WPH TWP TDS DQ7-0 Data Valid TDH Internal write starts - 13 - Publication Release Date: April 2000 Revision A6
W29EE512 Timing Waveforms, continued CE Controlled Write Cycle Timing Diagram TAS TWC TAH Address A15-0 TCPH TCP CE TOES TOEH OE WE TDS DQ7-0 High Z Data Valid TDH Internal write starts Page Write Cycle Timing Diagram TWC Address A15-0 DQ7-0 CE OE TWP TWPH TBLC WE Byte 0 Byte 1 Byte 2 Byte N-1 Internal write starts - 14 - Byte N
W29EE512 Timing Waveforms, continued DATA Polling Timing Diagram Address A15-0 WE CE TOEH OE TDH TWR HIGH-Z TOE DQ7 Toggle Bit Timing Diagram WE CE OE TOEH TDH TOE HIGH-Z TWR DQ6 - 15 - Publication Release Date: April 2000 Revision A6
W29EE512 Timing Waveforms, continued Page Write Timing Diagram Software Data Protection Mode Address A15-0 5555 DQ7-0 AA 2AAA TWC Byte/page load cycle starts Three-byte sequence for software data protection mode 5555 55 A0 CE OE TBLC TWP WE TWPH Word N-1 Word 0 SW2 SW1 SW0 Word N (last word) Internal write starts Reset Software Data Protection Timing Diagram TWC Six-byte sequence for resetting software data protection mode Address A15-0 DQ7-0 5555 2AAA 55 AA 5555 80 5555 AA
W29EE512 Timing Waveforms, continued 5-Volt-only Software Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase TWC Address A15-0 5555 2AAA 5555 DQ7-0 AA 55 80 AA 55 10 SW2 SW3 SW4 SW5 5555 2AAA 5555 CE OE TWP TBLC WE TWPH SW0 SW1 Internal programming starts - 17 - Publication Release Date: April 2000 Revision A6
W29EE512 ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VCC CURRENT MAX.
W29EE512 PACKAGE DIMENSIONS 32-pin PLCC HE E 4 1 32 30 Symbol 5 A A1 A2 b1 b c D E e GD GE HD HE L y 29 G D D HD 21 13 14 c 20 Dimension In mm Dimension In Inches Min. Nom. Max. Min. Nom. Max. 0.140 0.020 3.56 0.50 0.105 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.56 0.008 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 11.35 11.43 11.51 0.447 0.450 0.453 0.044 0.050 0.056 1.12 1.
W29EE512 Package Dimensions, continued 32-pin VSOP HD Dimension In Inches Dimension In mm Symbol D A A A1 M e E Min. Nom. __ __ A1 0.002 Max. 0.047 __ Min. Nom. __ __ 0.006 0.05 0.15 __ Max. 1.20 0.15 b 0.006 0.008 0.010 0.20 0.25 D 0.484 0.488 0.492 12.30 12.40 12.50 E 0.311 0.315 HD 0.543 0.551 0.559 13.80 14.00 14.20 0.319 7.90 8.00 8.10 0.10(0.004) b e __ 0.020 L 0.020 0.024 Y 0.004 θ 0 __ __ __ __ 0.028 0.50 0.008 0.
W29EE512 VERSION HISTORY VERSION DATE PAGE A5 Mar. 1998 6 Add. pause 10 mS 7 Add. pause 50 mS 8 Correct the time from 10 mS to 10 µS A6 Apr. 2000 1, 2, 18, 19 Eliminate 600 mil DIP, 450 mil SOP packages 1, 2, 18, 20 Add 32-pin VSOP package 3, 11 Headquarters DESCRIPTION Change Byte Load Cycle Time from 150 µS to 200 µS Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd.
