W49F002U 256K × 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49F002U results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products).
W49F002U BLOCK DIAGRAM PIN CONFIGURATIONS RESET 1 32 VDD A16 2 31 WE A15 VDD VSS 3 30 A17 A12 4 29 A14 CE A7 5 28 A13 OE A6 6 27 A8 A5 7 A4 8 A3 26 A9 25 A11 9 24 OE A2 10 23 A10 A1 11 22 CE A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 GND 16 17 DQ3 32-pin DIP CONTROL WE A7 A6 / R E S E T 4 3 1 32 31 30 2 V / D W D E .
W49F002U FUNCTIONAL DESCRIPTION Read Mode The read operation of the W49F002U is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details.
W49F002U operation if the boot block programming lockout feature is not activated. Once the boot block lockout feature is activated, the whole chip erase function will erase the two main memory blocks and the two parameter blocks but not the boot block. The device will automatically return to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
W49F002U Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W49F002U provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation.
W49F002U TABLE OF COMMAND DEFINITION(1) COMMAND DESCRIPTION NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr.
W49F002U Command Codes for Byte Program COMMAND SEQUENCE ADDRESS DATA 0 Write 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H A0H 3 Write Programmed-address Programmed-data Byte Program Flow Chart Byte Program Command Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555 Load data Din to programmedaddress Pause TBP Exit Notes for software program code: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) -7- Publication Release Date: April 2000 Revisi
W49F002U Command Codes for Chip Erase BYTE SEQUENCE ADDRESS DATA 1 Write 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 80H 4 Write 5555H AAH 5 Write 2AAAH 55H 6 Write 5555H 10H Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause TEC Exit Notes for chip erase: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) -8-
W49F002U Command Codes for Sector Erase BYTE SEQUENCE ADDRESS DATA 1 Write 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 80H 4 Write 5555H AAH 5 Write 2AAAH 55H 6 Write SA* 30H Sector Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 30 to address SA* Pause TEC Exit Notes for chip erase: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) SA : For details, se
W49F002U Command Codes for Product Identification and Boot Block Lockout Detection BYTE SEQUENCE SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT(6) ADDRESS DATA ADDRESS DATA 1 Write 5555 AA 5555H AAH 2 Write 2AAA 55 2AAAH 55H 3 Write 5555 90 5555H Pause 10 µS F0H Pause 10 µS Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA
W49F002U Command Codes for Boot Block Lockout Enable BYTE SEQUENCE ADDRESS 0 Write 5555H DATA 1 Write 2AAAH 55H 2 Write 5555H 80H 3 Write 5555H AAH 4 Write 2AAAH 55H 5 Write 5555H AAH 40H Pause TBP Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause T BP Exit Notes for boot b
W49F002U DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V 0 to +70 °C -65 to +150 °C D.C. Voltage on Any Pin to Ground Potential except OE -0.5 to VDD +1.0 V Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V -0.5 to 12.
W49F002U Power-up Timing PARAMETER SYMBOL TYPICAL UNIT Power-up to Read Operation TPU. READ 100 µS Power-up to Write Operation TPU. WRITE 5 mS CAPACITANCE (VDD = 5.0V, TA = 25° C, f = 1 MHz) PARAMETER SYMBOL I/O Pin Capacitance Input Capacitance CONDITIONS CI/O CIN VI/O = 0V VIN = 0V MAX. UNIT 12 6 pf pf AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 3.0V Input Rise/Fall Time Input/Output Timing Level Output Load < 5 nS 1.5V/1.
W49F002U AC Characteristics, continued Read Cycle Timing Parameters (VCC = 5.0V ±10%, VCC = 0V, TA = 0 to 70° C) PARAMETER SYM. W49F002U-70 W49F002U-90 W49F002U-120 UNIT MIN. MAX. MIN. MAX. MIN. MAX.
W49F002U AC Characteristics, continued Data Polling and Toggle Bit Timing Parameters PARAMETER SYM. W49F002U-70 W49F002U-90 W49F002U-120 UNIT MIN. MAX. MIN. MAX. MIN. MAX.
W49F002U Timing Waveforms, continued WE Controlled Command Write Cycle Timing Diagram TAS TAH Address A17-0 TCS CE TCH TOES TOEH OE TWP WE TWPH TDS DQ7-0 Data Valid TDH CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A17-0 TCPH TCP CE TOES TOEH OE WE TDS DQ7-0 High Z Data Valid TDH - 16 -
W49F002U Timing Waveforms, continued Program Cycle Timing Diagram Byte Program Cycle Address A17-0 2AAA 5555 55 AA DQ7-0 5555 Address A0 Data-In CE OE T WPH TBP TWP WE Byte 1 Byte 0 Byte 2 Byte 3 Internal Write Start DATA Polling Timing Diagram Address A17-0 An An An An WE TCEP CE TOEH TOES OE TOEP DQ7 X X X X TBP or TEC - 17 - Publication Release Date: April 2000 Revision A2
W49F002U Timing Waveforms, continued Toggle Bit Timing Diagram Address A17-0 WE CE TOES TOEH OE DQ6 TBP orTEC Boot Block Lockout Enable Timing Diagram Six byte code for Boot Block Lockout Feature Enable Address A17-0 DQ7-0 5555 2AAA 5555 AA 55 80 5555 AA 2AAA 5555 55 40 CE OE TWP TEC WE TWPH SB0 SB1 SB2 - 18 - SB3 SB4 SB5
W49F002U Timing Waveforms, continued Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A17-0 5555 DQ7-0 2AAA 55 AA 5555 5555 80 2AAA AA 55 5555 10 CE OE TWP TEC WE TWPH SB0 SB1 SB2 SB3 SB4 SB5 Internal Erase starts Sector Erase Timing Diagram Six-byte code for 5V-only software Main Memory Erase Address A17-0 DQ7-0 5555 2AAA 55 AA 5555 5555 80 AA 2AAA 55 SA 30 CE OE TWP TEC WE TWPH SB0 SB1 SB2 SB3 SB4 SB5 Internal Erase starts
W49F002U ORDERING INFORMATION PART NO. W49F002U-70B ACCESS TIME PACKAGE CYCLE (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VDD CURRENT MAX.
W49F002U PACKAGE DIMENSIONS 32-pin P-DIP Symbol A A1 A2 B B1 c D E E1 e1 L D 17 32 E1 16 E A1 L Base Plane Seating Plane B e1 a 5.33 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.008 0.010 0.014 0.20 0.25 0.36 1.650 1.660 0.600 41.91 42.16 15.49 0.610 14.99 15.24 0.545 0.550 0.555 13.84 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 16.51 17.02 0.590 0 0.630 0.
W49F002U Package Dimensions, continued 32-pin TSOP HD Dimension in mm Dimension in Inches Symbol D A c e E Nom. __ __ Max. Min. Nom. __ __ 0.047 A1 M Min. 0.002 __ 0.006 0.05 __ Max. 1.20 0.15 A2 0.037 0.039 0.041 0.95 1.00 b 0.007 0.008 0.009 0.17 0.20 0.23 c 0.005 0.006 0.007 0.12 0.15 0.17 18.50 1.05 0.10(0.004) b D 0.720 0.724 0.728 18.30 18.40 E 0.311 0.315 0.319 7.90 8.00 8.10 HD 0.780 0.787 0.795 19.80 20.00 20.
W49F002U VERSION HISTORY VERSION DATE PAGE A1 Nov. 1999 - A2 Apr. 2000 1, 13−15, 20 14 DESCRIPTION Renamed from W49F002/B/U/N Add the 120 nS bin Change Tbp(typ.) from 10 µS to 35 µS Change Tec(max.) from 1 Sec to 0.2 Sec Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd.
