Preliminary W49F020 256K × 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W49F020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49F020 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products).
Preliminary W49F020 BLOCK DIAGRAM PIN CONFIGURATIONS NC 1 32 VDD A16 2 31 WE A15 3 30 A12 4 29 A17 A14 A7 5 28 A13 A6 6 27 A8 26 A9 W49F020 V DD VSS A5 7 A4 8 25 A11 A3 9 24 A2 10 23 OE A10 CE OE WE 32-pin DIP A1 11 22 CE A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ2 15 18 DQ4 GND 16 17 DQ3 OUTPUT BUFFER CONTROL 3FFFF DQ5 A0 . MAIM MEMORY 248K BYTES DECODER .
Preliminary W49F020 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W49F020 is controlled by CE and OE , both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details.
Preliminary W49F020 TBP) when completing programming and return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. Hardware Data Protection The integrity of the data stored in the W49F020 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse with less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 2.5V typical.
Preliminary W49F020 TABLE OF OPERATING MODES Operating Mode Selection (VHH = 12V ± 5%) MODE Read Write Standby Write Inhibit CE VIL VIL VIH X X OE VIL VIH X VIL X WE VIH VIL X X VIH Output Disable Product ID X VIL VIH VIL X VIH VIL VIL VIH PINS ADDRESS DQ. AIN AIN X X X Dout Din High Z High Z/DOUT High Z/DOUT X A0 = VIL; A1−A17 = VIL; A9 = VHH A0 = VIL; A1−A17 = VIL; A9 = VHH High Z Manufacturer Code DA (Hex) Device Code 8C (Hex) TABLE OF COMMAND DEFINITION COMMAND DESCRIPTION NO.
Preliminary W49F020 Command Codes for Byte Program WORD SEQUENCE ADDRESS DATA 0 Write 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H A0H 3 Write Programmed-Address Programmed-Data Byte Program Flow Chart Byte Program Command Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555 Load data Din to programmedaddress Pause 50 µ S Exit Notes for software program code: Data Format: DQ7−DQ0 (Hex Address Format: A14−A0 (Hex) -6-
Preliminary W49F020 Command Codes for Chip Erase BYTE SEQUENCE ADDRESS DATA 1 Write 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 80H 4 Write 5555H AAH 5 Write 2AAAH 55H 6 Write 5555H 10H Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause 1 Sec.
Preliminary W49F020 Command Codes for Product Identification and Boot Block Lockout Detection BYTE SEQUENCE SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT (7) ALTERNATE PRODUCT (6) IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS DATA ADDRESS DATA 1 Write 5555 2 Write 2AAA AA 5555H AAH 55 2AAAH 3 Write 5555 55H 90 5555H F0H Pause 10 µS Pause 10 µS Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry
Preliminary W49F020 Command Codes for Boot Block Lockout Enable BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET ADDRESS DATA 1 Write 5555H 2 Write 2AAAH AAH 55H 3 Write 5555H 80H 4 Write 5555H AAH 5 Write 2AAAH 55H 6 Write 5555H 40H Pause 1 Sec.
Preliminary W49F020 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V 0 to +70 °C -65 to +150 °C D.C. Voltage on Any Pin to Ground Potential except OE -0.5 to VDD +1.0 V Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V -0.5 to 12.
Preliminary W49F020 Power-up Timing TYPICAL UNIT Power-up to Read Operation PARAMETER TPU. READ SYMBOL 100 Power-up to Write Operation TPU. WRITE 5 µS mS CAPACITANCE (VDD = 5.0V, TA = 25° C, f = 1 MHz) PARAMETER I/O Pin Capacitance Input Capacitance SYMBOL C I/O CIN CONDITIONS VI/O = 0V VIN = 0V MAX. 12 6 UNIT pf pf AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 3.0V < 5 nS 1.5V/1.
Preliminary W49F020 AC Characteristics, continued Read Cycle Timing Parameters (VCC = 5.0V ±10%, VCC = 0V, TA = 0 to 70° C) PARAMETER SYM. W49F020-70 MIN. W49F020-90 MAX. MIN. UNIT MAX.
Preliminary W49F020 AC Characteristics, continued Data Polling and Toggle Bit Timing Parameters PARAMETER SYM. W49F020-70 W49F020-90 MIN. MAX. MIN. MAX.
Preliminary W49F020 Timing Waveforms, continued WE Controlled Command Write Cycle Timing Diagram TAS TAH Address A17-0 CE TCS TCH TOES T OEH OE TWP WE TWPH TDS DQ7-0 Data Valid TDH CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A17-0 TCPH TCP CE TOES TOEH OE WE TDS DQ7-0 High Z Data Valid TDH - 14 -
Preliminary W49F020 Timing Waveforms, continued Program Cycle Timing Diagram Byte Program Cycle Address A17-0 2AAA 5555 55 AA DQ7-0 Address 5555 A0 Data-In CE OE T WPH TBP TWP WE Byte 1 Byte 0 Byte 2 Byte 3 Internal Write Start DATA Polling Timing Diagram Address A17-0 WE TCEP CE TOEH TOES OE TOEP DQ7 X X X X TBP or TEC - 15 - Publication Release Date: October 1999 Revision A1
Preliminary W49F020 Timing Waveforms, continued Toggle Bit Timing Diagram Address A17-0 WE CE TOES TOEH OE DQ6 TBP or TEC Boot Block Lockout Enable Timing Diagram Six byte code for Boot Block Lockout Feature Enable Address A17-0 DQ7-0 5555 2AAA XXAA XX55 5555 5555 XX80 XXAA 2AAA XX55 5555 XX40 CE OE TWP TEC WE TWPH SB0 SB1 SB2 SB3 - 16 - SB4 SB5
Preliminary W49F020 Timing Waveforms, continued Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A17-0 DQ7-0 5555 2AAA XXAA XX55 5555 5555 XX80 XXAA 2AAA XX55 5555 XX10 CE OE TWP TEC WE TWPH SB0 SB1 SB2 SB3 - 17 - SB4 SB5 Internal Erase starts Publication Release Date: October 1999 Revision A1
Preliminary W49F020 ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) W49F020-70 STANDBY VDD CURRENT MAX.
Preliminary W49F020 PACKAGE DIMENSIONS 32-pin P-DIP Symbol A A1 A2 B B1 c D E E1 e1 L D 17 32 E1 16 E A1 L Base Plane Seating Plane B e1 a 5.33 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.008 0.010 0.014 0.20 0.25 0.36 1.650 1.660 0.590 0.600 0.610 14.99 15.24 0.545 0.550 0.555 13.84 41.91 42.16 15.49 13.97 14.10 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.
Preliminary W49F020 Package Dimensions, continued 32-pin TSOP HD Dimension in Inches Dimension in mm Symbol D A c e E Nom. __ __ Max. Min. Nom. __ __ 0.047 A1 M Min. 0.002 __ 0.006 0.05 __ Max. 1.20 0.15 A2 0.037 0.039 0.041 0.95 1.00 b 0.007 0.008 0.009 0.17 0.20 0.23 c 0.005 0.006 0.007 0.12 0.15 0.17 18.50 1.05 0.10(0.004) b D 0.720 0.724 0.728 18.30 18.40 E 0.311 0.315 0.319 7.90 8.00 8.10 HD 0.780 0.787 0.795 19.80 20.00 20.
Preliminary W49F020 VERSION HISTORY VERSION DATE PAGE A1 Oct. 1999 - Headquarters DESCRIPTION Initial Issued Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab.
