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W78C54

8-BIT MICROCONTROLLER

Publication Release Date: December 1997

- 1 - Revision A2

GENERAL DESCRIPTION

The W78C54 is a derivative of the W78C52 microcontroller family that provides extended internal

ROM. The chip has 16K bytes of mask ROM and 256 bytes of RAM.

This device provides an enhanced architecture that makes it more powerful and suitable for a variety

of applications for general control systems. It provides on-chip 16KB mask ROM to accommodate

large program codes, 256-bytes of non-volatile on-chip RAM, four 8-bit I/O ports, one 4-bit I/O port,

three 16-bit timer/counters, eight sources with two-level interrupt structures, and on-chip oscillator

clock circuits.

FEATURES

• DC to 40 MHz extensive operating frequency

• 256-byte on-chip scratch pad RAM

• 16K-byte on-chip mask ROM

• 64K-byte address space for external Program Memory

• 64K-byte address space for external Data Memory

• Three 16-bit timer/counters

•

Four 8-bit bit-addressable I/O ports

• One extra 4-bit bit-addressable I/O port, additional INT2/ INT3

(Available on 44-pin PLCC/QFP package)

• Eight-source, two priority-level interrupts

• Low EMI emission mode

• Built-in programmable power-saving modes - Idle mode & Power-down mode

• Packages:

− DIP 40: W78C54-16/24/40

− PLCC 44: W78C54P-16/24/40

− QFP 44: W78C54F-16/24/40

− TQFP 44: W78C54M-16/24/40

Summary of content (16 pages)

PAGE 1
W78C54 8-BIT MICROCONTROLLER GENERAL DESCRIPTION The W78C54 is a derivative of the W78C52 microcontroller family that provides extended internal ROM. The chip has 16K bytes of mask ROM and 256 bytes of RAM. This device provides an enhanced architecture that makes it more powerful and suitable for a variety of applications for general control systems.
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W78C54 PIN CONFIGURATIONS 40-Pin DIP (W78C54) T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 44-Pin PLCC (W78C54P) T 2 E X , P P P P 1 1 1 1 . . . . 4 3 2 1 P1.5 P1.6 P1.7 RST RXD, P3. INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 T 2 , P 1 . 0 P 3 .
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W78C54 PIN DESCRIPTION SYMBOL EA PSEN TYPE DESCRIPTIONS I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. The ROM address and data will not be present on the bus if the EA pin is high and the program counter is within the 16 KB area. Otherwise they will be present on the bus. O H PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin.
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W78C54 BLOCK DIAGRAM P1.0 ~ P1.7 Port 1 Port 1 Latch ACC B INT2 Port 0 Interrupt INT3 T1 Latch T2 Timer 2 Timer 0 Port 0 P0.0 ~ P0.7 DPTR Stack Pointer PSW ALU Temp Reg. Timer 1 PC Incrementor UART Addr. Reg. P3.0 ~ P3.7 Port 3 Port 3 Latch 16KB ROM SFR RAM Address Instruction Decoder & Sequencer 256 bytes RAM & SFR Port 2 Latch Bus & Clock Controller P4.0 ~ P4.3 Port 4 Port 4 Latch Oscillator Reset Block XTAL1 XTAL2 ALE PSEN RST Power control VCC GND Figure 2.
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W78C54 FUNCTIONAL DESCRIPTION The W78C54 is pin-to-pin compatible with the W78C52, except that the internal 8K mask ROM has been replaced with 16K of internal mask ROM. The processor supports 111 different opcodes and references both 64K program address space and 64K data storage space. Clock The W78C54 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used.
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W78C54 1. INT2 / INT3 Two additional external interrupts, INT2 and INT3, whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction.
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W78C54 DESCRIPTIONS OF THE SPECIAL FUNCTION REGISTERS (SFRS) SYM. DEFINITION ADDR. MSB BIT ADDRESS, SYMBOL LSB RESET B B register F0H (F7) (F6) (F5) (F4) (F3) (F2) (F1) (F0) 00000000B ACC Accumulator E0H (E7) (E6) (E5) (E4) (E3) (E2) (E1) (E0) 00000000B P4* Port 4 D8H - - - - (D9) (D8) xxxx0000B 00000000B (DB) (DA) INT2 INT3 PSW Program status word D0H TH2 T2 reg. high CDH 00000000B TL2 T2 reg.
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W78C54 Note: In column BIT_ADDRESS, SYMBOL, containing ( ) item means the bit address. * SFRs modified or added to the W78C52. + Reset value depends on reset condition. W78C54 SFRs address location map: F8 F0 FF +B F7 E8 EF E0 + ACC E7 D8 +P4 DF D0 + PSW C8 +T2CON D7 C0 +XICON C7 B8 + IP BF B0 + P3 B7 A8 + IE AF A0 + P2 98 + SCON 90 + P1 88 + TCON TMOD TL0 TL1 80 +P0 SP DPL DPH RCAP2L RCAP2H TL2 TH2 CF A7 SBUF 9F 97 TH0 TH1 AUXR 8F PCON 87 Notes: 1.
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W78C54 * Interrupts ***IE - Interrupt Enable (A8H) EA - ET2 ES ET1 EX1 ET0 EX0 PT1 PX1 PT0 PX0 PX2 EX2 IE2 IT2 EA: Lobal interrupt enable flag ET2: Timer 2 overflow interrupt enable ES: Serial port interrupt enable EX1: External interrupt 1 enable ET1: Timer 1 overflow interrupt enable EX0: External interrupt 0 enable ***IP - Interrupt Priority (B8H) - - PT2 PS PT2: Timer 2 interrupt priority high if set PS: Serial port priority high if set PT1: Timer 1 interrupt priority high if set PX1
PAGE 10
W78C54 Following tables show the interrupt informations and priority definitions. Eight-source interrupt informations: INTERRUPT SOURCE VECTOR ADDRESS POLLING SEQUENCE WITHIN PRIORITY LEVEL ENABLE REQUIRED SETTINGS INTERRUPT TYPE EDGE/LEVEL External Interrupt 0 03H 0 (highest) IE.0 TCON.IT0 Timer/Counter 0 0BH 1 IE.1 - External Interrupt 1 13H 2 IE.2 TCON.IT1 Timer/Counter 1 1BH 3 IE.3 - Serial Port 23H 4 IE.4 - Timer/Counter 2 2BH 5 IE.
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W78C54 TR1: Timer 1 run control bit. Set/cleared by software to turn timer/counter on or off. TF0: Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TR0: Timer 0 run control bit. Set/cleared by software to turn timer/counter on or off. IE1: Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. IT1: Interrupt 1 type control bit.
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W78C54 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN. MAX. UNIT VCC−VSS -0.3 +7.0 V Input Voltage VIN VSS -0.3 VCC +0.3 V Operating Temperature TA 0 70 °C Storage Temperature TST -55 +150 °C DC Power Supply Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC CHARACTERISTICS (VDD−VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.) PARAMETER SYM. SPECIFICATION MIN. MAX.
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W78C54 DC Characteristics, continued PARAMETER Input High Voltage SYM. SPECIFICATION UNIT TEST CONDITIONS MIN. MAX. VIH1 2.4 VDD +0.2 V VDD = 5.5V VIH2 3.5 VDD +0.2 V VDD = 5.5V VIH3 3.5 VDD +0.2 V VDD = 5.5V VOL1 - 0.45 V VDD = 4.
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W78C54 Clock Input Waveform XTAL1 TCH TCL FOP, TCP Continued PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES Operating Speed FOP 0 - 40 MHz 1 Clock Period TCP 25 - - nS 2 Clock High TCH 10 - - nS 3 Clock Low TCL 10 - - nS 3 NOTES Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input.
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W78C54 Data Read Cycle External Data Memory Read Cycle (see Figure 7) PARAMETER SYMBOL MIN. TYP. MAX. UINT NOTES ALE Low to RD Low TDAR 3 Tcp-∆ 3 Tcp 3 Tcp+∆ nS 1, 2 RD Low to Data Valid TDDA - - 4 Tcp nS 1 Data hold After RD High TDDH 0 - 2 Tcp nS Data Float After RD High TDDZ 0 - 2 Tcp nS RD Pulse Width TDRD 6 Tcp-∆ 6 Tcp 6 Tcp+∆ nS 2 Notes: 1. Data Memory access time is 5 Tcp. 2. ∆ is 20 ns (due to buffer driving delay and wire loading.
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