W90N740 Data Sheet WINBOND 32-BIT ARM7TDMI-BASED MICRO-CONTROLLER -I- Publication Release Date: November 26, 2004 Revision A4
W90N740 The information described in this document is the exclusive intellectual property of Winbond Electronics Corporation and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes of W90N740-based system design. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Winbond Electronics Corp.
W90N740 Table of Contents1. GENERAL DESCRIPTION .......................................................................................................... 1 2. FEATURES .................................................................................................................................. 1 3. BLOCK DIAGRAM ....................................................................................................................... 5 4. PIN CONFIGURATION ...........................................
W90N740 7.8 USB Host Controller .................................................................................................. 136 7.8.1 7.9 UART Controller ........................................................................................................ 154 7.9.1 7.10 7.11 7.12 UART Control Registers Map ......................................................................................155 TIMER Controller ...............................................................................
W90N740 1. GENERAL DESCRIPTION The W90N740 micro-controller is 16/32 bit, ARM7TDMI based RISC micro-controller for network as well as embedded applications. An integrated dual Ethernet MAC, the W90N740, is designed for use in broadband routers, wireless access points, residential gateways and LAN camera. The W90N740N is built around The ARM7TDMI CPU core designed by Advanced RISC Machines, Ltd. And achieves 80MHz under worse conditions.
W90N740 External Bus Interface (EBI) • External I/O Control with 8/16/32 bit external data bus • Cost-effective memory-to-peripheral DMA interface • SDRAM Controller supports up to 2 external SDRAM & the maximum size of each device is 32MB • ROM/FLASH & External I/O interface • Support for PCMCIA 16-bit PC Card devices On-Chip Instruction and Data Cache • Two-way, Set-associative, 8K-byte I-cache and 2K-byte D-cache • Support for LRU (Least Recently Used) Protocol • Cache can be configured as
W90N740 USB Host Controller • USB 1.1 compatible • Open Host Controller Interface (OHCI) 1.0 compatible. • Supports both low-speed (1.5 Mbps) and full-speed (12Mbps) USB devices.
W90N740 On-Chip PLL • One PLL for both CPU and USB host controller • The external clock can be multiplied by on-chip PLL to provide high frequency system clock • Programmable clock frequency, and the input frequency range is 3-30MHz; 15MHz is preferred. Operation Voltage Range • 2.7 – 3.6 V for IO Buffer • 1.62 – 1.
W90N740 3. BLOCK DIAGRAM W90N740 TDMI Bus JTAG ICE Cache Controller ARM7TDMI Wrapper PLL 8K-Byte I Cache 2K-Byte D Cache Clock Controller AHB Arbiter UART AHB Decoder APB Bridge Interrupt Controller COM Port External Interrupts ROM Flash RAM PCMCIA IO Dev APB Bus EBI Bus External Bus Controller AHB Bus SDRAM GDMA Controller TIMER x2 WDT GPIO USB Device USB Host Controller Ethenet MAC Controller 0 NAT Accelerator PHY Ethenet MAC Controller 1 PHY Fig 3.
W90N740 4.
W90N740 5.
W90N740 Table 4 W90N740 Pins Assignment (Continued) PIN NAME 176-PIN LQFP Ethernet Interface (0) ( 17 pins ) MDC0 z 142 MDIO0 z 143 COL0 / z 151 z 152 TX0_CLK z 150 TX0D [3:0] / R1B_TXD [1:0], R0_TXD [1:0] z 149-146 TX0_EN / R0_TXEN z 144 RX0_CLK / R0_REFCLK z 153 RX0D [3:0] / R1B_RXD [1:0], R0_RXD [1:0] z 159-157, 154 RX0_DV / R0_CRSDV z 160 RX0_ERR z 161 CRS0 / R1B_CRSDV Ethernet Interface (1) ( 17 pins ) MDC1 z 10 MDIO1 z 8 COL1 z 6 CRS1 z 7 TX1_CLK z
W90N740 Table 4 W90N740 Pins Assignment (Continued) NAME 176-PIN LQFP USB Interface ( 2 pins ) DP z 131 DN z 130 Miscellaneous ( 21 pins ) GP [20:17] / nIRQ [3:0] z 136-133 GP16 / nXDREQ z 29 GP15 /nXDACK z 28 z 19 z 18 GP12 /nWDOG z 17 GP11 /RxD z 140 GP10 /TxD z 139 GP9/nDSR/nTOE z 128 GP8 /nDTR/FSE0 z 127 GP7 /nCD / VO z 126 GP6 /nCTS/ VM z 138 GP5 /nRTS/ VP z 137 GP4 /nRI / RCV z 125 GP [3:0] z 16-13 GP14 / TIMER1/ SPEED GP13 / TIMER0/ STDBY Name
W90N740 6. PIN DESCRIPTION Table 6.
W90N740 Pins Description, continued PIN NAME IO TYPE PAD TYPE DESCRIPTION Ethernet Interface (0) MDC0 O - MII Management Data Clock for Ethernet 0. It is the reference clock of MDIO0. Each MDIO0 data will be latched at the rising edge of MDC0 clock. MDIO0 IO - MII Management Data I/O for Ethernet 0. It is used to transfer MII control and status information between PHY and MAC. COL0 I - Collision Detect for Ethernet 0 in MII mode.
W90N740 Pins Description, continued IO TYPE PAD TYPE MDC1 O - MII Management Data Clock for Ethernet 1. It is the reference clock of MDIO1. Each MDIO1 data will be latched at the rising edge of MDC1 clock. MDIO1 IO - MII Management Data I/O for Ethernet 1. It is used to transfer MII control and status information between PHY and MAC. COL1 I - Collision Detect for Ethernet 1 in MII mode. This shall be asserted by PHY upon detecting a collision happened over the medium.
W90N740 Pins Description, continued IO TYPE PAD TYPE DP IO - Differential Positive USB IO signal DN IO - Differential Negative (Minus) USB IO signal GP[20:17] / nIRQ[3:0] IO - External Interrupt Request or General Purpose I/O GP16 / nXDREQ IO - External DMA Request or General Purpose I/O GP15 /nXDACK IO - External DMA Acknowledge or General Purpose I/O IO - IO - Timer 0 or General Purpose I/O.
W90N740 7. FUNCTIONAL DESCRIPTION 7.1 ARM7TDMI CPU Core The ARM7TDMI CPU core is a member of the ARM family of general-purpose 32-bit microprocessors, which offer high performance for very low power consumption. The architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set Computer (CISC) systems.
W90N740 7.2 7.2.1 System Manager Overview The functions of the System Manager: • System memory map & on-chip peripherals memory map • The data bus width of external memory address & data bus connection with external memory • Bus arbitration supports the Fixed Priority Mode & Rotate Priority Mode • Power-On setting • On-Chip PLL module control & Clock select control 7.2.2 System Memory Map W90N740 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable.
W90N740 Cacheable space 0x7FFF.FFFF 512KB (Fixed) 0x7FF8.0000 RESERVED 512KB (Fixed) 0x7FF0.0000 RESERVED 10KB RESERVED 0x7FE0.0000 Non-Cacheable space 0xFFFF.FFFF 512KB (Fixed) 0xFFF8.0000 512KB (Fixed) 0xFFF0.0000 RESERVED 10KB 0xFFE0.
W90N740 Table 7.2.1 On-Chip Peripherals Memory Map BASE ADDRESS DESCRIPTION AHB Peripherals 0xFFF0.0000 Product Identifier Register (PDID) 0xFFF0.0004 Arbitration Control Register (ARBCON) 0xFFF0.0008 PLL Control Register (PLLCON) 0xFFF0.000C Clock Select Register (CLKSEL) 0xFFF0.1000 EBI Control Register (EBICON) 0xFFF0.1004 ROM/FLASH (ROMCON) 0xFFF0.1008 SDRAM bank 0 - 1 0xFFF0.1018 External I/O 0 - 3 0xFFF0.2000 Cache Controller 0xFFF0.3000 Ethernet MAC Controller 0 - 1 0xFFF0.
W90N740 7.2.4 7.2.4.1 Data Bus Connection with External Memory Memory formats The internal architecture is big endian. The little endian mode only support for external memory. The W90N740 can be configured as big endian or little endian mode by pull up or down the data D14 pin. If D14 is pull-up then it is a little endian mode, otherwise, it is a big endian mode.
W90N740 7.2.4.2 Connection of External Memory with Various Data Width The system diagram for W90N740 connecting with the external memory is shown in Fig. 7.2.4. Below tables (Table7.2.3 − Table7.2.14) show the program/data path between CPU register and the external memory using little / big endian and word/half-word/byte access. Fig. 7.2.4 Address/Data bus connection with external memory Fig. 7.2.
W90N740 Table 7.2.3 and Table 7.2.4 Using big-endian and word access, Program/Data path between register and external memory WA = Address whose LSB is 0, 4, 8, C X = Don’t care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table7.2.
W90N740 Table 7.2.5 and Table 7.2.6 Using big-endian and half-word access, Program/Data path between register and external memory. HA = Address whose LSB is 0, 2, 4, 6, 8, A, C, E HAL = Address whose LSB is 0, 4, 8, C HAU = Address whose LSB is 2, 6, A, E X = Don’t care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table7.2.
W90N740 Table 7.2.7 and Table 7.2.8 Using big-endian and byte access, Program/Data path between register and external memory. BA = Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F BAL = Address whose LSB is 0, 2, 4, 6, 8, A, C, E F BAU = Address whose LSB is 1, 3, 5, 7, 9, B, D, BA0 = Address whose LSB is 0, 4, 8, C BA1 = Address whose LSB is 1, 5, 9, D BA2 = Address whose LSB is 2, 6, A, E BA3 = Address whose LSB is 3, 7, B, F Table7.2.
W90N740 Table7.2.
W90N740 Table 7.2.9 and Table 7.2.10 Using little-endian and word access, Program/Data path between register and external memory WA = Address whose LSB is 0, 4, 8, C X = Don’t care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table7.2.
W90N740 Table 7.2.11 and Table 7.2.12 Using little-endian and half-word access, Program/Data path between register and external memory. HA = Address whose LSB is 0, 2, 4, 6, 8, A, C, E HAL = Address whose LSB is 0,4,8,C HAU = Address whose LSB is 2, 6, A, E X = Don’t care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table7.2.
W90N740 Table 7.2.13 and Table 7.2.14 Using little-endian and byte access, Program/Data path between register and external memory. BA = Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F BAL = Address whose LSB is 0, 2, 4, 6, 8, A, C, E BAU = Address whose LSB is 1, 3, 5, 7, 9, B, D, F BA0 = Address whose LSB is 0, 4, 8, C BA1 = Address whose LSB is 1, 5, 9, D BA2 = Address whose LSB is 2, 6, A, E BA3 = Address whose LSB is 3, 7, B, F Table7.2.
W90N740 7.2.5 Bus Arbitration The W90N740’s internal function blocks or external devices can request mastership of the system bus and then hold the system bus in order to perform data transfers. The design of W90N740 bus allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal units or external devices simultaneously request bus mastership.
W90N740 7.2.5.2 Rotate Priority Mode In Rotate Priority Mode (PRTMOD = 1), the IPEN and IPACT bits have no function (i.e. ignore). W90N740 used a round robin arbitration scheme ensures that all bus masters (except the External Bus Master, it always has the first priority) have equal chance to gain the bus and that a retracted master does not lock up the bus. 7.2.6 Power-On Setting After power on reset, there are four Power-On setting pins to configure W90N740 system configuration.
W90N740 7.2.7 System Manager Control Registers Map Register Address R/W Description Reset Value PDID 0xFFF0.0000 R Product Identifier Register 0xX090.0740 ARBCON 0xFFF0.0004 R/W Arbitration Control Register 0x0000.0000 PLLCON 0xFFF0.0008 R/W PLL Control Register 0x0000.2F01 CLKSEL 0xFFF0.000C R/W Clock Select Register 0x0000.
W90N740 Arbitration Control Register (ARBCON) Register Address R/W Description Reset Value ARBCON 0xFFF0.0004 R/W Arbitration Control Register 0x0000.0000 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 IPACT IPEN PRTMOD RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 RESERVED IPACT [2] ： Interrupt priority active When IPEN=”1”, this bit is set when the ARM core has an unmasked interrupt request. This bit is available only when the PRTMOD = 0.
W90N740 PLL Control Register （PLLCON） W90N740 provides two options for clock generation - crystal and oscillator. The external clock via EXTAL input pin as the reference clock input of PLL module. The external clock can bypass the PLL and be used to the internal system clock by pull-down the data D15 pin. Using PLL’s output clock for the internal system clock, D15 pin must be pull-up. Register Address R/W PLLCON 0xFFF0.
W90N740 INDV [4:0] ：PLL input clock divider Input Divider divides the input reference clock into the PLL. EXTAL USBCKS FIN INDV[4:0] PFD FBDV[8:0] GP12 PLL Input Divider (NR) Charge Pump 48MHz Gen Output 480MHz Divider FOUT (NO) VCO Feedback Divider (NF) Clock Divider & Selector 1 0 0 1 ECLKS OTDV[1:0] Fig 7.2.
W90N740 Clock Select Register (CLKSEL) REGISTER ADDRESS R/W CLKSEL 0xFFF0.000C R/W 31 30 29 DESCRIPTION RESET VALUE Clock Select Register 28 27 0x0000.
W90N740 WDT [8] ： WDT clock enable bit 0 = Disable WDT counting clock 1 = Enable WDT counting clock USB [7] ： USB clock enable bit 0 = Disable USB clock 1 = Enable USB clock TIMER [6] ： Timer clock enable bit 0 = Disable Timer clock 1 = Enable Timer clock UART [5] ： UART clock enable bit 0 = Disable UART clock 1 = Enable UART clock ECLKS [4] ： External clock select 0 = External clock from EXTAL pin is used as system clock 1 = PLL output clock is used as system clock After power on reset, the content of ECLK
W90N740 RESET [0] ： Reset This is a software reset control bit. Set logic 1 to generate an internal reset pulse. This bit is auto-clear to logic 0 at the end of the reset pulse. 7.3 External Bus Interface (EBI) 7.3.1 EBI Overview External Bus Interface (EBI) controls the access to the external memory (ROM/SRAM/FLASH, SDRAM) and External I/O devices. The EBI has seven chip selects to select one ROM/FLASH bank, two SDRAM banks, and four External I/O banks and 25-bit address bus.
W90N740 7.3.2.
W90N740 SDRAM Data Bus Width: 32-bit Total Type RxC R/C A14 (BS1) A13 (BS0) A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16M 2Mx8 11x9 R ** 11 ** 11* 22 21 20 19 18 17 16 15 14 13 12 C ** 11 ** 11* AP 25* 10 9 8 7 6 5 4 3 2 R ** 10 ** 10* 11 21 20 19 18 17 16 15 14 13 12 C ** 10 ** 10* AP 25* 10* 9 8 7 6 5 4 3 2 R 11 12 11* 23 22 21 20 19 18 17 16 15 14 13 24 C 11 12 11* 23* AP 25* 10 9 8 7 6 5 4
W90N740 SDRAM Data Bus Width: 16-bit Total Type RxC R/C A14 (BS1) A13 (BS0) A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16M 2Mx8 11x9 R ** 10 ** 10* 21 20 19 18 17 16 15 14 13 12 11 C ** 10 ** 10* AP 24* 9 8 7 6 5 4 3 2 1 R ** 9 ** 9* 10 20 19 18 17 16 15 14 13 12 11 C ** 9 ** 9* AP 24* 9* 8 7 6 5 4 3 2 1 R 10 11 10* 22 21 20 19 18 17 16 15 14 13 12 23 C 10 11 10* 22* AP 24* 9 8 7 6 5 4 3 2 1
W90N740 SDRAM Data Bus Width: 8-bit Total Type RxC R/C A14 (BS1) A13 (BS0) A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16M 2Mx8 11x9 R ** 9 ** 9* 20 19 18 17 16 15 14 13 12 11 10 C ** 9 ** 9* AP 23* 8 7 6 5 4 3 2 1 0 R ** 8 ** 8* 9 19 18 17 16 15 14 13 12 11 10 C ** 8 ** 8* AP 23* 8* 7 6 5 4 3 2 1 0 R 9 10 9* 21 20 19 18 17 16 15 14 13 12 11 22 C 9 10 9* 21* AP 23* 8 7 6 5 4 3 2 1 1 R 9 8 9
W90N740 SDRAM Power Up Sequence The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. W90N740 supports the function of Power Up Sequence, that is, after system power on the W90N740 SDRAM Controller automatically executes the commands needed for Power Up Sequence and set the mode register of each bank to default value.
W90N740 7.3.3 External Bus Mastership The W90N740 can receive and acknowledge bus request signals that are generated by an external bus master. When the CPU asserts an external bus acknowledge signal, mastership is granted to the external bus master, assuming the external bus request is still active. When the external bus acknowledge signal is active, the W90N740’s memory interface signals go to high impedance state so that the external bus master can drive the required external memory interface signals.
W90N740 EBI Control Register (EBICON) Register Address EBICON 0xFFF0.1000 31 30 R/W Description Reset Value R/W EBI control register 29 28 27 0x0001.0000 26 25 24 18 17 16 REFEN REFMOD CLKEN 11 10 9 8 3 2 1 0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 REFRAT 7 6 5 4 REFRAT WAITVT LITTLE REFEN [18]: Enable SDRAM refresh cycle for SDRAM bank0 & bank1 This bit set will start the auto-refresh cycle to SDRAM. The refresh rate is according to REFRAT bits.
W90N740 WAITVT [2:1]: Valid time of nWAIT signal W90N740 recognizes the nEWAIT signal at the next “nth” MCLK rising edge after the nOE or nWBE active cycle. WAITVT bits determine the n. WAITVT [2:1] 0 0 0 1 1 0 1 1 nth MCLK 1 2 3 4 LITTLE [0] ：Read only, Little Endian mode 0 = EBI memory format is Big Endian mode 1 = EBI memory format is Little Endian mode After power on reset, the content of LITTLE is the Power-On Setting value from D14 pin.
W90N740 ROM/Flash Control Register （ROMCON） Register Address R/W ROMCON 0xFFF0.1004 R/W 31 30 Description Reset Value ROM/FLASH control register 29 28 0x0000.0XFC 27 26 25 24 19 18 17 16 BASADDR 23 22 21 20 BASADDR 15 14 13 SIZE 12 11 10 RESERVED 7 6 9 8 1 0 tPA 5 4 3 tACC 2 BTSIZE PGMODE BASADDR [31:19] ：Base address pointer of ROM/Flash bank The start address is calculated as ROM/Flash bank base pointer << 18.
W90N740 tPA [11:8]：Page mode access cycle time tPA [11:8] tPA [11:8] MCLK MCLK 0 0 0 0 1 1 0 0 0 10 0 0 0 1 2 1 0 0 1 12 0 0 1 0 3 1 0 1 0 14 0 0 1 1 4 1 0 1 1 16 0 1 0 0 5 1 1 0 0 18 0 1 0 1 6 1 1 0 1 20 0 1 1 0 7 1 1 1 0 22 0 1 1 1 8 1 1 1 1 24 tACC [7:4]：Access cycle time tACC [7:4] tACC [7:4] MCLK MCLK 0 0 0 0 1 1 0 0 0 10 0 0 0 1 2 1 0 0 1 12 0 0 1 0 3 1 0 1 0 14 0 0 1 1 4 1 0 1
W90N740 PGMODE [1:0] ：Page mode configuration PGMODE [1:0] Mode 0 0 Normal ROM 0 1 4 word page 1 0 8 word page 1 1 16 word page Fig7.3.2 ROM/FLASH Read Operation Timing Fig 7.3.
W90N740 Configuration Registers（SDCONF0/1） The configuration registers enable software to set a number of operating parameters for the SDRAM controller. There are two configuration registers SDCONF0、SDCONF1 for SDRAM bank 0、bank 1 respectively. Each bank can have a different configuration. Register Address SDCONF0 0xFFF0.1008 R/W SDRAM bank 0 configuration register 0x0000.0800 SDCONF1 0xFFF0.100C R/W SDRAM bank 1 configuration register 0x0000.
W90N740 LATENCY [12:11] ：The CAS Latency of SDRAM bank 0/1 Defines the CAS latency of external SDRAM bank 0/1 LATENCY [12:11] MCLK 0 0 1 0 1 2 1 0 3 1 1 REVERSED COMPBK [7] ： Number of component bank in SDRAM bank 0/1 Indicates the number of component bank (2 or 4 banks) in external SDRAM bank 0/1.
W90N740 SIZE [2:0] ：Size of SDRAM bank 0/1 Indicates the memory size of external SDRAM bank 0/1 SIZE [2:0] Size of SDRAM （Byte） 0 0 0 Bank disable 0 0 1 2M 0 1 0 4M 0 1 1 8M 1 0 0 16M 1 0 1 32M 1 1 0 64M 1 1 1 REVERSED Timing Control Registers （SDTIME0/1） W90N740 offers the flexible timing control registers to control the generation and processing of the control signals and can achieve you use different speed of SDRAM Register Address SDTIME0 0xFFF0.
W90N740 tRCD [10:8] ：SDRAM bank 0/1, /RAS to /CAS delay (see Fig 7.3.4) tRCD [10:8] MCLK 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 tRDL [7:6] ：SDRAM bank 0/1, Last data in to pre-charge command (see Fig 7.3.
W90N740 tRP [5:3] ：SDRAM bank 0/1, Row pre-charge time (see Fig 7.3.4) tRP [5:3] MCLK 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 Fig 7.3.
W90N740 tRAS [2:0] ：SDRAM bank 0/1, Row active time (see Fig 7.3.4) tRAS [2:0] MCLK 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 Fig 7.3.
W90N740 External I/O Control Registers（EXT0CON – EXT3CON） The W90N740 supports an external device control without glue logic. It is very cost effective because address decoding and control signals timing logic are not needed. Using these control registers you can configure special external I/O devices for providing the low cost external devices control solution. Register Address EXT0CON 0xFFF0.1018 R/W External I/O 0 control register 0x0000.0000 EXT1CON 0xFFF0.
W90N740 ADRS [15] ：Address bus alignment for external I/O bank 0~3 When ADRS is set, EBI bus is alignment to byte address format, and ignores DBWD [1:0] setting.
W90N740 tACS [7:5] ：Address set-up before nECS for external I/O bank 0~3 tACS [7:5] MCLK 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 tCOS [4:2]：Chip selection set-up time on nOE or nWBE for external I/O bank 0~3 When ROM/Flash memory bank is configured, the access to its bank stretches chip selection time before the nOE or new signal is activated.
W90N740 Fig 7.3.
W90N740 Clock Skew Control Register （CKSKEW） Register Address R/W Description Reset Value CKSKEW 0xFFF7.1F00 R/W Clock skew control register 0xXXXX.0038 31 30 29 28 27 26 25 24 18 17 16 10 9 8 DLH_CLK_REF 23 22 21 20 19 DLH_CLK_REF 15 14 13 12 11 RESVERED 7 6 5 4 SWPON 3 DLH_CLK_SKEW 2 1 0 MCLK_O_D DLH_CLK_REF [31:16]: Latch DLH_CLK clock tree by HCLK positive edge.
W90N740 DLH_CLK_SKEW [7:4] ：Data latch clock skew adjustment DLH_CLK_SKEW [7:4] DLH_CLK_SKEW [7:4] Gate Delay 0 0 0 0 P-0 0 0 0 1 P-1 0 0 1 0 P-2 0 0 1 1 P-3 0 1 0 0 P-4 0 1 0 1 P-5 0 1 1 0 P-6 0 1 1 1 P-7 Gate Delay 1 0 0 0 N-0 1 0 0 1 N-1 1 0 1 0 N-2 1 0 1 1 N-3 1 1 0 0 N-4 1 1 0 1 N-5 1 1 1 0 N-6 Note: P-x means Data latched Clock shift “X” gates delays by refer MCLKO positive edge, N-x means Data latched Clock shift “X” gate
W90N740 7.4 Cache Controller The W90N740 has an 8KB Instruction cache, 2KB Data cache, and 8 words write buffer. The I-Cache and D-Cache are similar except the cache size. To enhance the hit ratio, these two caches are configured two-way set associative addressing. Each cache has four words cache line size. When a miss occurs, four words must be fetched consecutively from external memory. The replacement algorithm is a LRU (Least Recently Used).
W90N740 The cache access cycle begins with an instruction request from the instruction unit in the core. In the case of a cache hit, the instruction is delivered to the instruction unit. In case of a cache miss, the cache initiates a burst read cycle on the internal bus with the address of the requested instruction. The first word received from the bus is the requested instruction. The cache forwards this instruction to the instruction unit of the core as soon as it is received from the internal bus.
W90N740 the ICAH bit is set. As flushing the cache line, the “V” bit of the line is cleared to “0”. The I-Cache is automatically flushed during reset. 7.4.3.4 Instruction Cache Load and Lock The W90N740 supports a cache-locking feature that can be used to lock critical sections of code into ICache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The smallest space, which can be locked down, is 4 words.
W90N740 7.4.4 Data Cache The W90N740 data cache (D-Cache) is a 2KB two-way set associative cache. The cache organization is 64 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache is designed for buffer write-through mode of operation and a least recently used (LRU) replacement algorithm is used to select a line when no empty lines are available. When D-Cache is disabled, the cache memory is served as 2KB On-chip RAM.
W90N740 7.4.4.3 Data Cache Flushing The W90N740 allows flushing of the data cache under software control. The data cache may be invalidated through writing flush line (FLHS) or flush all (FLHA) commands to the CAHCON register. Flushing the entire D-Cache also flushed any locked down code. As flushing the data cache, the “V” bit of the line is cleared to “0”. The D-cache is automatically flushed during reset. 7.4.4.
W90N740 7.4.5 Write Buffer The W90N740 provides a write buffer to improve system performance. The write buffer can buffer up to eight words of data. The write buffer may be enabled or be disabled via the WRBEN bit in the CAHCNF register, and the buffer is disabled and flushed on reset. Drain write buffer To force data, which is in write buffer, to be written to external main memory.
W90N740 Cache Configuration Register (CAHCNF) Cache controller has a configuration register to enable or disable the I-Cache, D-Cache, and Write buffer. Register Address CAHCNF 0xFFF0.2000 31 30 R/W Description Reset Value R/W Cache configuration register 29 28 0x0000.
W90N740 Cache Control Register (CAHCON) Cache controller supports one Control register used to control the following operations. z z z z Flush I-Cache and D-Cache Load and lock I-Cache and D-Cache Unlock I-Cache and D-Cache Drain write buffer These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command set bit will be cleared to “0” automatically. Register Address CAHCON 0xFFF0.
W90N740 To flush the entire I-Cache/D-Cache, also flushes any locked-down code. If the I-Cache/D-Cache contains locked down code, the programmer must flush lines individually. DCAH [1] ：D-Cache selected When set to “1”, the command set is executed with D-Cache. ICAH [0] ：I-Cache selected When set to “1”, the command set is executed with I-Cache. Notes：When using the FLHA or ULKA command, you can set both ICAH and DCAH bits to execute entire I-Cache and D-Cache flushing or unlocking.
W90N740 7.5 Ethernet MAC Controller (EMC) The W90N740 has two Ethernet MAC Controllers (EMC) for WAN/LAN application. Each EMC has its DMA controller, transmit FIFO, and receive FIFO. The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM address register for entry address comparison, Transmit-FIFO, Receive-FIFO, TX/RX state machine controller and status controller.
W90N740 the ownership is granted to CPU. If NATA is enabled, NATA is also allowed to access current descriptor and bit 30 is set to 1 by NATA when NATA is processing. 7.5.1.2 Rx Status: Receive Status This field is updated by EMC after reception completed. The detail description is on next page. Frame Length: Received Frame Length This field is the size of the received frame. Data Buffer Starting Address This field is the starting address of the frame data to be received.
W90N740 7.5.1.5 NATFSH: NAT Processing Finish The value is 1 if current packet NAT processing is finished and successful. This bit will be written while NATA finish the NAT processing. NOP: No Operation This bit indicates the packet is hit in NAT table but no need to be replaced by NATA. This bit will be set to 1 if the packet hit the NAT table and the corresponding NOP and Discard bit of hit entry is 2’b10. RP: Runt Packet Set if the received packet length is less than 64 bytes.
W90N740 NH_Err: No Hit Error These bits records error status if NAT processing error is occurred and are wrote by NATA. (1) UCK_Err: TCP = 1 and UCKS = 1 (2) TU_Err: TCP = 1 and UDP = 1 (3) NH_Err: No hit error IP Header Length: TCP/UDP header location offset The offset value lets the NAT accelerator to identify the starting address of TCP or UDP header, which is used for NAT to parsing port data. The value is valid if Hit is set.
W90N740 Hit: current packet is hit with NAT entry table The value is 1 if current packet IP/port is in the entry list. If NAT is disabled, the bit is reserved. Tx Buffer Descriptor (TXBD) 3 1 3 0 1 6 1 5 3 O 2 1 0 I C P Data Buffer Starting Address Tx Status Frame Length Next Descriptor Starting Address O: Ownership bit 0 = CPU 1 = DMA W90N740 transmit DMA is allowed to access current descriptor if this bit is set to ‘1’ by the user driver program.
W90N740 Tx Status (TXSTA) 31 30 29 28 27 CCNT 26 25 24 SEQ PAU TXHA 23 22 21 20 19 18 17 16 LC TXABT NCS EXDEF TXCP Reserved DEF TXINTR TXINTR: Interrupt on Transmit Set if transmission of packet causes an interrupt condition. It includes TXCP. DEF: Transmit deferred Set when MAC has to defer, if MAC is ready to transmit a frame, because the carrier sense input is asserted before the MAC gets granted to acquire the network media.
W90N740 These registers are used for loading commands generated by user, indicating transmit and receive status, buffering data to/from memory, and providing interrupt control. The registers used by W90N740 EMC (Ethernet MAC controller) are divided into three groups: • CAM REGISTERS • MAC REGISTERS • DMA REGISTERS Note: registers are named as xxxx_0 or xxxx_1, where xxxx_0 is the register in EMC 0, and xxxx_1 is the register in EMC 1.
W90N740 EMC 0 Control registers, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM9L_0 0xFFF0.3054 R/W CAM9 Least Significant Word Register 0x0000.0000 CAM10M_0 0xFFF0.3058 R/W CAM10 Most Significant Word Register 0x0000.0000 CAM10L_0 0xFFF0.305C R/W CAM10 Least Significant Word Register 0x0000.0000 CAM11M_0 0xFFF0.3060 R/W CAM11 Most Significant Word Register 0x0000.0000 CAM11L_0 0xFFF0.3064 R/W CAM11 Least Significant Word Register 0x0000.
W90N740 EMC 0 Status Registers Register Address R/W Description Reset Value MAC REGISTERS MISTA_0 0xFFF0.30B4 R/W MAC Interrupt Status Register 0x0000.0000 MGSTA_0 0xFFF0.30B8 R/W MAC General Status Register 0x0000.0000 MRPC_0 0xFFF0.30BC R MAC Receive Pause count register 0x0000.0000 MRPCC_0 0xFFF0.30C0 R MAC Receive Pause Current Count Register 0x0000.0000 MREPC_0 0xFFF0.30C4 R MAC Remote pause count register 0x0000.0000 DMA REGISTERS DMARFS_0 0xFFF0.
W90N740 EMC 1 Control Registers, continued Register Address R/W Description Reset Value CAM REGISTERS CAM5M_1 0xFFF0.3830 R/W CAM5 Most Significant Word Register 0x0000.0000 CAM5L_1 0xFFF0.3834 R/W CAM5 Least Significant Word Register 0x0000.0000 CAM6M_1 0xFFF0.3838 R/W CAM6 Most Significant Word Register 0x0000.0000 CAM6L_1 0xFFF0.383C R/W CAM6 Least Significant Word Register 0x0000.0000 CAM7M_1 0xFFF0.3840 R/W CAM7 Most Significant Word Register 0x0000.0000 CAM7L_1 0xFFF0.
W90N740 EMC 1 Control Registers, continued Register Address R/W Description Reset Value DMA REGISTERS Transmit Descriptor Link List Start Address register TXDLSA_1 0xFFF0.389C R/W 0xFFFF.FFFC RXDLSA_1 0xFFF0.38A0 R/W Receive Descriptor Link List Start Address register 0xFFFF.FFFC DMARFC_1 0xFFF0.38A4 R/W DMA Receive Frame Control Register TSDR_1 0xFFF0.38A8 W Transmit Start Demand Register Undefined RSDR_1 0xFFF0.38AC W Receive Start Demand Register Undefined FIFOTHD_1 0xFFF0.
W90N740 CAM Command Register (CAMCMR_0, CAMCMR_1) The three accept bits in the CAMCMR_x are used to override CAM rejections or accept ion. To place the MAC in promiscuous mode, use CAMCMR_x settings to accept packets with all three types of destination address. The three types of destination address packets are as follows: 1. Station packets, xxxxxxx0-xxxxxxxx-xxxxxxxx-xxxxxxxx-xxxxxxxx-xxxxxxxx 2. Multicast packet, xxxxxxx1-xxxxxxxx-xxxxxxxx-xxxxxxxx-xxxxxxxx-xxxxxxxx. (but x not all 1) 3.
W90N740 AMP [1]: Accept Multicast Packet Default value: 0 Set this bit to accept any packet with a multicast address. AUP [0]: Accept Unicast Packet Default value: 0 Set this bit to accept any packet with a unicast address. CAM Enable Register (CAMEN_0, CAMEN_1) The CAM enable register, CAMEN_x, indicates which CAM entries are valid, using a direct comparison mode. Up to 16 entries, numbered 0 through 15, may be active, depending on the CAM size.
W90N740 CAM Address Registers (CAMxx_0, CAMxx_1) There are 16 entries for the Destination Address (entries 0~12) and the Pause Control Packet (entries 13~15). For the destination address values, one destination address consists of 6 bytes with 2-word access port.
W90N740 {CAMxM, CAMxL} : destination address (6 byte), with 2 bytes in CAMxL and 4 bytes in CAMxM, (CAM15M and CAM15L excluded). For example, if the address of Entry CAM 1 is desired to store 12-34-56-78-90-13, then the content of CAM1M is 12-34-56-78, and the content of CAM1L is 90-13-00-00.
W90N740 MAC Interrupt Enable Register (MIEN_0, MIEN_1) Register Address R/W Description Reset Value MIEN_1 0xFFF0.3088 R/W MAC Interrupt Enable Register 0x0000.0000 MIEN_2 0xFFF0.3888 R/W MAC Interrupt Enable Register 0x0000.
W90N740 Set this bit to enable the interrupt, which is generated to indicate 16 collisions occur while transmitting the same packet. EnNCS [20]: Enable No Carrier Sense interrupt Default value: 0 Set this bit to enable the interrupt, which is generated to indicate no carrier sense is presented during transmission. EnEXDEF [19]: Enable Defer interrupt Default value: 0 Set this bit to enable the interrupt, which is generated to indicate that the defer time exceeding 0.32768ms operated at 100Mbs/s or 3.
W90N740 Set this bit to enable the interrupt, which is generated if there is no error during NATA do the NAT processing. EnRxBErr [11]: Enable Receive Bus ERROR interrupt Default value: 0 Set this bit to enable the interrupt, which is generated if system bus access error from Rx to system memory occurred. If the interrupt is triggered, the Rx state machine will stay at Halt state. The software reset is recommended while this interrupt occurred.
W90N740 EnRXGD [4]: Enable Receive Good interrupt Default value: 0 Set this bit to enable the interrupt, which is generated if a packet was successfully received with no errors. EnPTLE [3]: Enable Packet Too Long interrupt Default value: 0 Set this bit to enable the interrupt, which is generated if the MAC received a frame longer than 1518 bytes (unless ALP in MCMDR is set).
W90N740 MAC Command Register (MCMDR_0, MCMDR_1) The MAC command register provides global control information for the MAC. MAC command register settings affect both transmission and reception. The user can also control transmit and receive operation separately. To select customized operating features, users should write this register during system initialization. This way, users will not need to write or read it again during normal operation.
W90N740 MAC 1 BIT [23:22] MAC 0 BIT [23:22] MAC 1 INTERFACE MAC 0 INTERFACE LPCS: ENRMII LPCS*1: ENRMII 00 X0 MII MII 00 X1 MII RMII 01 X0 RMII MII 01 X1 RMII RMII NOTE *1: the LPCS of MAC0 bit23 is undefined, which not affect MAC 0 Interface. LBK [21]: Loop Back Default value: 0 Set this bit to enable MAC internal loop back mode. OPMOD [20]: Operation Mode Default value: 0 Set this bit to enable MAC to be operated at 100Mb/s. Clear this bit to enable MAC to be operated at 10Mb/s.
W90N740 SPCRC [5]: Accept Strip CRC Value Default value: 0 Set this bit to enable MAC to check the CRC and then strip it from the message. AEP [4]: Accept Error Packet Default value: 0 Set this bit to enable MAC to accept error (CRC error) packet. ACP [3]: Accept Control Packet Default value : 0 Set this bit to enable accept control packets. ARP [2]: Accept Runt Packet Default value: 0 Set this bit to enable accepting frames with lengths less than 64 bytes.
W90N740 MAC MII Management Data Register (MIID_0, MIID_1) W90N740 provides MII management function to let user access the registers of the external physical layer device. Setting options in MII management registers does not affect the MAC controller operation. Register Address R/W MIID_0 0xFFF0.3090 R/W MII Management Data Register 0x0000.0000 MIID_1 0xFFF0.3890 R/W MII Management Data Register 0x0000.
W90N740 MAC MII Management Data Control and Address Register (MIIDA_0, MIIDA_1) Register Address R/W Description Reset Value MIIDA_0 0xFFF0.3094 R/W MII Management Data Control and Address Register 0x00A0.0000 MIIDA_1 0xFFF0.3894 R/W MII Management Data Control and Address Register 0x00A0.
W90N740 Users should set the MDC clock setting to meet the PHY requirement (maximum 2.5MHz). Besides, the MCLK (HCLK) frequency ranges from 10 MHz to 150 MHz (set MDC 2.5MHz). MDCON [19]: MDC Clock On Always Default value: 0 If this bit was set, the MDC clock will always active. Otherwise, the MDC clock will active only when the EnMDC of MCMDR and BUSY of MIIDA are both set. In other words, the MDC clock will be turned off after the station management command finished. This bit is only for debug.
W90N740 MAC Missed Packet Count register (MPCNT_0, MPCNT_1) The value in the MAC Missed Packet Count register (MPCNT) indicates the number of packets that were discarded due to various types of errors. Together with status information on packets transmitted and received, the MPCNT and these two pause count registers provide the information required for station management. Users can read the MPCNT to get current missed packet counter value and clears the register (read clear).
W90N740 DMA Transmit Descriptor Link-list Start Address Register (TXDLSA_0, TXDLSA_1) Register Address R/W Description Reset Value TXDLSA_0 0xFFF0.309C R/W Transmit Descriptor Link-list Start Address register 0xFFFF.FFFC TXDLSA_1 0xFFF0.389C R/W Transmit Descriptor Link-list Start Address register 0xFFFF.
W90N740 DMA Receive Descriptor Link List Start Address Register (RXDLSA_0, RXDLSA_1) Register Address R/W Description Reset Value RXDLSA_0 0xFFF0.30A0 R/W Receive Descriptor Link List Start Address register 0xFFFF.FFFC RXDLSA_1 0xFFF0.38A0 R/W Receive Descriptor Link List Start Address register 0xFFFF.
W90N740 DMA Receive Frame Control Register (DMARFC_0, DMARFC_1) Register Address R/W DMARFC_0 0xFFF0.30A4 R/W DMA Receive Frame Control Register 0x0000.0800 DMARFC_1 0xFFF0.38A4 R/W DMA Receive Frame Control Register 0x0000.
W90N740 Transmit Start Demand Register (TSDR_0, TSDR_1) Register Address R/W TSDR_0 0xFFF0.30A8 W Transmit Start Demand Register Undefined TSDR_1 0xFFF0.
W90N740 Receive Start Demand Register (TSDR_0, TSDR_1) Register Address R/W RSDR_0 0xFFF0.30AC W Receive Start Demand Register Undefined RSDR_1 0xFFF0.
W90N740 FIFO Threshold Adjustment Register (FIFOTHD_0, FIFOTHD_1) Register Address R/W FIFOTHD_0 0xFFF0.30B0 R/W FIFO Threshold Adjustment Register 0x0000.0101 FIFOTHD_1 0xFFF0.38B0 R/W FIFO Threshold Adjustment Register 0x0000.
W90N740 setting value, Tx DMA will request the arbiter to get data from memory. RxTHD [1:0]: Receive FIFO Upper threshold Register Default value: 1h Value setting: 00b: Depend on the burst length setting 01b: 64 bytes (i.e. low threshold 32 bytes) 10b: 128 bytes (i.e. low threshold 64 bytes) 11b: 192 bytes (i.e. low threshold 96 bytes) This value controls the receive FIFO high threshold. If receiving packet number is greater than the setting value, Rx DMA will request the arbiter to send data into memory.
W90N740 MAC Interrupt Status Register (MISTA_0, MISTA_1) The MAC event register is used as the Ethernet event register to generate interrupts and report events recognized by MAC controller. When an event is recognized, the MAC controller sets the corresponding MISTA bit. Interrupts are enabled by setting, and masked by clearing, the equivalent bits in the MAC Interrupt Enable Register (MIEN). The MISTA bits are cleared by write ones; writing zeros has no effect. Register Address R/W MISTA_0 0xFFF0.
W90N740 TXABT [21]: Transmit Abort Default value: 0 The bit is set to indicate 16 collisions occur while transmitting the same packet. NCS [20]: No Carrier Sense Default value: 0 Set to indicate no carrier sense is presented during transmission. EXDEF [19]: Defer Default value: 0 This bit is set to indicate that defer time exceeding 0.32768ms operated at 100Mbs/s and 3.2768ms operated at 10Mbs/s.
W90N740 This field will be set if there is no error during NATA do the NAT processing. If the status and EnNATOK in MIEN are both set, the EMC_RxINT will be triggered. RxBErr [11]: Receive Bus Error interrupt Default value: 0 This field will be set if the access error from EMC to memory (for example, address undefined in system) is occurred. If the status and EnBErr in MIEN are both set, the EMC_RxINT will be triggered.
W90N740 Default value: 0 This bit is set if a packet was successfully received with no errors. PTLE [3]: Packet Too Long Error Default value: 0 This bit is set if the MAC received a frame longer than 1518 bytes (unless ALP in MCMDR is set). RXOV [2]: Receive FIFO Overflow error Default value: 0 This bit is set if the MAC receives FIFO was overflow when receiving a frame.
W90N740 MAC General Status Register (MGSTA_0, MGSTA_1) Register Address R/W MGSTA_0 0xFFF0.30B8 R/W MAC General Status Register 0x0000.0000 MGSTA_1 0xFFF0.38B8 R/W MAC General Status Register 0x0000.0000 31 30 29 Description 28 Reset Value 27 26 25 24 19 18 17 16 11 10 9 8 TXHA SQE PAU DEF 3 2 1 0 RXHA CFR Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 CCNT Reserved All the MGSTA bits are write ones clear.
W90N740 RXHA [1]: Reception Halted Default value: 0 This bit is set if reception is halted by clearing RXON bit in the MAC Command Register (MCMDR). CFR [0]: Control Frame Received Default value: 0 This bit is set if (1) the packet received is a MAC control frame (type = 8808H), (2) if the CAM recognizes the packet address, and (3) if the frame length is 64 bytes.
W90N740 MAC Received Pause Current Count Register (MRPCC_0, MRPCC_1) The received pause current count register, MRPCC, stores the current value of the 16-bit received pause counter. It is read only. Register Address R/W Description Reset Value MRPCC_0 0xFFF0.30C0 R MAC Receive Pause Current Count register 0x0000.0000 MRPCC_1 0xFFF0.38C0 R MAC Receive Pause Current Count register 0x0000.
W90N740 MAC Remote Pause Count Register (MREPC_0, MREPC_1) The remote pause count register, MREPC, stores the current value of the remote pause counter. It is read only. Register Address R/W MREPC_0 0xFFF0.30C4 R MAC Remote pause count register 0x0000.0000 MREPC_1 0xFFF0.38C4 R MAC Remote pause count register 0x0000.
W90N740 DMA Receive Frame Status Register (DMARFS_0, DMARFS_1) Register Address R/W Description Reset Value DMARFS_0 0xFFF0.30C8 R/W DMA Receive Frame Status Register 0x0000.0000 DMARFS_1 0xFFF0.38C8 R/W DMA Receive Frame Status Register 0x0000.
W90N740 Current Transmit Descriptor Start Address Register (CTXDSA_0, CTXDSA_1) Register Address R/W CTXDSA_0 0xFFF0.30CC R Current Transmit Descriptor Start Address Register 0x0000.0000 CTXDSA_1 0xFFF0.38CC R Current Transmit Descriptor Start Address Register 0x0000.
W90N740 Current Transmit Buffer Start Address Register (CTXBSA_0, CTXBSA_1) Register Address R/W Description Reset Value CTXBSA_0 0xFFF0.30D0 R Current Transmit Buffer Start Address Register 0x0000.0000 CTXBSA_1 0xFFF0.38D0 R Current Transmit Buffer Start Address Register 0x0000.
W90N740 Current Receive Descriptor Start Address Register (CRXDSA_0, CRXDSA_1) Register Address R/W CRXDSA_0 0xFFF0.30D4 R Current Receive Descriptor Start Address Register 0x0000.0000 CRXDSA_1 0xFFF0.38D4 R Current Receive Descriptor Start Address Register 0x0000.
W90N740 Current Receive Buffer Start Address Register (CRXBSA_0, CRXBSA_1) Register Address R/W Description Reset Value CRXBSA_0 0xFFF0.30D8 R Current Receive Buffer Start Address Register 0x0000.0000 CRXBSA_1 0xFFF0.38D8 R Current Receive Buffer Start Address Register 0x0000.
W90N740 7.6 Network Address Translation Accelerator (NATA) The Network Address Translation Accelerator (NATA) provides hardware acceleration function to enhance the IP address and port number translation. An inside (local/LAN) IP address is mapped to an outside (global/WAN) IP address, meaning that an inside IP address is replaced by the appropriate outside IP address, and vice versa.
W90N740 7.6.1 NAT Process Flow While EMC port get valid MAC packets and store them in memory, it check if {IP, port} hit, and update descriptors Rx: Look up NAT table process : 1. parsing IP address 2. according IP header length jump to TCP/UDP header 3. parsing TCP/UDP port number 4. compare {IP address, port number} with NAT table content Hit or not, hit message in descriptor NAT hit? No No NAT processing Yes Rx triggers NAT processing 1. 2. 3. 4.
W90N740 7.6.2 NATA Registers Map This set of registers is used to convey status/control information to/from the NAT engine. These registers are used for loading commands generated by user, indicating network translation status, and providing interrupt control.
W90N740 REGISTER OFFSET R/W DESCRIPTION RESET VALUE Address Lookup and Replacement Registers MASAD0 0xFFF0.6800 R/W NAT Masquerading IP Address Entry 0 0x0000.0000 MASPN0 0xFFF0.6804 R/W NAT Masquerading Port Number Entry 0 0x0000.0000 LSAD0 0xFFF0.6808 R/W Local Station IP Address Entry 0 0x0000.0000 LSPN0 0xFFF0.680C R/W Local Station Port Number Entry 0 0x0000.0000 0x0000.0000 LSMAC0M 0xFFF0.
W90N740 NAT Command Register (NATCMD) The NAT function is enabled by software setting NATEN, and auto triggered by EMC Rx if current packet is hit. S/W will get hit status from Rx descriptors when current packet is receiving, and processed by NATA, if it is hit. Writing ones in NATCMD can start NAT function, or clear entry counters. Register NATCMD Address 0x7FF06000 31 30 R/W Description Reset Value R/W NAT Command Register 29 28 0x0000.
W90N740 NAT Counter x Clear Register (NATCCLRx)(x: 3 ~ 0) Register NATCCLR0 Address 0x7FF06010 | Description Reset Value NAT Counter 0 Clear Register | NATCCLR3 7.6.2.1 R/W W 0x7FF0601C 0x0000.0000 | | NAT Counter 3 Clear Register 0x0000.
W90N740 NATCCLR2 31 30 29 28 27 26 25 24 CLREH47 CLREH46 CLREH45 CLREH44 CLREH43 CLREH42 CLREH41 CLREH40 23 22 21 20 19 18 17 16 CLREH39 CLREH38 CLREH37 CLREH36 CLREH35 CLREH34 CLREH33 CLREH32 15 14 13 12 11 10 9 8 CLRCNT47 CLRCNT46 CLRCNT45 CLRCNT44 CLRCNT43 CLRCNT42 CLRCNT41 CLRCNT40 7 6 5 4 3 2 1 0 CLRCNT39 CLRCNT38 CLRCNT37 CLRCNT36 CLRCNT35 CLRCNT34 CLRCNT33 CLRCNT32 7.6.2.
W90N740 NAT Entry x Configuration Registers (NATCFGx)(x: 63 ~ 0) All NAT Configuration registers, NATCFGx, include enable switches to control IP address and port number comparison, or replacement. Further, additional inverse (I) bit to control source address (SA) or destination address (DA) comparison. The NAT function is enabled if either of entry enable bits is set, else the NAT function is disabled.
W90N740 7.6.2.5 CNTx [10:8]: Number of Entry x Hit Packets to be processed Default value: 0x0 The register is read-only, to indicate that how many packet is hit with entry x and still not processed by NAT. When a new packet is hit with entry x, the corresponding entry counter, CNTx, will increase. On the other hand, when a packet hit with entry x is process, the corresponding CNTx will be decrease. Nop [7]: Packet Nop bit Default value: 0 Set this bit to receive current hit packet as usual.
W90N740 ExEN [0]: Entry x Comparison Enable bit Default value: 0 Set the bits to selectively enable entry location comparison. To disable an entry location, clear the appropriate bit. If S/W wants to change some entry data, it has to disable the selected entry and monitor corresponding CNTx till the value is 0, then it is acceptable to change new entry data.
W90N740 NATA comparison and replacement table at different port Inverse bit is reset WAN port (for receiving external packets) LAN port (for receiving local station packets) 7.6.2.
W90N740 MAC Address Registers (EXMACM, EXMACL, INMACM, INMACL, LSMACxM, LSMACxL, RSMACxM, RSMACxL) The MAC address registers are to store the MAC address of each EMC port. When the NATA is enabled and corresponding entry is hit, the MAC address translation from one port to another port must be done by hardwire, instead of by software. Thus the user must set the MAC address of each port for NAT to translate.
W90N740 NAT Masquerading IP Address Registers (MASADx) (x : 15 ~ 0) NAT Masquerading Port Number Registers (MASPNx) (x : 15 ~ 0) Local Station IP Address Registers (LSADx) (x : 15 ~ 0) Local Station Port Number Registers (LSPNx) (x : 15 ~ 0) The {MASADx, MASPNx} is represented for the outside IP address and the port number. The {LSADx, LSPNx} is represented for the internal IP address and the port number.
W90N740 7.7 GDMA Controller The GDMA Controller of W90N740 is a two-channel general DMA controller. The two-channel GDMA performs the following data transfers without the CPU intervention: • Memory-to-memory (memory to/from memory) • Memory –to – IO • IO- to -memory The GDMA can be started by the software or external DMA request nXDREQ1/2/3. Software can also be used to restart the GDMA operation after it has been stopped.
W90N740 7.7.2 GDMA Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GDMA_CTL0 0xFFF0.4000 R/W Channel 0 Control Register 0x0000.0000 GDMA_SRCB0 0xFFF0.4004 R/W Channel 0 Source Base Address Register 0x0000.0000 GDMA_DSTB0 0xFFF0.4008 R/W Channel 0 Destination Base Address Register 0x0000.0000 GDMA_TCNT0 0xFFF0.400C R/W Channel 0 Transfer Count Register 0x0000.0000 GDMA_CSRC0 0xFFF0.4010 R Channel 0 Current Source Address Register 0x0000.0000 GDMA_CDST0 0xFFF0.
W90N740 Channel 0/1 Control Register (GDMA_CTL0, GDMA_CTL1) Register Address R/W Description Reset Value GDMA_CTL0 0xFFF0.4000 R/W Channel 0 Control Register 0x0000.0000 GDMA_CTL1 0xFFF0.4020 R/W Channel 1 Control Register 0x0000.
W90N740 RW_TC [23]: Read/Write terminal count output selection. (This is for PCMCIA application in DMA mode, will be active during the final data transfer.) If RW_TC [23]=0, output to nRTC. If RW_TC [23]=1, output to nWTC. SABNDERR [22]: Source address Boundary alignment Error flag If TWS [13:12]=10, GDMA_SRCB [1:0] should be 00 If TWS [13:12]=01, GDMA_SRCB [0] should be 0 The address boundary alignment should be depended on TWS [13:12]. 0 = the GDMA_SRCB is on the boundary alignment.
W90N740 BLOCK [17]: Bus Lock 0 = Unlocks the bus during the period of transfer 1 = locks the bus during the period of transfer SOFTREQ [16]: Software Triggered GDMA Request Software can request the GDMA transfer service by setting this bit to 1. This bit is automatically cleared by hardware when the transfer is completed. This bit is available only while GDMAMS [3:2] register bits are set on software mode (memory to memory).
W90N740 However, if BME [9]=0, the GDMA_TCNT should be 0x10. SIEN [8]: Stop Interrupt Enable 0 = Do not generate an interrupt when the GDMA operation is stopped 1 = interrupt is generated when the GDMA operation is stopped SAFIX [7]: Source Address Fixed 0 = Source address is changed during the GDMA operation 1 = Do not change the destination address during the GDMA operation. This feature can be used when data were transferred from a single source to multiple destinations.
W90N740 Channel 0/1 Source Base Address Register (GDMA_SRCB0, GDMA_SRCB1) The GDMA channel starts reading its data from the source address as defined in this source base address register. Register Address R/W Description Reset Value GDMA_SRCB0 0xFFF0.4004 R/W Channel 0 Source Base Address Register 0x0000.0000 GDMA_SRCB1 0xFFF0.4024 R/W Channel 1 Source Base Address Register 0x0000.
W90N740 Channel 0/1 Transfer Count Register (GDMA_TCNT0, GDMA_TCNT1) Register Address R/W Description GDMA_TCNT0 0xFFF0.400C R/W Channel 0 Transfer Count Register 0x0000.0000 GDMA_TCNT1 0xFFF0.402C R/W Channel 1 Transfer Count Register 0x0000.
W90N740 Channel 0/1 Current Destination Register (GDMA_CDST0, GDMA_CDST1) Register Address R/W GDMA_CDST0 0xFFF0.4014 R Channel 0 Current Destination Address Register 0x0000.0000 GDMA_CDST1 0xFFF0.4034 R Channel 1 Current Destination Address Register 0x0000.
W90N740 7.8 USB Host Controller The Universal Serial Bus (USB) is a low-cost, low-to-middle speed peripheral interface standard intended for modem, printer, scanner, PDA, keyboard, mouse, and other devices that do not require a high-bandwidth parallel interface. The USB is a 4-wire serial cable bus that supports serial data exchange between a Host Controller and a peripheral device. The attached peripherals share USB bandwidth through a host-scheduled, token-based protocol.
W90N740 7.8.1 USB Host Controller Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE HcRevision 0xFFF0.5000 R HcControl 0xFFF0.5004 R/W Host Controller Control Register 0x0000.0000 HcCommandStatus 0xFFF0.5008 R/W Host Controller Command Status Register 0x0000.0000 HcInterruptStatus 0xFFF0.500C R/W Host Controller Interrupt Status Register HcInterruptEnable 0xFFF0.5010 R/W Host Controller Interrupt Enable Register 0x0000.0000 HcInterruptDisable 0xFFF0.
W90N740 Host Controller Revision Register (HcRevision) Register Address R/W HcRevision 0xFFF0.5000 R Description Host Controller Revision Register Reset Value 0x0000.0010 Register: HcRevision Bits Reset R/W Description Revision 7-0 10h R Indicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.0 specification. (X.Y = XYh) 31-8 0h - Reserved.
W90N740 Register: HcControl Bits Reset R/W 5 0b R/W Description BulkListEnable When set this bit enables processing of the Bulk list. HostControllerFunctionalState This field sets the Host Controller state. The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port.
W90N740 Host Controller Command Status Register (HcCommandStatus) Register Address R/W HcCommandStatus 0xFFF0.5008 R/W Description Host Controller Command Status Register Reset Value 0x0000.0000 Register: HcCommandStatus Bits Reset R/W 0 0b R/W Description HostControllerReset This bit is set to initiate the software reset. This bit is cleared by the Host Controller, upon completed of the reset operation. ControlListFilled 1 0b R/W Set to indicate there is an active ED on the Control List.
W90N740 Host Controller Interrupt Status Register (HcInterruptStatus) All bits are set by hardware and cleared by software. Register Address HcInterruptStatus 0xFFF0.500C R/W Description R/W Host Controller Interrupt Status Register Reset Value 0x0000.0000 Register: HcInterruptStatus Bits Reset R/W 0 0b R/W 1 0b R/W 2 0b R/W 3 0b R/W 4 0b R 5 0b R/W 6 0b R/W 29-7 0h - Description SchedulingOverrun Set when the List Processor determines a Schedule Overrun has occurred.
W90N740 Host Controller Interrupt Enable Register (HcInterruptEnable) Writing a ‘1’ to a bit in this register sets the corresponding bit, while writing a ‘0’ leaves the bit unchanged. Register Address HcInterruptEnable 0xFFF0.5010 R/W Description R/W Host Controller Interrupt Enable Register Reset Value 0x0000.
W90N740 Host Controller Interrupt Disable Register (HcInterruptDisable) Writing a ‘1’ to a bit in this register clears the corresponding bit, while writing a ‘0’ to a bit leaves the bit nchanged. Register Address HcInterruptDisable 0xFFF0.5014 R/W Description R/W Host Controller Interrupt Disable Register Reset Value 0x0000.0000 Register: HcInterruptDisable Bits Reset R/W Description SchedulingOverrunEnable 0 0b R/W 0: Ignore 1: Disable interrupt generation due to Scheduling Overrun.
W90N740 Host Controller Communication Area Register (HcHCCA) Register HcHCCA Address R/W Description Reset Value R/W Host Controller Communication Area Register 0x0000.0000 0xFFF0.5018 Register: HcHCCA Bits Reset R/W 31-8 0h R/W Description HCCA Pointer to HCCA base address. Host Controller Period Current ED Register (HcPeriodCurrentED) Register HcPeriodCurrentED Address R/W Description 0xFFF0.501C R/W Host Controller Period Current ED Register Reset Value 0x0000.
W90N740 Host Controller Control Current ED Register (HcControlCurrentED) Register Address HcControlCurrentED R/W Description Reset Value Host Controller Control Current ED Register 0xFFF0.5024 R/W 0x0000.0000 Register: HcControlCurrentED Bits Reset R/W 3-0 0h - 31-4 0h R/W Description Reserved. Read/Write 0's ControlCurrentED Pointer to the current Control List ED. Host Controller Bulk Head ED Register (HcBulkHeadED) Register HcBulkHeadED Address R/W 0xFFF0.
W90N740 Host Controller Bulk Current ED Register (HcBulkCurrentED) Register HcBulkCurrentED Address 0xFFF0.502C R/W Description R/W Host Controller Bulk Current ED Register Reset Value 0x0000.0000 Register: HcBulkCurrentED Bits Reset R/W 3-0 0h - 31-4 0h R/W Description Reserved. Read/Write 0's BulkCurrentED Pointer to the current Bulk List ED. Host Controller Done Head Register (HcDoneHead) Register HcDoneHead Address R/W 0xFFF0.
W90N740 Register: HcFmInterval Bits Reset R/W Description FSLargestDataPacket 30-16 This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. FrameIntervalToggle 31 This bit is toggled by HCD when it loads a new value into FrameInterval. Host Controller Frame Remaining Register (HcFrameRemaining) Register HcFrameRemaining Address R/W 0xFFF0.5038 R Description Host Controller Frame Remaining Register Reset Value 0x0000.
W90N740 Host Controller Periodic Start Register (HcPeriodicStart) Register HcPeriodicStart Address R/W 0xFFF0.5040 R/W Description Reset Value Host Controller Periodic Start Register 0x0000.0000 Register: HcPeriodicStart Bits Reset R/W Description 13-0 0b R/W PeriodicStart This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. 31-14 0h - Reserved.
W90N740 Host Controller Root Hub Descriptor A Register (HcRhDescriptorA) This register is only reset by a power-on reset. It is written during system initialization to configure the Root Hub. This bit should not be written during normal operation. Register HcRhDescriptorA Address R/W 0xFFF0.5048 R/W Description Host Controller Root Hub Descriptor A Register Reset Value 0x0100.
W90N740 Host Controller Root Hub Descriptor B Register (HcRhDescriptorB) This register is only reset by a power-on reset. It is written during system initialization to configure the Root Hub. These bits should not be written during normal operation. Register HcRhDescriptorB Address R/W 0xFFF0.504C R/W Description Host Controller Root Hub Descriptor B Register Reset Value 0x0000.0000 Register: HcRhDescriptorB Bits Reset R/W Description DeviceRemoveable HYDRA-4 ports default to removable devices.
W90N740 Host Controller Root Hub Status Register (HcRhStatus) This register is reset by the USBRESET state. Register HcRhStatus Address R/W 0xFFF0.5050 R/W Description Host Controller Root Hub Status Register Reset Value 0x0000.0000 Register: HcRhStatus Bits Reset R/W Description (Read) LocalPowerStatus Not Supported. Always read '0'. 0 0 R/W (Write) ClearGlobalPower Writing a '1' issues a ClearGlobalPower command to the ports. Writing a '0' has no effect.
W90N740 Host Controller Root Hub Port Status (HcRhPortStatus [1:2]) This register is reset by the USBRESET state. Register Address R/W Description Reset Value HcRhPortStatus [1] 0xFFF0.5054 R/W Host Controller Root Hub Port Status [1] 0x0000.0000 HcRhPortStatus [2] 0xFFF0.5058 R/W Host Controller Root Hub Port Status [2] 0x0000.0000 Register: HcRhPortStatus[1:2] Bits 0 Reset 0 R/W R/W Description (Read) CurrentConnectStatus 0 = No device connected. 1 = Device connected.
W90N740 Register: HcRhPortStatus[1:2] Bits Reset R/W 7-5 0h - 8 0 R/W Description Reserved. Read/Write 0's (Read) PortPowerStatus This bit reflects the power state of the port regardless of the power switching mode. 0 = Port power is off. 1 = Port power is on. Note: If NoPowerSwitching is set, this bit is always read as '1'. (Write) SetPortPower Writing a '1' sets PortPowerStatus. Writing a '0' has no effect.
W90N740 7.9 UART Controller The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data characters received from the peripheral such as MODEM, and a parallel-to-serial conversion on data characters received from the CPU. There are five types of interrupts, i.e., line status interrupt, transmitter FIFO empty interrupt, receiver threshold level reaching interrupt, time out interrupt, and MODEM status interrupt.
W90N740 7.9.1 UART Control Registers Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RBR 0xFFF8.0000 R Receive Buffer Register (DLAB = 0) Undefined THR 0xFFF8.0000 W Transmit Holding Register (DLAB = 0) Undefined IER 0xFFF8.0004 R/W Interrupt Enable Register (DLAB = 0) 0x0000.0000 DLL 0xFFF8.0000 R/W DLM 0xFFF8.0004 R/W IIR 0xFFF8.0008 R Interrupt Identification Register FCR 0xFFF8.
W90N740 Transmit Holding Register (THR) Register Address R/W THR 0xFFF8.0000 W 7 6 Description Reset Value Transmit Holding Register (DLAB = 0) 5 4 3 Undefined 2 1 0 8-bit Transmitted Data 8-bit Transmitted Data [7:0] By writing to this register, the UART will send out an 8-bit data through the SOUT pin (LSB first). Interrupt Enable Register (IER) Register Address R/W IER 0xFFF8.0004 R/W 7 6 RESERVED 5 Description Reset Value Interrupt Enable Register (DLAB = 0) 0x0000.
W90N740 RDAIE [0]: Receive Data Available Interrupt (Irpt_RDA) Enable and Time-out Interrupt (Irpt_TOUT) Enable 0 = Mask off Irpt_RDA and Irpt_TOUT 1 = Enable Irpt_RDA and Irpt_TOUT Divider Latch (Low Byte) Register (DLL) Register Address R/W DLL 0xFFF8.0000 R/W 7 6 Description Reset Value Divisor Latch Register (LS) (DLAB = 1) 5 4 3 0x0000.
W90N740 Interrupt Identification Register (IIR) Register Address R/W IIR 0xFFF8.0008 R 7 FMES 6 Description Reset Value Interrupt Identification Register 5 RFTLS 4 DMS 3 0x8181.8181 2 IID 1 0 NIP FMES [7]: FIFO Mode Enable Status This bit indicates whether the FIFO mode is enabled or not. Since the FIFO mode is always enable, this bit always shows the logical 1 when CPU is reading this register.
W90N740 FIFO Control Register (FCR) Register Address R/W FCR 0xFFF8.0008 W 7 6 Reset Value FIFO Control Register 5 RFITL Description 4 RESERVED Undefined 3 2 1 0 DMS TFR RFR FME RFITL [7:6]: RX FIFO Interrupt (Irpt_RDA) Trigger Level RFITL [7:6] Irpt_RDA Trigger Level (Bytes) 00 01 01 04 10 08 11 14 DMS [3]: DMA Mode Select The DMA function is not implemented in this version. TFR [2]: TX FIFO Reset Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO.
W90N740 Line Control Register (LCR) Register Address R/W LCR 0xFFF8.000C R/W Description Reset Value Line Control Register 0x0000.0000 7 6 5 4 3 2 DLAB BCB SPE EPE PBE NSB 1 0 WLS DLAB [7]: Divider Latch Access Bit 0 = It is used to access RBR, THR or IER. 1 = It is used to access Divisor Latch Registers {DLL, DLM}. BCB [6]: Break Control Bit When this bit is set to logic 1, the serial data output (SOUT) is forced to the Spacing State (logic 0).
W90N740 WLS [1:0]: Word Length Select WLS[1:0] Character length 00 5 bits 01 6 bits 10 7 bits 11 8 bits Modem Control Register (MCR) Register Address R/W MCR 0xFFF8.0010 R/W 7 6 Description Reset Value Modem Control Register 5 RESERVED 0x0000.
W90N740 Line Status Control Register (LSR) Register Address R/W LSR 0xFFF8.0014 R Description Reset Value Line Status Register 0x6060.6060 7 6 5 4 3 2 1 0 ERR_RX TE THRE BII FEI PEI OEI RFDR ERR_RX [7]: RX FIFO Error 0 = RX FIFO works normally 1 = There is at least one parity error (PE), framing error (FE), or break indication (BI) in the FIFO. ERR_RX is cleared when CPU reads the LSR and if there are no subsequent errors in the RX FIFO.
W90N740 PEI [2]: Parity Error Indicator This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU reads the contents of the LSR. OEI [1]: Overrun Error Indicator An overrun error will occur only after the RX FIFO is full and the next character has been completely received in the shift register. The character in the shift register is overwritten, but it is not transferred to the RX FIFO.
W90N740 TERI [2]: Tailing Edge of RI# This bit is set whenever RI# input has changed from high to low, and it will be reset if the CPU reads the MSR. DDSR [1]: DSR# State Change This bit is set whenever DSR# input has changed state, and it will be reset if the CPU reads the MSR. DCTS [0]: CTS# State Change This bit is set whenever CTS# input has changed state, and it will be reset if the CPU reads the MSR. Whenever any of MSR [3:0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1.
W90N740 7.10 TIMER Controller 7.10.1 General Timer Controller The timer module has two channels, TIMER0 and TIMER1, which allow you to easily implement a counting scheme for use. The timer can perform functions like frequency measurement, event counting, interval measurement, pulse generation, delay timing, and so on. The timer possesses features such as adjustable resolution, programmable counting period, and detailed information.
W90N740 7.10.3 Timer Control Registers Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Address R/W/C Description Reset Value TCR0 0xFFF8.1000 R/W Timer Control Register 0 0x0000.0005 TCR1 0xFFF8.1004 R/W Timer Control Register 1 0x0000.0005 TICR0 0xFFF8.1008 R/W Timer Initial Control Register 0 0x0000.00FF TICR1 0xFFF8.100C R/W Timer Initial Control Register 1 0x0000.00FF TDR0 0xFFF8.1010 R Timer Data Register 0 0x0000.
W90N740 0 = Disables timer interrupt 1 = Enables timer interrupt. If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter decrements to zero. MODE [28:27]: Timer Operating Mode MODE [28:27] Timer Operating Mode 00 The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if IE is enabled) and CE is automatically cleared then. 01 The timer is operating in the periodic mode.
W90N740 TIC [23:0]: Timer Initial Count This is a 24-bit value representing the initial count. Timer will reload this value whenever the counter is decremented to zero. Timer Data Register 0 (TDR0) Timer Data Register 1 (TDR1) Register Address R/W/C TDR0 0xFFF8.1010 R Timer Data Register 0 0x0000.00FF TDR1 0xFFF8.1014 R Timer Data Register 1 0x0000.
W90N740 Timer Interrupt Status Register (TISR) Register Address R/W/C TISR 0xFFF8.1018 R/C 31 30 Description Reset Value Timer Interrupt Status Register 29 28 27 0x0000.0000 26 25 24 18 17 16 10 9 8 2 1 0 TIF1 TIF0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 RESERVED TIF1 [1]: Timer Interrupt Flag 1 It indicates the interrupt status of the timer 1. 0 = It indicates that the timer 1 does not count down to zero yet.
W90N740 Watchdog Timer Control Register (WTCR) Register WTCR 31 Address R/W/C Description Reset Value 0xFFF8.101C R/W Watchdog Timer Control Register 0x0000.
W90N740 WTIS [5:4] Interrupt Time-out Reset Time-out 20 00 2 clocks 220 + 512 clocks 01 221 clocks 221 + 512 clocks 10 222 clocks 222 + 512 clocks 11 223 clocks 223 + 512 clocks WTIF [3]: Watchdog Timer Interrupt Flag If the watchdog interrupt is enabled, then the hardware will set this bit to indicate that the watchdog interrupt has occurred. If the watchdog interrupt is not enabled, then this bit indicates that a time-out period has elapsed.
W90N740 7.11 Advanced Interrupt Controller (AIC) An interrupt temporarily changes the sequence of program execution to react to a particular event such as power failure, watchdog timer timeout, transmit/receive request from Ethernet MAC Controller, and so on. The ARM7TDMI processor provides two modes of interrupt, the Fast Interrupt (FIQ) mode for critical session and the Interrupt (IRQ) mode for general purpose. The IRQ exception is occurred when the nIRQ input is asserted.
W90N740 7.11.1 Interrupt Sources The table as shown below lists all the interrupt sources originated from internal peripherals and external devices. Please be careful that interrupt channel 0 and all that beyond 18 are undefined in this implementation. Table 7.11.
W90N740 7.11.2 AIC Registers Map REGISTER ADDRESS R/W DESCRIPTION AIC_SCR1 0xFFF8.2004 R/W Source Control Register 1 0x0000.0047 AIC_SCR2 0xFFF8.2008 R/W Source Control Register 2 0x0000.0047 AIC_SCR3 0xFFF8.200C R/W Source Control Register 3 0x0000.0047 AIC_SCR4 0xFFF8.2010 R/W Source Control Register 4 0x0000.0047 AIC_SCR5 0xFFF8.2014 R/W Source Control Register 5 0x0000.0047 AIC_SCR6 0xFFF8.2018 R/W Source Control Register 6 0x0000.0047 AIC_SCR7 0xFFF8.
W90N740 AIC Source Control Registers (AIC_SCR1 ~ AIC_SCR18) Register Address R/W AIC_SCR1 0xFFF8.2004 R/W Source Control Register 1 0x0000.0047 AIC_SCR2 0xFFF8.2008 R/W Source Control Register 2 0x0000.0047 yyy yyy yyy Description Reset Value yyy yyy AIC_SCR17 0xFFF8.2044 R/W Source Control Register 17 0x0000.0047 AIC_SCR18 0xFFF8.2048 R/W Source Control Register 18 0x0000.
W90N740 AIC Interrupt Raw Status Register (AIC_IRSR) Register Address R/W AIC_IRSR 0xFFF8.2100 R 31 30 29 Description Reset Value 0x0000.0000 Interrupt Raw Status Register 28 27 26 25 24 19 18 17 16 IRS18 IRS17 IRS16 RESERVED 23 22 21 20 RESERVED 15 14 13 12 11 10 9 8 IRS15 IRS14 IRS13 IRS12 IRS11 IRS10 IRS9 IRS8 7 6 5 4 3 2 1 0 IRS7 IRS6 IRS5 IRS4 IRS3 IRS2 IRS1 RESERVED This register records the intrinsic state within each interrupt channel.
W90N740 AIC Interrupt Active Status Register (AIC_IASR) Register Address R/W AIC_IASR 0xFFF8.2104 R 31 30 29 Description Reset Value 0x0000.
W90N740 AIC Interrupt Status Register (AIC_ISR) Register Address R/W AIC_ISR 0xFFF8.2108 R 31 30 Description Reset Value 0x0000.0000 Interrupt Status Register 29 28 27 26 25 24 18 17 16 IS18 IS17 IS16 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 10 9 8 IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8 7 6 5 4 3 2 1 0 IS7 IS6 IS5 IS4 IS3 IS2 IS1 RESERVED This register identifies those interrupt channels whose are both active and enabled.
W90N740 AIC IRQ Priority Encoding Register (AIC_IPER) Register Address R/W AIC_IPER 0xFFF8.210C R Description Reset Value 0x0000.
W90N740 AIC Interrupt Source Number Register (AIC_ISNR) Register Address R/W AIC_ISNR 0xFFF8.2110 R Description Reset Value 0x0000.0000 Interrupt Source Number Register 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 IRQID The purpose of this register is to record the interrupt channel number that is active, enabled, and has the highest priority.
W90N740 AIC Interrupt Mask Register (AIC_IMR) Register Address R/W AIC_IMR 0xFFF8.2114 R 31 30 29 Description Reset Value 0x0000.0000 Interrupt Mask Register 28 27 26 25 24 19 18 17 16 IM18 IM17 IM16 RESERVED 23 22 21 20 RESERVED 15 14 13 12 11 10 9 8 IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 7 6 5 4 3 2 1 0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 RESERVED IMx: Interrupt Mask This bit determines whether the corresponding interrupt channel is enabled or disabled.
W90N740 AIC Output Interrupt Status Register (AIC_OISR) Register Address R/W AIC_OISR 0xFFF8.2118 R 31 30 29 Description Reset Value 0x0000.0000 Output Interrupt Status Register 28 27 26 25 24 18 17 16 10 9 8 2 1 0 IRQ FIQ RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 RESERVED The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted interrupt is FIQ or IRQ.
W90N740 AIC Mask Enable Command Register (AIC_MECR) Register Address R/W AIC_MECR 0xFFF8.
W90N740 AIC Mask Disable Command Register (AIC_MDCR) Register Address AIC_MDCR 0xFFF8.
W90N740 AIC Source Set Command Register (AIC_SSCR) Register Address R/W AIC_SSCR 0xFFF8.
W90N740 AIC Source Clear Command Register (AIC_SCCR) Register Address R/W Description Reset Value AIC_SCCR 0xFFF8.
W90N740 AIC End of Service Command Register (AIC_EOSCR) Register Address AIC_EOSCR 0xFFF8.
W90N740 7.12 General-Purpose Input/Output Controller (GPIO) The General-Purpose Input/Output (GPIO) module possesses 21 pins and serves multiple purposes.
W90N740 7.12.1 GPIO Controller Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG 0xFFF8.3000 R/W GPIO Configuration Register 0x0000.0000 GPIO_DIR 0xFFF8.3004 R/W GPIO Direction Register 0x0000.0000 GPIO_DATAOUT 0xFFF8.3008 R/W GPIO Data Output Register 0x0000.0000 GPIO_DATAIN 0xFFF8.300C R DEBNCE_CTRL 0xFFF8.3010 R/W GPIO Data Input Register Undefined De-bounce Control Register 0x0000.
W90N740 GPIOCFG19 [19:18]: Operating mode for GPIO19 GPIOCFG19 GPIO19 11 Name RESERVED 10 Type I 01 Name Type RESERVED Name nIRQ2 00 Type I Name GP19 Type IO nIRQ2 is one of the external interrupt input pins. GPIOCFG18 [17:16]: Operating mode for GPIO18 11 GPIOCFG18 GPIO18 Name Type RESERVED I 10 Name OVRCU R 01 00 Type Name Type Name Type I nIRQ1 I GP18 IO OVRCUR is used as over current indicator if this field set to 10. nIRQ1 is one of the external interrupt input pins.
W90N740 GPIOCFG13 [9:8]: Operating mode for GPIO13 GPIOCFG13 GPIO13 11 10 Name RESERVED Type O Name STDBY 01 Type O Name TIMER0 00 Type O Name GP13 Type IO STDBY is a USB IO port, which controls the external USB transceiver power-down mode. TIMER0 is the tone output of TIMER0. GPIOCFG12 [7:6]: Operating mode for GPIO12 GPIOCFG12 GPIO12 11 10 Name RESERVED Type IO Name PWREN 01 Type IO Name nWDOG 00 Type O Name GP12 Type IO nWDOG is the timeout output of Watch-Dog Timer.
W90N740 GPIOCFG3_0 [1:0]: Operating mode for GPIO3, GPIO2, GPIO1, and GPIO0 GPIOCFG3_0 11 Name 10 Type Name 01 Type GPIO3 GPIO2 RESERVED GPIO1 RESERVED 00 Name Type Name Type NXDREQ2 IU GP3 I/O NXDREQ1 IU GP2 I/O NWTC O GP1 I/O NRTC O GP0 I/O GPIO0 GPIO Direction Register (GPIO_DIR) Register Address R/W Description GPIO_DIR 0xFFF8.3004 R/W GPIO Direction Register 31 30 29 28 27 Reset Value 0x0000.
W90N740 GPIO Data Output Register (GPIO_DATAOUT) Register Address GPIO_DATAOUT 31 R/W 0xFFF8.3008 R/W 30 29 Description Reset Value GPIO Data Output Register 28 0x0000.
W90N740 Debounce Control Register (DEBNCE_CTRL) Register Address R/W DEBNCE_CTRL 0xFFF8.3010 R/W 31 30 29 Description Reset Value De-bounce Control Register 28 27 0x0000.0000 26 25 24 18 17 16 10 9 8 3 2 1 0 DBE3 DBE2 DBE1 DBE0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 RESERVED 6 5 4 DBCLKSEL DBCLKSEL [6:4]: De-bounce Clock Rate Selector These three bits are used to select the clock rate for de-bouncer circuit.
W90N740 8. ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings Ambient Temperature...............................……………............................ 0 °C ~ 70 °C Storage Temperature ..................................................…….................... -40 °C ~ 125°C Voltage on Any Pin ...............................................................…….......... -0.5V ~ 6V Power Supply Voltage (Core logic) .............................…...........……….. 1.62V ~ 1.
W90N740 8.2 DC Characteristics (Normal test conditions: VDD33/USBVDD = 3.3V+/- 0.3V, VDD18/DVDD18/AVDD18 = 1.8V+/- 0.18V TA = 0 °C ~ 70 °C unless otherwise specified) SYMBOL MIN. MAX. UNIT Power Supply 3.00 3.60 V Power Supply 1.62 1.98 V VIL Input Low Voltage -0.3 0.8 V VIH Input High Voltage 2.0 5.5 V VT+ Schmitt Trigger positive-going threshold 1.47 1.5 V VT- Schmitt trigger negative-going threshold 0.89 0.95 V VOL Output Low Voltage Depend on driving 0.
W90N740 8.3 AC Characteristics 8.3.1 EBI/SDRAM Interface AC Characteristics 1.5V MCLK TDH TDSU D[31:0] MCLK Input Valid 1.5V 1.5V 1.5V TDO Output Delay Output Valid 1.5V SYM. PARAMETER MIN. MAX. UNIT TDSU D [31:0] Setup Time 2 nS TDH D [31:0] Hold Time 3 nS TDO D [31:0], A [24:0], nSCS [1:0], SDQM [3:0], CKE, nSWE, nSRAS, nSCAS 2 8.3.2 7 nS EBI/External Master Interface AC Characteristics MCLK EMREQ TEMSU TEMAO EMACK SYM. TEMH TEMAO DESCRIPTION MIN. MAX.
W90N740 8.3.3 EBI/(ROM/SRAM/External I/O) AC Characteristics MCLK TNECSO TNECSO nECS[3:0] TADDO A[24:0] Address Valid TNOEO nOE TNOEO TDSU D[31:0] nWAIT TDH R Data TNWASU TNWAH nWBE[3:0] TNWBO TNWBO TDO D[31:0] SYMBOL Write Data Vaild DESCRIPTION MIN. MAX.
W90N740 8.3.4 USB Transceiver AC Characteristics Rise Time CL Differential Data Lines CL Fall Time 90% 90% 10% 10% tR Full Speed: 4 to 20ns at CL = 50pF tF Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF Data Signal Rise and Fall Time USB Transceiver AC Characteristics SYM. DESCRIPTION CONDITIONS MIN. MAX. UNIT TR Rise Time (Full Speed) CL = 50 pF 4 20 nS TF Fall Time (Full Speed CL = 50 pF 4 20 nS 90 112 % 11.97 12.
W90N740 8.3.5 EMC MII AC Characteristics The signal timing characteristics conforms to the guidelines specified in IEEE Std. 802.3. TX_CLK TTXO TX_D [3:0] TX_EN TX_ERR Valid Transmit Signal Timing Relationships at MII RX_CLK TRXSU RX_D [3:0] RX_DV RX_ERR TRXH VALID INPUT Receive Signal Timing Relationships at MII SYMBOL DESCRIPTION MIN. MAX.
W90N740 MDC TMDSU TMDH VALID INPUT MDIO MDIO Read From PHY Timing MDC TMDO V a lid M D IO MDIO Write to PHY Timing SYMBOL DESCRIPTION MIN. MAX.
W90N740 9.
W90N740 10. W90N740 REGISTERS MAPPING TABLE R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written System Manager Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PDID 0xFFF0.0000 R Product Identifier Register 0xX090.0740 ARBCON 0xFFF0.0004 R/W Arbitration Control Register 0x0000.0000 PLLCON 0xFFF0.0008 R/W PLL Control Register 0x0000.2F01 CLKSEL 0xFFF0.000C R/W Clock Select Register 0x0000.
W90N740 EMC 0 Control registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM REGISTERS CAMCMR_0 0xFFF0.3000 R/W CAM Command Register 0x0000.0000 CAMEN_0 0xFFF0.3004 R/W CAM enable register 0x0000.0000 CAM1M_0 0xFFF0.3008 R/W CAM1 Most Significant Word Register 0x0000.0000 CAM1L_0 0xFFF0.300C R/W CAM1 Least Significant Word Register 0x0000.0000 CAM2M_0 0xFFF0.3010 R/W CAM2 Most Significant Word Register 0x0000.0000 CAM2L_0 0xFFF0.
W90N740 EMC 0 Control registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM REGISTERS CAM15M_0 0xFFF0.3078 R/W CAM15 Most Significant Word Register 0x0000.0000 CAM15L_0 0xFFF0.307C R/W CAM15 Least Significant Word Register 0x0000.0000 CAM16M_0 0xFFF0.3080 R/W CAM16 Most Significant Word Register 0x0000.0000 CAM16L_0 0xFFF0.3084 R/W CAM16 Least Significant Word Register 0x0000.0000 MAC REGISTERS MIEN_0 0xFFF0.3088 R/W MAC Interrupt Enable Register 0x0000.
W90N740 EMC 0 Status Registers REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MAC REGISTERS MISTA_0 0xFFF0.30B4 R/W MAC Interrupt Status Register 0x0000.0000 MGSTA_0 0xFFF0.30B8 R/W MAC General Status Register 0x0000.0000 MRPC_0 0xFFF0.30BC R MAC Receive Pause count register 0x0000.0000 MRPCC_0 0xFFF0.30C0 R MAC Receive Pause Current Count Register 0x0000.0000 MREPC_0 0xFFF0.30C4 R MAC Remote pause count register 0x0000.0000 DMA REGISTERS DMARFS_0 0xFFF0.
W90N740 EMC 1 Control Registers REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM REGISTERS CAMCMR_1 0xFFF0.3800 R/W CAM Command Register 0x0000.0000 CAMEN_1 0xFFF0.3804 R/W CAM enable register 0x0000.0000 CAM1M_1 0xFFF0.3808 R/W CAM1 Most Significant Word Register 0x0000.0000 CAM1L_1 0xFFF0.380C R/W CAM1 Least Significant Word Register 0x0000.0000 CAM2M_1 0xFFF0.3810 R/W CAM2 Most Significant Word Register 0x0000.0000 CAM2L_1 0xFFF0.
W90N740 REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM REGISTERS CAM14M_1 0xFFF0.3870 R/W CAM14 Most Significant Word Register 0x0000.0000 CAM14L_1 0xFFF0.3874 R/W CAM14 Least Significant Word Register 0x0000.0000 CAM15M_1 0xFFF0.3878 R/W CAM15 Most Significant Word Register 0x0000.0000 CAM15L_1 0xFFF0.387C R/W CAM15 Least Significant Word Register 0x0000.0000 CAM16M_1 0xFFF0.3880 R/W CAM16 Most Significant Word Register 0x0000.0000 CAM16L_1 0xFFF0.
W90N740 EMC 1 Status Registers REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MAC REGISTERS MISTA_1 0xFFF0.38B4 R/W MAC Interrupt Status Register 0x0000.0000 MGSTA_1 0xFFF0.38B8 R/W MAC General Status Register 0x0000.0000 MRPC_1 0xFFF0.38BC R MAC Receive Pause count register 0x0000.0000 MRPCC_1 0xFFF0.38C0 R MAC Receive Pause Current Count Register 0x0000.0000 MREPC_1 0xFFF0.38C4 R MAC Remote pause count register 0x0000.0000 DMA REGISTERS DMARFS_1 0xFFF0.
W90N740 USB Host Controller Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE HcRevision 0xFFF0.5000 R HcControl 0xFFF0.5004 R/W Host Controller Control Register 0x0000.0000 HcCommandStatus 0xFFF0.5008 R/W Host Controller Command Status Register 0x0000.0000 HcInterruptStatus 0xFFF0.500C R/W Host Controller Interrupt Status Register 0x0000.0000 HcInterruptEnable 0xFFF0.5010 R/W Host Controller Interrupt Enable Register 0x0000.0000 HcInterruptDisable 0xFFF0.
W90N740 NATA Registers Map REGISTER OFFSET R/W DESCRIPTION RESET VALUE NATA Control and Status Registers NATCMD 0xFFF0.6000 R/W NAT Command Register 0x0000.0000 NATCCLR0 0xFFF0.6010 W NAT Counter 0 Clear Register 0x0000.0000 NATCCLR1 0xFFF0.6014 W NAT Counter 1 Clear Register 0x0000.0000 NATCCLR2 0xFFF0.6018 W NAT Counter 2 Clear Register 0x0000.0000 NATCCLR3 0xFFF0.601C W NAT Counter 3 Clear Register 0x0000.0000 NATCFG0 0xFFF0.
W90N740 REGISTER OFFSET R/W DESCRIPTION RESET VALUE Address Lookup and Replacement Registers MASAD0 0xFFF0.6800 R/W NAT Masquerading IP Address Entry 0 0x0000.0000 MASPN0 0xFFF0.6804 R/W NAT Masquerading Port Number Entry 0 0x0000.0000 LSAD0 0xFFF0.6808 R/W Local Station IP Address Entry 0 0x0000.0000 LSPN0 0xFFF0.680C R/W Local Station Port Number Entry 0 0x0000.0000 LSMAC0M 0xFFF0.6810 R/W Local Station MAC Address Most Significant Word Register for Entry 0 0x0000.
W90N740 UART Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RBR 0xFFF8.0000 R Receive Buffer Register (DLAB = 0) Undefined THR 0xFFF8.0000 W Transmit Holding Register (DLAB = 0) Undefined IER 0xFFF8.0004 R/W Interrupt Enable Register (DLAB = 0) 0x0000.0000 DLL 0xFFF8.0000 R/W Divisor Latch Register (LS) (DLAB = 1) 0x0000.0000 DLM 0xFFF8.0004 R/W Divisor Latch Register (MS) (DLAB = 1) 0x0000.0000 IIR 0xFFF8.0008 R Interrupt Identification Register 0x8181.
W90N740 AIC Registers Map REGISTER ADDRESS R/W DESCRIPTION AIC_SCR1 0xFFF8.2004 R/W Source Control Register 1 0x0000.0047 AIC_SCR2 0xFFF8.2008 R/W Source Control Register 2 0x0000.0047 AIC_SCR3 0xFFF8.200C R/W Source Control Register 3 0x0000.0047 AIC_SCR4 0xFFF8.2010 R/W Source Control Register 4 0x0000.0047 AIC_SCR5 0xFFF8.2014 R/W Source Control Register 5 0x0000.0047 AIC_SCR6 0xFFF8.2018 R/W Source Control Register 6 0x0000.0047 AIC_SCR7 0xFFF8.
W90N740 11. ORDERING INFORMATION PART NUMBER NAME PACKAGE DESCRIPTION W90N740CD LQFP176 176 Leads, body 22 x 22 x 1.4 mm W90N740CDG LQFP176 176 Leads, body 22 x 22 x 1.4 mm, Lead free package 12. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A1 Jan 15, 2003 - Initial Issued A2 May 27, 2003 - Add DC specifications in 8.2 A3 Sep. 3, 2004 A4 Nov. 26, 2004 Change Pin Description Page 54 Change tCOH description Page 56 Remove Fig. 7.3.
