W90N745CD/W90N745CDG 32-BIT ARM7TDMI-BASED MCU W90N745 16/32-bit ARM microcontroller Product Data Sheet
W90N745CD/W90N745CDG Revision History REVISION DATE COMMENTS A 2006/06/23 Draft A1 2006/08/30 Add Electrical specification A2 2006/09/22 Delete Chapter 6: BLOCK DIAGRAM -I- Publication Release Date: September 22, 2006 Revision A2
W90N745CD/W90N745CDG Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 1 2. FEATURES ................................................................................................................................. 2 3. PIN DIAGRAM ............................................................................................................................ 7 4. PIN ASSIGNMENT ................................
W90N745CD/W90N745CDG 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.8.2 Standard Device Request.............................................................................................192 6.8.3 USB Device Register Description .................................................................................192 Audio Controller .......................................................................................................... 231 6.9.1 I²S Interface....................................
W90N745CD/W90N745CDG 6.18 7. PS2 Host Interface Controller ..................................................................................... 380 6.18.1 PS2 Host Controller Interface Register Map...............................................................381 6.18.2 Register Description ...................................................................................................382 ELECTRICAL SPECIFICATIONS.....................................................................................
W90N745CD/W90N745CDG 1. GENERAL DESCRIPTION The W90N745 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which designed by Advanced RISC Machines, Ltd. It offers 4K-byte I-cache/SRAM and 4K-byte Dcache/SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost sensitive and power sensitive applications. One 100/10 Mbit MAC of Ethernet controller is built-in to reduce total system cost.
W90N745CD/W90N745CDG 2.
W90N745CD/W90N745CDG DMA Controller • 2-channel general DMA for memory-to-memory data transfers without CPU intervention • Initialed by a software or external DMA request • Increments or decrements a source or destination address in 8-bit, 16-bit or 32-bit data transfers • 4-data burst mode UART • Four UART (serial I/O) blocks with interrupt-based operation • Support for 5-bit, 6-bit, 7-bit or 8-bit serial data transmit and receive • Programmable baud rates • 1, ½ or 2 stop bits • Odd or ev
W90N745CD/W90N745CDG USB Host Controller • USB 1.1 compliant • Compatible with Open HCI 1.0 specification • Supports low-speed and full speed devices • Build-in DMA for real time data transfer • Two on-chip USB transceivers with one optionally shared with USB device controller USB Device Controller • USB 1.
W90N745CD/W90N745CDG • Supports 7 bit addressing mode • Software mode I2C Universal Serial Interface (USI) • 1-channel USI • Support USI (Microwire/SPI) master mode • Full duplex synchronous serial data transfer • Variable length of transfer word up to 32 bits • Provide burst mode operation, transmit/receive can be executed up to four times in one transfer • MSB or LSB first data transfer • Rx and Tx on both rising or falling edge of serial clock independently • Two slave/device select li
W90N745CD/W90N745CDG Power management • Programmable clock enables for individual peripheral • IDLE mode to halt ARM core and keep peripheral working • Power-Down mode to stop all clocks included external crystal oscillator. • Exit IDLE by all interrupts y Exit Power-Down by keypad,USB device and external interrupts Operation Voltage Range • 3.0 ~ 3.6 V for IO buffer • 1.62 ~ 1.
W90N745CD/W90N745CDG 3. PIN DIAGRAM Figure 3.
W90N745CD/W90N745CDG 4. PIN ASSIGNMENT Table 4.
W90N745CD/W90N745CDG Table 4.
W90N745CD/W90N745CDG Table 4.
W90N745CD/W90N745CDG Table 4.
W90N745CD/W90N745CDG Table 4.
W90N745CD/W90N745CDG 5. PIN DESCRIPTION Table 5.
W90N745CD/W90N745CDG Table 5.1 W90N745 Pins Description, continued PIN NAME IO TYPE DESCRIPTION IOU RMII Management Data Clock for Ethernet. It is the reference clock of MDIO. Each MDIO data will be latched at the rising edge of MDC clock. General Programmable In/Out Port [29] Keypad ROW[1] scan output. IO RMII Management Data I/O for Ethernet. It is used to transfer RMII control and status information between PHY and MAC. General Programmable In/Out Port [28] Keypad ROW[0] scan output.
W90N745CD/W90N745CDG Table 5.
W90N745CD/W90N745CDG Table 5.1 W90N745 Pins Description, continued PIN NAME IO TYPE DESCRIPTION 2 I C/USI SCL0 / SFRM / TIMER0 / GPIO [11] SDA0 / SSPTXD / TIMER1 / GPIO [12] SCL1 / SCLK / GPIO [13] / KPROW [3] SDA1 / SSPRXD / GPIO [14] / KPROW [2] 2 IOU I C Serial Clock Line 0. USI Serial Frame. Timer0 time out output. General Purpose In/Out port [11].
W90N745CD/W90N745CDG Table 5.1 W90N745 Pins Description, continued PIN NAME IO TYPE DESCRIPTION Power/Ground VDD18 P Core Logic power (1.8V) VSS18 G Core Logic ground (0V) VDD33 P IO Buffer power (3.3V) VSS33 G IO Buffer ground (0V) USBVDD P USB power (3.3V) USBVSS G USB ground (0V) DVDD18 P PLL Digital power (1.8V) DVSS18 G PLL Digital ground (0V) AVDD18 P PLL Analog power (1.
W90N745CD/W90N745CDG Table 5.2 W90N745 128-pin LQFP Multi-function List PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 USB1.
W90N745CD/W90N745CDG Table 5.
W90N745CD/W90N745CDG Table 5.2 W90N745 128-pin LQFP Multi-function List, continued PIN NO.
W90N745CD/W90N745CDG Table 5.2 W90N745 128-pin LQFP Multi-function List, continued PIN NO.
W90N745CD/W90N745CDG Table 5.2 W90N745 128-pin LQFP Multi-function List, continued PIN NO.
W90N745CD/W90N745CDG Table 5.2 W90N745 128-pin LQFP Multi-function List, continued PIN NO.
W90N745CD/W90N745CDG 6. FUNCTIONAL DESCRIPTION 6.1 ARM7TDMI CPU CORE The ARM7TDMI CPU core is a member of the Advanced RISC Machines (ARM) family of generalpurpose 32-bit microprocessors, which offer high performance for very low power consumption. The architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set Computers.
W90N745CD/W90N745CDG 6.2 6.2.1 System Manager Overview The W90N745 system manager has the following functions. 6.2.2 y System memory map y Data bus connection with external memory y Product identifier register y Bus arbitration y PLL module y Clock select and power saving control register y Power-On setting System Memory Map W90N745 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable.
W90N745CD/W90N745CDG 0x7FFF_FFFF 512KB (Fixed) 0x7FF8.
W90N745CD/W90N745CDG Table 6.2.
W90N745CD/W90N745CDG 6.2.3 Address Bus Generation The W90N745 address bus generation is depended on the required data bus width of each memory bank. The data bus width is determined by DBWD bits in each bank’s control register. The maximum accessible memory size of each external IO bank is 4M bytes. Table 6.2.2 Address Bus Generation Guidelines DATA BUS EXTERNAL ADDRESS PINS WIDTH A [20:0] 8-bit 16-bit 6.2.
W90N745CD/W90N745CDG Big endian In Big endian format, the W90N745 stores the most significant byte of a word at the lowest numbered byte, and the least significant byte at the highest-numbered byte. So the byte at address 0 of the memory system connects to data lines 31 through 24. For a word aligned address A, Figure 6.2.3 shows how the half-word at addresses A and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when the D14 pin is Low.
W90N745CD/W90N745CDG Figure 6.2.5 CPU registers Read/Write with external memory Table 6.2.3 and Table 6.2.4 Using big-endian and word access, Program/Data path between register and external memory WA = Address whose LSB is 0,4,8,C X = Don’t care nWBE [1-0] / SDQM [1-0] = A means active and U means inactive Table 6.2.
W90N745CD/W90N745CDG Table 6.2.4 Word access read operation with Big Endian ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY) XD WIDTH HALF WORD BYTE Bit Number CPU Reg Data 31 0 CDAB 31 0 DCBA SA WA WA Bit Number SD Bit Number ED 31 0 CD AB 31 0 31 0 CD XX CD AB 31 0 D C B A 31 0 31 0 D C X X D C B X 31 0 D X X X 31 0 D C B A XA WA WA+2 WA WA+1 WA+2 WA+3 SDQM [1-0] AA AA XA XA XA XA Bit Number XD Bit Number Ext.
W90N745CD/W90N745CDG Table 6.2.6 Half-word access read operation with Big Endian ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY) XD WIDTH HALF WORD BYTE Bit Number CPU Reg Data 15 0 CD 15 0 DC SA HA HA Bit Number SD Bit Number ED 15 0 CD 15 0 CD 15 0 DC 15 0 DX 15 0 DC XA HA HA HA+1 SDQM [1-0] AA XA XA Bit Number XD Bit Number Ext. Mem Data 15 0 CD 15 0 CD 7 0 D 7 0 D 7 0 C 7 0 C 1st read 2nd read Timing Sequence Table 6.2.7 and Table 6.2.
W90N745CD/W90N745CDG Table 6.2.7 Byte access write operation with Big Endian ACCESS OPERATION WRITE OPERATION (CPU REGISTER EXTERNAL MEMORY) XD WIDTH HALF WORD BYTE Bit Number CPU Reg Data 31 0 ABCD 31 0 ABCD SA BAL BAU BA Bit Number SD Bit Number ED 31 0 D D D D 15 8 D 31 0 D D D D 7 0 D 31 0 D D D D 7 0 D XA BAL BAL BA AU UA XA 15 0 DX 15 8 D 15 0 XD 7 0 D 7 0 D 7 0 D nWBE [1-0] / SDQM [1-0] Bit Number XD Bit Number Ext. Mem Data Timing Sequence Table 6.2.
W90N745CD/W90N745CDG Table 6.2.9 and Table 6.2.10 Using little-endian and word access, Program/Data path between register and external memory WA = Address whose LSB is 0,4,8,C X = Don’t care nWBE [1-0] / SDQM [1-0] = A means active and U means inactive Table 6.2.
W90N745CD/W90N745CDG Table 6.2.11 and Table 6.2.12 Using little-endian and half-word access, Program/Data path between register and external memory. HA = Address whose LSB is 0,2,4,6,8,A,C,E X = Don’t care nWBE [1-0] / SDQM [1-0] = A means active and U means inactive Table 6.2.
W90N745CD/W90N745CDG Table 6.2.13 and Table 6.2.14 Using little-endian and byte access, Program/Data path between register and external memory. BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F BAL = Address whose LSB is 0,2,4,6,8,A,C,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F Table 6.2.
W90N745CD/W90N745CDG 6.2.5 Bus Arbitration The W90N745’s internal function blocks or external devices can request mastership of the system bus and then hold the system bus in order to perform data transfers. Because the design of W90N745 bus allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal units or external devices simultaneously request bus mastership.
W90N745CD/W90N745CDG 6.2.5.2. Rotate Priority Mode In Rotate Priority Mode (PRTMOD=1), the IPEN and IPACT bits have no function (i.e. can be ignored). W90N745 uses a round robin arbitration scheme ensures that all bus masters have equal chance to gain the bus and that a retracted master does not lock up the bus. 6.2.6 Power Management W90N745 provide three power management scenarios to reduce power consumption.
W90N745CD/W90N745CDG IDLE MODE If the IDLE bit in Power Management Control Register (PMCON) is set, the ARM CORE clock source will be halted, the ARM CORE will not go forward. The AHB or APB clocks still active except the clock to cache controller and ARM are stopped. W90N745 will exit idle state when nIRQ or nFIQ from any peripheral is revived; like keypad, timer overflow interrupts and so on. The memory controller can also be forced to enter idle state if both MIDLE and IDLE bits are set.
W90N745CD/W90N745CDG Power Down Mode This mode provides the minimum power consumption. When the W90N745 system is not working or waiting an external event, software can write PD bit “1” to turn off all the clocks includes system crystal oscillator to let ARM CORE enter sleep mode. In this state, all peripherals are also in sleep mode since the clock source is stopped. W90N745 will exit power down state when nIRQ/nFIQ is detected.
W90N745CD/W90N745CDG 6.2.7 Power-On Setting After power on reset, there are eight Power-On setting pins to configure W90N745 system configuration. POWER-ON SETTING PIN Internal System Clock Select Little/Big Endian Mode Select Boot ROM/FLASH Data Bus Width D15 D14 D [13:12] Default: Pull-Down in Normal Operation D9 Default: Pull-Up in Normal Operation D8 D15 pin：Internal System Clock Select If pin D15 is pull-down, the external clock from EXTAL pin is served as internal system clock.
W90N745CD/W90N745CDG Product Identifier Register （PDID） This register is read only and lets software can use it to recognize certain characteristics of the chip ID and the version number.
W90N745CD/W90N745CDG Arbitration Control Register (ARBCON) REGISTER ADDRESS R/W DESCRIPTION ARBCON 0xFFF0_0004 R/W Arbitration Control Register 31 30 29 28 23 22 21 20 27 RESET VALUE 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 IPACT IPEN PRTMOD RESERVED 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 RESERVED BITS DESCRIPTION [31:3] RESERVED [2] IPACT [1] IPEN [0] PRTMOD Interrupt priority active.
W90N745CD/W90N745CDG PLL Control Register0 （PLLCON0） W90N745 provides two clock generation options – crystal and oscillator. The external clock via EXTAL(15M) Minput pin as the reference clock input of PLL module. The external clock can bypass the PLL and be used to the internal system clock by pull-down the data D15 pin. Using PLL’s output clock for the internal system clock, D15 pin must be pull-up.
W90N745CD/W90N745CDG EXTAL USBCKS FIN INDV[4:0] GP0 Charge Pump PFD FBDV[8:0] PLL Input Divider (NR) VCO 48MHz Gen Output 480MHz Divider FOUT (NO) Feedback Divider (NF) Clock Divider & Selector 1 0 0 1 USB Module Internal System Clock ECLKS OTDV[1:0] CLKS[2:0] Figure 6.2.
W90N745CD/W90N745CDG Clock Select Register (CLKSEL) REGISTER ADDRESS R/W CLKSEL 0xFFF0_000C R/W 31 30 DESCRIPTION RESET VALUE Clock Select Register 0x1FFF_7FX8 29 28 27 26 23 RESERVED 22 21 PS2 20 KPI 19 RESERVED 18 17 UART3 15 UART2 14 UART1 13 I2C1 12 I2C0 11 USBCKS 7 USBD 6 GDMA 5 USBH TIMER UART BITS [31:29] PS2 AC97 8 EMC 2 RESERVED 1 WDT 0 RESERVED 4 3 ECLKS CLKS 0 = Disable PS2 controller clock 1 = Enable PS2 controller clock Keypad controller clock enable bi
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG PLL Control Register 1（PLLCON1） W90N745 provides extra PLL to provide 12.288/16.934 MHz clock source to Audio Controller. It uses the same 15MHz crystal clock input source with system PLL mentioned above.
W90N745CD/W90N745CDG EXTAL FIN INDV1[4:0] PFD FBDV1[8:0] PLL1 Input Divider (NR) Charge Pump VCO Output 480MHz Divider FOUT (NO) to Audio Controller Feedback Divider (NF) OTDV1[1:0] Figure 6.2.
W90N745CD/W90N745CDG I²S Clock Control Register (I²SCKCON) REGISTER ADDRESS R/W I²SCKCON 0xFFF0_0014 R/W 31 30 29 23 22 21 15 14 13 7 6 5 RESET VALUE I²S PLL clock Control Register 28 27 RESERVED 20 19 RESERVED 12 11 RESERVED 4 3 PRESCALE BITS [31:9] DESCRIPTION 0x0000_0000 26 25 24 18 17 16 10 9 2 1 8 I²SPLLEN 0 DESCRIPTION RESERVED I²S PLL clock source enable [8] I²SPLLEN Set this bit will enable PLL1 clock output to audio I²S clock input.
W90N745CD/W90N745CDG IRQ Wakeup Control Register (IRQWAKECON) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE IRQWAKECON 0xFFF0_0020 R/W IRQ Wakeup Control Register 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESERVED 23 22 21 20 RESERVED 15 14 13 12 RESERVED 7 6 RESERVED 5 RESERVED IRQWAKEUPPOL BITS [31:6] 4 DESCRIPTION RESERVED nIRQ1 wake up polarity [5] IRQWAKEUPPOL[1] 1 = nIRQ1 is high level wake up 0 = nIRQ1 is low level wake up nIRQ0
W90N745CD/W90N745CDG IRQ Wakeup Flag Register (IRQWAKEFLAG) REGISTER ADDRESS IRQWAKEFLAG 0xFFF0_0024 31 30 29 R/W DESCRIPTION RESET VALUE R/W IRQ Wakeup Flag Register 0x0000_0000 28 27 26 25 24 18 17 16 10 9 8 2 1 0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 RESERVED IRQWAKEFLAG This register is used to record the wakeup event, after clock recovery, software should check these flags to identify which nIRQ is used to wakeup the system.
W90N745CD/W90N745CDG Power Management Control Register (PMCON) REGISTER ADDRESS R/W PMCON 0xFFF0_0028 R/W 31 30 29 23 22 21 15 14 13 7 6 5 RESERVED DESCRIPTION Power Management Control Register 28 27 RESERVED 20 19 RESERVED 12 11 RESERVED 4 3 BITS [31:3] RESET VALUE 0x0000_0000 26 25 24 18 17 16 10 9 8 2 MIDLE 1 PD 0 IDLE DESCRIPTION RESERVED Memory controller IDLE enable Setting both MIDLE and IDLE bits HIGH will let memory controller enter IDLE mode, the clock source o
W90N745CD/W90N745CDG USB Transceiver Control Register (USBTXRCON) REGISTER ADDRESS R/W USBTXRCON 0xFFF0_0030 31 30 DESCRIPTION USB Transceiver Control Register R/W 29 RESET VALUE 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 RESERVED BITS [31:1] USBHnD DESCRIPTION RESERVED USBHnD[0]: USB transceiver control [0] USBHnD There are two USB1.1 built-in transceivers for data transmission.
W90N745CD/W90N745CDG 6.3 6.3.1 External Bus Interface EBI Overview W90N745 supports External Bus Interface (EBI), which controls the access to the external memory (ROM/FLASH, SDRAM) and External I/O devices. The EBI has seven chip selects to select one ROM/FLASH bank, two SDRAM banks, and four External I/O banks.The address bus is 21 bits. It supports 8-bit, 16-bit external data bus width for each bank. The EBI has the following functions： 6.3.
W90N745CD/W90N745CDG 6.3.2.1. SDRAM Components Supported Table 6.3.
W90N745CD/W90N745CDG SDRAM Data Bus Width: 16-bit A14 Total Type RxC R/C 16M 2Mx8 11x9 R ** C A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 10 ** 10* 21 20 19 18 17 16 15 14 13 12 11 ** 10 ** 10* AP 24* 9 8 7 6 5 4 3 2 1 ** 9 ** 9* 10 20 19 18 17 16 15 14 13 12 11 (BS1) (BS0) 16M 1Mx16 11x8 R C ** 9 ** 9* AP 24* 9* 8 7 6 5 4 3 2 1 64M 8Mx8 12x9 R 10 11 10* 22 21 20 19 18 17 16 15 14 13 12 23 C 10 11
W90N745CD/W90N745CDG 6.3.2.2. SDRAM Power Up Sequence The SDRAM must be initialized predefined manner after power on.W90N745 SDRAM Controller automatically executes the commands needed for initialion and set the mode register of each bank to default value.
W90N745CD/W90N745CDG 6.3.
W90N745CD/W90N745CDG EBI Control Register (EBICON) REGISTER ADDRESS EBICON 0xFFF0_1000 31 30 R/W DESCRIPTION R/W EBI control register 29 28 RESERVED 23 22 21 14 13 0x0001_0000 27 26 25 24 EXBE3 EXBE2 EXBE1 EXBE0 19 18 17 16 REFEN REFMOD CLKEN 11 10 9 8 3 2 1 0 20 RESERVED 15 RESET VALUE 12 REFRAT 7 6 5 4 REFRAT BITS [31:27] WAITVT LITTLE DESCRIPTION RESERVED External IO bank 3 byte enable [27] EXBE3 This function is used for some devices that with hig
W90N745CD/W90N745CDG Continued. BITS DESCRIPTION External IO bank 0 byte enable This bit function description is the same as EXBE3 above. [24] EXBE0 1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write strobe signal to SRAM 0 = nWBE[1:0] pin is byte write strobe signal [23:19] RESERVED Enable SDRAM refresh cycle for SDRAM bank0 & bank1 [18] REFEN This bit set will start the auto-refresh cycle to SDRAM. The refresh rate is according to REFRAT bits.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTION Valid time of nWAIT signal W90N745 recognizes the nWAIT signal at the next “nth” MCLK rising edge after the nOE or nWBE active cycle. WAITVT bits determine the n. [2:1] WAITVT WAITVT [2:1] 0 0 1 1 0 1 0 1 nth MCLK 1 2 3 4 Little Endian mode [0] LITTLE After power on reset, the content of LITTLE is the Power-On Setting value from D14 pin. If pin D14 is pull-down, the external memory format is Big Endian mode.
W90N745CD/W90N745CDG ROM/Flash Control Register （ROMCON） REGISTER ADDRESS ROMCON 0xFFF0_1004 31 R/W 30 DESCRIPTION RESET VALUE R/W ROM/FLASH control register 0x0000_0XFC 29 28 27 26 25 24 18 17 16 BASADDR 23 22 21 20 19 BASADDR 15 14 SIZE 13 12 11 10 RESERVED 7 6 9 8 1 0 tPA 5 4 3 tACC 2 BTSIZE BITS PGMODE DESCRIPTION Base address pointer of ROM/Flash bank [31:19] BASADDR The start address is calculated as ROM/Flash bank base pointer << 18.
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG Figure 6.3.2 ROM/FLASH Read Operation Timing Figure 6.3.
W90N745CD/W90N745CDG Configuration Registers（SDCONF0/1） The configuration registers enable software to set a number of operating parameters for the SDRAM controller. There are two configuration registers SDCONF0、SDCONF1 for SDRAM bank 0、bank 1 respectively. Each bank can have a different configuration.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTION [10:8] RESERVED [7] COMPBK [6:5] DBWD Number of component bank in SDRAM bank 0/1 Indicates the number of component bank (2 or 4 banks) in external SDRAM bank 0/1. 0 = 2 banks 1 = 4 banks Data bus width for SDRAM bank 0/1 Indicates the external data bus width connect with SDRAM bank 0/1 If DBWD = 00, the assigned SDRAM access signal is not generated i.e. disable.
W90N745CD/W90N745CDG Timing Control Registers （SDTIME0/1） W90N745 offers the flexible timing control registers to control the generation and processing of the control signals and can achieve you use different speed of SDRAM REGISTER ADDRESS SDTIME0 0xFFF0_1010 R/W SDRAM bank 0 timing control register 0x0000_0000 SDTIME1 0xFFF0_1014 R/W SDRAM bank 1 timing control register 0x0000_0000 31 30 R/W 29 DESCRIPTION 28 27 RESET VALUE 26 25 24 18 17 16 10 9 8 RESERVED 23 22 21 20 19 R
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG Figure 6.3.4 Access timing 1 of SDRAM Figure 6.3.
W90N745CD/W90N745CDG External I/O Control Registers（EXT0CON – EXT3CON） The W90N745 supports an external device control without glue logic. It is very cost effective because address decoding and control signals timing logic are not needed. Using these control registers you can configure special external I/O devices for providing the low cost external devices control solution.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTION Address bus alignment for external I/O bank 0~3 [15] ADRS When ADRS is set, external address (A20~A0) bus is alignment to byte address format, that is, A0 is internal AHB address bus HADDR[0] and A1 is AHB bus HADDR[1] and so forth. And it ignores DBWD [1:0] setting. Access cycles of external I/O bank 0~3 This parameter means nWE, nWBE and nOE active time clock. Detail timing diagram please refer to Figure 6.3.6 and 6.3.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTION Address set-up before nECS for external I/O bank 0~3 [7:5] tACS 0 0 0 0 1 1 1 1 tACS [7:5] 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MCLK 0 1 2 3 4 5 6 7 Chip selection set-up time of external I/O bank 0~3 When ROM/Flash memory bank is configured, the access to its bank stretches chip selection time before the nOE or new signal is activated.
W90N745CD/W90N745CDG Figure 6.3.6 External I/O write operation timing Figure 6.3.
W90N745CD/W90N745CDG Figure 6.3.
W90N745CD/W90N745CDG BITS DESCRIPTION Latch DLH_CLK clock tree by HCLK positive edge [31:16] DLH_CLK_REF [15:9] RESERVED The SDRAM MCLK is generated by inserting a delay (XOR2) chain in HCLK positive or negedge edge to adjust the MCLK skew. So software can read these bits to expore MCLK and HCLK relationship. [31:24] is used for positive edge and [23:16] is for negedge edge.
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG 6.4 Cache Controller The W90N745 incorporates a 4KB Instruction cache, 4KB Data cache and 8 words write buffer. The ICache and D-Cache have similar organization except the cache size. To raise the cache-hit ratio, these two caches are configured two-way set associative addressing. Each cache has four words cache line size. When a miss occurs, four words must be fetched consecutively from external memory. The replacement algorithm is a LRU (Least Recently Used).
W90N745CD/W90N745CDG 6.4.3 Instruction Cache The Instruction cache (I-cache) is a 4K bytes two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache access cycle begins with an instruction request from the instruction unit in the core. In the case of a cache hit, the instruction is delivered to the instruction unit.
W90N745CD/W90N745CDG Instruction Cache Load and Lock The W90N745 supports a cache-locking feature that can be used to lock critical sections of code into ICache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular instruction SRAM. Lines locked are not replaced during misses and not affected by flush per line command.
W90N745CD/W90N745CDG 6.4.4 Data Cache The W90N745 data cache (D-Cache) is a 4KB two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache is designed for buffer write-through mode of operation and a least recently used (LRU) replacement algorithm is used to select a line when no empty lines are available. When D-Cache is disabled, the cache memory is served as 4KB On-chip RAM.
W90N745CD/W90N745CDG Write Hit：Data is written into both the cache and write buffer. The processor then continues to access the cache, while the cache controller simultaneously downloads the contents of the write buffer to main memory. This reduces the effective write memory cycle time from the time required for a main memory cycle to the cycle time of the high-speed cache. Write Miss：Data is only written into write buffer, not to the cache (write no allocate).
W90N745CD/W90N745CDG The unlock all operation is used to unlock the whole D-Cache. This operation is performed on all cache lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA and DCAH bits. 6.4.5 Write Buffer The W90N745 provides a write buffer to improve system performance. The write buffer can buffer up to eight words of data.
W90N745CD/W90N745CDG Configuration Register (CAHCNF) Cache controller has a configuration register to enable or disable the I-Cache, D-Cache, and Write buffer.
W90N745CD/W90N745CDG Control Register (CAHCON) Cache controller supports one Control register used to control the following operations. y Flush I-Cache and D-Cache y Load and lock I-Cache and D-Cache y Unlock I-Cache and D-Cache y Drain write buffer These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command set bit will be cleared to “0” automatically.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTION Flush I-Cache/D-Cache single line [3] FLHS Flushes the entire I-Cache/D-Cache per line. Both WAY and ADDR bits in CAHADR register must be specified. Flush I-Cache/D-Cache entirely [2] FLHA [1] DCAH [0] ICAH To flush the entire I-Cache/D-Cache, also flushes any locked-down code. If the I-Cache/D-Cache contains locked down code, the programmer must flush lines individually D-Cache selected When set to “1”, the command set is executed with D-Cache.
W90N745CD/W90N745CDG Address Register (CAHADR) W90N745 Cache Controller supports one address register. This address register is used with the command set in the control register (CAHCON) by specifying instruction/data address.
W90N745CD/W90N745CDG Cache Test Register 0 (CTEST0) Cache test control register that configures the cache and tag ram testing enable or disable. In addition, this register controls the built-in-self-test (BIST) function of SRAM.
W90N745CD/W90N745CDG Cache Test Register 1 (CTEST1) Cache Test Register that will be read back to provide the status of cache RAM BIST. Whether the BIST is finish and all of bank of SRAM are tested successfully will be presented in this register.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTION BIST test fail for data cache ram way 0 [2] BFAIL2 If this bit equals to “1”, it indicates the data cache ram for way 0 is tested fail by BIST. “0” means the test is passed. BIST test fail for instruction cache ram way 1 [1] BFAIL1 [0] BFAIL0 If this bit equals to “1”, it indicates the instruction cache ram for way 1 is tested fail by BIST. “0” means the test is passed.
W90N745CD/W90N745CDG 6.5 Ethernet MAC Controller Overview The W90N745 provides an Ethernet MAC Controller (EMC) for LAN application. This EMC has its DMA controller, transmit FIFO, and receive FIFO. The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM function for Ethernet MAC address recognition, Transmit-FIFO, Receive-FIFO, TX/RX state machine controller and status controller.
W90N745CD/W90N745CDG 6.5.1 EMC Functional Description MII Management State Machine The MII management function of EMC is compliant to IEEE 802.3 Std. Through the MII management interface, software can access the control and status registers of the external PHY chip. Tow programmable register MIID (MAC MII Management Data Register) and MIIDA (MAC MII Management Data Control and Address Register) are for MII management function.
W90N745CD/W90N745CDG EMC Descriptors A link-list data structure named as descriptor is used to keep the control, status and data information of each frame. Through the descriptor, CPU and EMC exchange the information for frame reception and transmission. Two different descriptors are defined in W90N745. One named as Rx descriptor for frame reception and the other names as Tx descriptor for frame transmission. Each Rx descriptor consists of four words.
W90N745CD/W90N745CDG If the O=2’b00 indicates the CPU is the owner of Rx descriptor. After the CPU completes processing the frame, it modifies the ownership field to 2’b10 and releases the Rx descriptor to EMC RxDMA. Rx Status [29:16]: Receive Status This field keeps the status for frame reception. All status bits are updated by EMC. In the receive status, bits 29 to 23 are undefined and reserved for the future.
W90N745CD/W90N745CDG RXINTR [16]: Receive Interrupt The RXINTR indicates the frame stored in the data buffer pointed by Rx descriptor caused an interrupt condition. 1’b0: The frame doesn’t cause an interrupt. 1’b1: The frame caused an interrupt. RBC [15:0]: Receive Byte Count The RBC indicates the byte count of the frame stored in the data buffer pointed by Rx descriptor. The four bytes CRC field is also included in the receive byte count.
W90N745CD/W90N745CDG Rx Descriptor Word 2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved The Rx descriptor word 2 keeps obsolete information for MAC translation. Therefore, these information bits are undefined and should be ignored.
W90N745CD/W90N745CDG 6.5.1.2.
W90N745CD/W90N745CDG CRCApp [1]: CRC Append The CRCApp control the CRC append during frame transmission. If CRCApp is enabled, the 4-bytes CRC checksum will be appended to frame at the end of frame transmission. 1’b0: 4-bytes CRC appending is disabled. 1’b1: 4-bytes CRC appending is enabled. PadEN [0]: Padding Enable The PadEN control the PAD bits appending while the length of transmission frame is less than 60 bytes. If PadEN is enabled, EMC does the padding automatically.
W90N745CD/W90N745CDG Tx Descriptor Word 2 31 30 29 28 CCNT 27 26 25 24 Reserved SQE PAU TXHA 23 22 21 20 19 18 17 16 LC TXABT NCS EXDEF TXCP Reserved DEF TXINTR 15 14 13 12 11 10 9 8 3 2 1 0 TBC 7 6 5 4 TBC CCNT [31:28]: Collision Count The CCNT indicates the how many collision occurred consecutively during a packet transmission. If the packet incurred 16 consecutive collisions during transmission, the CCNT will be 4’h0 and bit TXABT will be set to 1.
W90N745CD/W90N745CDG LC [23]: Late Collision The LC indicates the collision occurred in the outside of 64 bytes collision window. This means after the 64 bytes of a frame has transmitted out to the network, the collision still occurred. The late collision check will only be done while EMC is operating on half-duplex mode. 1’b0: No collision occurred in the outside of 64 bytes collision window. 1’b1: Collision occurred in the outside of 64 bytes collision window.
W90N745CD/W90N745CDG TXINTR [16]: Transmit Interrupt The TXINTR indicates the packet transmission caused an interrupt condition. 1’b0: The packet transmission doesn’t cause an interrupt. 1’b1: The packet transmission caused an interrupt. TBC [15:0]: Transmit Byte Count The TBC indicates the byte count of the frame stored in the data buffer pointed by Tx descriptor for transmission.
W90N745CD/W90N745CDG 6.5.2 EMC Register Mapping The EMC implements many registers and the registers are separated into three types, the control registers, the status registers and diagnostic registers. The control registers are used by S/W to pass control information to EMC. The status registers are used to keep EMC operation status for S/W. And, the diagnostic registers are used for debug only.
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG 6.5.2.1. Register Details CAM Command Register (CAMCMR) The EMC of W90N745 supports CAM function for destination MAC address recognition. The CAMCMR control the CAM comparison function, and unicast, multicast, and broadcast packet reception.
W90N745CD/W90N745CDG Continued. BITS [2] DESCRIPTIONS ABP The Accept Broadcast Packet controls the broadcast packet reception. If ABP is enabled, EMC receives all incoming packet it’s destination MAC address is a broadcast address. 1’b0: EMC receives packet depends on the CAM comparison result. 1’b1: EMC receives all broadcast packets. [1] AMP The Accept Multicast Packet controls the multicast packet reception.
W90N745CD/W90N745CDG ECMP CCAM AUP AMP ABP RESULT 0 0 0 0 0 No Packet 0 0 0 0 1 B 0 0 0 1 0 M 0 0 0 1 1 M B 0 0 1 0 0 C U 0 0 1 0 1 C U B 0 0 1 1 0 C U M 0 0 1 1 1 C U M B 0 1 0 0 0 C U M B 0 1 0 0 1 C U M B 0 1 0 1 0 C U M B 0 1 0 1 1 C U M B 0 1 1 0 0 C U M B 0 1 1 0 1 C U M B 0 1 1 1 0 C U M B 0 1 1 1 1 C U M B 1 0 0 0 0 C 1 0 0 0 1 C B 1 0 0 1 0 C M
W90N745CD/W90N745CDG CAM Enable Register (CAMEN) The CAMEN controls the validation of each CAM entry. Each CAM entry must be enabled first before it can participate in the destination MAC address recognition.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTIONS CAM entry 9 is enabled [9] CAM9EN 1’b0: CAM entry 9 disabled. 1’b1: CAM entry 9 enabled. CAM entry 8 is enabled [8] CAM8EN 1’b0: CAM entry 8 disabled. 1’b1: CAM entry 8 enabled. CAM entry 7 is enabled [7] CAM7EN 1’b0: CAM entry 7 disabled. 1’b1: CAM entry 7 enabled. CAM entry 6 is enabled [6] CAM6EN 1’b0: CAM entry 6 disabled. 1’b1: CAM entry 6 enabled. CAM entry 5 is enabled [5] CAM5EN 1’b0: CAM entry 5 disabled. 1’b1: CAM entry 5 enabled.
W90N745CD/W90N745CDG CAM Entry Registers (CAMxx) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM0M CAM0L 0xFFF0_3008 0xFFF0_300C R/W R/W CAM0 Most Significant Word Register CAM0 Least Significant Word Register 0x0000_0000 0x0000_0000 CAM1M 0xFFF0_3010 R/W CAM1 Most Significant Word Register 0x0000_0000 CAM1L 0xFFF0_3014 R/W CAM1 Least Significant Word Register 0x0000_0000 CAM2M 0xFFF0_3018 R/W CAM2 Most Significant Word Register 0x0000_0000 CAM2L 0xFFF0_301C R/W CAM2 Least Signi
W90N745CD/W90N745CDG CAMxM 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 MAC Address Byte 5 (MSB) 23 22 21 20 19 MAC Address Byte 4 15 14 13 12 11 MAC Address Byte 3 7 6 5 4 3 MAC Address Byte 2 BITS [31:0] DESCRIPTIONS CAMxM The CAMxM(CAMx Most Significant Word) keeps the bit 47~16 of MAC address. The x can be the 0~14. The register pair {CAMxM, CAMxL} represents a CAM entry and can keep a MAC address.
W90N745CD/W90N745CDG CAMxL 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 MAC Address Byte 1 23 22 21 20 19 MAC Address Byte 0 (LSB) 15 14 13 12 11 Reserved 7 6 5 4 3 Reserved BITS DESCRIPTIONS [31:16] CAMxL The CAMxL(CAMx Least Significant Word) keeps the bit 15~0 of MAC address. The x can be the 0~14. The register pair {CAMxM, CAMxL} represents a CAM entry and can keep a MAC address.
W90N745CD/W90N745CDG BITS DESCRIPTIONS Length/Type Field of PAUSE Control Frame [31:0] Length/Type In the PAUSE control frame, a length/type field is defined and will be 16’h8808. OP Code Field of PAUSE Control Frame [15:0] OP-Code In the PAUSE control frame, an op code field is defined and will be 16’h0001.
W90N745CD/W90N745CDG Transmit Descriptor Link List Start Address Register (TXDLSA) The Tx descriptor defined in EMC is a link-list data structure. The TXDLSA keeps the starting address of this link-list. In other words, the TXDLSA keeps the starting address of the 1st Tx descriptor. S/W must configure TXDLSA before enable bit TXON of MCMDR register.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 RXDLSA 23 22 21 20 19 RXDLSA 15 14 13 12 11 RXDLSA 7 6 5 4 3 RXDLSA BITS [31:0] DESCRIPTIONS The RXDLSA(Receive Descriptor Link-List Start Address) keeps the start address of receive descriptor link-list. If the S/W enables the bit RXON of MCMDR register, the content of RXDLSA will be loaded into the current receive descriptor start address register (CRXDSA). The RXDLSA doesn’t be updated by EMC.
W90N745CD/W90N745CDG BITS [31:25] [24] DESCRIPTIONS Reserved SWR The SWR (Software Reset) implements a reset function to make the EMC return default state. The SWR is a self-clear bit. This means after the software reset finished, the SWR will be cleared automatically. Enable SWR can also reset all control and status registers, except for OPMOD bit of MCMDR register. The EMC re-initial is needed after the software reset completed. 1’b0: Software reset completed. 1’b1: Enable software reset.
W90N745CD/W90N745CDG Continued. BITS [17] DESCRIPTIONS EnSQE The Enable SQE Checking controls the enable of SQE checking. The SQE checking is only available while EMC is operating on 10M bps and half duplex mode. In other words, the EnSQE cannot affect EMC operation, if the EMC is operating on 100M bps or full duplex mode. 1’b0: Disable SQE checking while EMC is operating on 10Mbps and half duplex mode. 1’b1: Enable SQE checking while EMC is operating on 10Mbps and half duplex mode.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTIONS The Frame Transmission ON controls the normal packet transmission of EMC. If the TXON is set to high, the EMC starts the packet transmission process, including the Tx descriptor fetching, packet transmission and Tx descriptor modification. [8] TXON It is must to finish EMC initial sequence before enable TXON. Otherwise, the EMC operation is undefined.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTIONS The Accept Runt Packet controls the runt packet, which length is less than 64 bytes, reception. If the ARP is set to high, the EMC will accept the runt packet. [2] ARP Otherwise, the runt packet will be dropped. 1’b0: The runt packet will be dropped by EMC. 1’b1: The runt packet will be accepted by EMC. The Accept Long Packet controls the long packet, which packet length is greater than 1518 bytes, reception.
W90N745CD/W90N745CDG MII Management Data Register (MIID) The EMC provides MII management function to access the control and status registers of the external PHY. The MIID register is used to store the data that will be written into the registers of external PHY for write command or the data that is read from the registers of external PHY for read command.
W90N745CD/W90N745CDG MII Management Control and Address Register (MIIDA) The EMC provides MII management function to access the control and status registers of the external PHY. The MIIDA register is used to keep the MII management command information, like the register address, external PHY address, MDC clocking rate, read/write etc.
W90N745CD/W90N745CDG Continued. BITS [18] DESCRIPTIONS PreSP The Preamble Suppress controls the preamble field generation of MII management frame. If the PreSP is set to high, the preamble field generation of MII management frame is skipped. 1’b0: Preamble field generation of MII management frame is not skipped. 1’b1: Preamble field generation of MII management frame is skipped. The Busy Bit controls the enable of the MII management frame generation.
W90N745CD/W90N745CDG MDCCR [23:20] MDC CLOCK PERIOD MDC CLOCK FREQUENCY 4’b0000 4 x THCLK HCLK/4 4’b0001 6 x THCLK HCLK/6 4’b0010 8 x THCLK HCLK/8 4’b0011 12 x THCLK HCLK/12 4’b0100 16 x THCLK HCLK/16 4’b0101 20 x THCLK HCLK/20 4’b0110 24 x THCLK HCLK/24 4’b0111 28 x THCLK HCLK/28 4’b1000 30 x THCLK HCLK/30 4’b1001 32 x THCLK HCLK/32 4’b1010 36 x THCLK HCLK/36 4’b1011 40 x THCLK HCLK/40 4’b1100 44 x THCLK HCLK/44 4’b1101 48 x THCLK HCLK/48 4’b1110 54 x THCLK H
W90N745CD/W90N745CDG MII Management Function Frame Format In IEEE Std. 802.3 clause 22.2.4, the MII management function is defined. The MII management function is used for the purpose of controlling the PHY and gathering status from the PHY. The MII management frame format is shown as follow.
W90N745CD/W90N745CDG FIFO Threshold Control Register (FFTCR) The FFTCR defines the high and low threshold of internal FIFOs, including TxFIFO and RxFIFO. The threshold of internal FIFOs is related to EMC request generation and when the frame transmission starts. The FFTCR also defines the burst length of AHB bus cycle for system memory access.
W90N745CD/W90N745CDG Continued. BITS [9:8] DESCRIPTIONS TxTHD The TxFIFO Low Threshold controls when TxDMA requests internal arbiter for data transfer between system memory and TxFIFO. The TxTHD defines not only the low threshold of TxFIFO, but also the high threshold. The high threshold is the twice of low threshold always. During the packet transmission, if the TxFIFO reaches the high threshold, the TxDMA stops generate request to transfer frame data from system memory to TxFIFO.
W90N745CD/W90N745CDG Transmit Start Demand Register (TSDR) If the Tx descriptor is not available for use of TxDMA after the TXON of MCMDR register is enabled, the FSM (Finite State Machine) of TxDMA enters the Halt state and the frame transmission is halted. After the S/W has prepared the new Tx descriptor for frame transmission, it must issue a write command to TSDR register to make TxDMA leave Halt state and contiguous frame transmission.
W90N745CD/W90N745CDG Maximum Receive Frame Control Register (DMARFC) The DMARFC defines the maximum frame length for a received frame that can be stored in the system memory. It is recommend that only use this register while S/W wants to receive a frame which length is greater than 1518 bytes.
W90N745CD/W90N745CDG MAC Interrupt Enable Register (MIEN) The MIEN controls the enable of EMC interrupt status to generate interrupt. Two interrupts, RXINTR for frame reception and TXINTR for frame transmission, are generated from EMC to CPU.
W90N745CD/W90N745CDG Continued BITS [22] DESCRIPTIONS EnLC The Enable Late Collision Interrupt controls the LC interrupt generation. If LC of MISTA register is set, and both EnLC and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnLC or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the LC of MISTA register is set. 1’b0: LC of MISTA register is masked from Tx interrupt generation. 1’b1: LC of MISTA register can participate in Tx interrupt generation.
W90N745CD/W90N745CDG Continued. BITS [17] DESCRIPTIONS EnTXEMP The Enable Transmit FIFO Underflow Interrupt controls the TXEMP interrupt generation. If TXEMP of MISTA register is set, and both EnTXEMP and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnTXEMP or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the TXEMP of MISTA register is set. 1’b0: TXEMP of MISTA register is masked from Tx interrupt generation.
W90N745CD/W90N745CDG Continued. BITS [10] DESCRIPTIONS EnRDU The Enable Receive Descriptor Unavailable Interrupt controls the RDU interrupt generation. If RDU of MISTA register is set, and both EnRDU and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnRDU or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the RDU of MISTA register is set. 1’b0: RDU of MISTA register is masked from Rx interrupt generation.
W90N745CD/W90N745CDG Continued. BITS [5] DESCRIPTIONS EnALIE The Enable Alignment Error Interrupt controls the ALIE interrupt generation. If ALIE of MISTA register is set, and both EnALIE and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnALIE or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the ALIE of MISTA register is set. 1’b0: ALIE of MISTA register is masked from Rx interrupt generation.
W90N745CD/W90N745CDG Continued. BITS [1] DESCRIPTIONS EnCRCE The Enable CRC Error Interrupt controls the CRCE interrupt generation. If CRCE of MISTA register is set, and both EnCRCE and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnCRCE or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the CRCE of MISTA register is set. 1’b0: CRCE of MISTA register is masked from Rx interrupt generation. 1’b1: CRCE of MISTA register can participate in Rx interrupt generation.
W90N745CD/W90N745CDG MAC Interrupt Status Register (MISTA) The MISTA keeps much EMC statuses, like frame transmission and reception status, internal FIFO status and also NATA processing status. The statuses kept in MISTA will trigger the reception or transmission interrupt. The MISTA is a write clear register and write 1 to corresponding bit clears the status and also clears the interrupt.
W90N745CD/W90N745CDG Continued. BITS [22] DESCRIPTIONS LC The Late Collision Interrupt high indicates the collision occurred in the outside of 64 bytes collision window. This means after the 64 bytes of a frame has transmitted out to the network, the collision still occurred. The late collision check will only be done while EMC is operating on half-duplex mode. If the LC is high and EnLC of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the LC status.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTIONS The Transmit Completion Interrupt indicates the packet transmission has completed correctly. [18] TXCP If the TXCP is high and EnTXCP of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TXCP status. 1’b0: The packet transmission doesn’t complete. 1’b1: The packet transmission has completed. [17] TXEMP The Transmit FIFO Underflow Interrupt high indicates the TxFIFO underflow occurred during packet transmission.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTIONS The Control Frame Receive Interrupt high indicates EMC receives a flow control frame. The CFR only available while EMC is operating on full duplex mode. [14] CFR If the CFR is high and EnCFR of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the CFR status. 1’b0: The EMC doesn’t receive the flow control frame. 1’b1: The EMC receives a flow control frame.
W90N745CD/W90N745CDG Continued. BITS [8] DESCRIPTIONS DFOI The Maximum Frame Length Interrupt high indicates the length of the incoming packet has exceeded the length limitation configured in DMARFC register and the incoming packet is dropped. If the DFOI is high and EnDFO of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the DFOI status. 1’b0: The length of the incoming packet doesn’t exceed the length limitation configured in DMARFC.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTIONS The Receive Good Interrupt high indicates the frame reception has completed. [4] RXGD If the RXGD is high and EnRXGD of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the RXGD status. 1’b0: The frame reception has not complete yet. 1’b1: The frame reception has completed. The Packet Too Long Interrupt high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTIONS The Receive Interrupt indicates the Rx interrupt status. If RXINTR high and its corresponding enable bit, EnRXINTR of MISTA register, is also high indicates the EMC generates Rx interrupt to CPU. If RXINTR is high but EnRXINTR of MISTA is disabled, no Rx interrupt is generated. [0] The RXINTR is logic OR result of the bits 1~14 in MISTA register do logic AND with the corresponding bits in MIEN register.
W90N745CD/W90N745CDG BITS [31:12] DESCRIPTIONS Reserved - TXHA The Transmission Halted high indicates the next normal packet transmission process will be halted because the bit TXON of MCMDR is disabled be S/W. 1’b0: Next normal packet transmission process will go on. 1’b1: Next normal packet transmission process will be halted. SQE The Signal Quality Error high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode.
W90N745CD/W90N745CDG Missed Packet Count Register (MPCNT) The MPCNT keeps the number of packets that were dropped due to various types of receive errors. The MPCNT is a read clear register. In addition, S/W also can write an initial value to MPCNT and the missed packet counter will start counting from that initial value. If the missed packet counter is overflow, the MMP of MISTA will be set.
W90N745CD/W90N745CDG MAC Receive Pause Count Register (MRPC) The EMC of W90N745 supports the PAUSE control frame reception and recognition. If EMC received a PAUSE control frame, the operand field of the PAUSE control frame will be extracted and stored in the MRPC register. The MRPC register will keep the same while Tx of EMC is pausing due to the PAUSE control frame is received. The MRPC is read only and write to this register has no effect.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 MRPCC 7 6 5 4 3 MRPCC BITS [31:16] [15:0] DESCRIPTIONS Reserved - MRPCC The MAC Receive Pause Current Count shows the current value of that down count timer.
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:16] Reserved [15:0] MREPC The MAC Remote Pause Count shows the current value of the down count timer that starts to count down from the value of operand of the transmitted PAUSE control frame. DMA Receive Frame Status Register (DMARFS) The DMARFS is used to keep the Length/Type field of each incoming Ethernet packet. This register is writing clear and writes 1 to corresponding bit clears the bit.
W90N745CD/W90N745CDG Current Transmit Descriptor Start Address Register (CTXDSA) The CTXDSA keeps the start address of Tx descriptor that is used by TxDMA currently. The CTXDSA is read only and write to this register has no effect.
W90N745CD/W90N745CDG BITS [31:0] DESCRIPTIONS CTXBSA Current Transmit Buffer Start Address Current Receive Descriptor Start Address Register (CRXDSA) The CRXDSA keeps the start address of Rx descriptor that is used by RxDMA currently. The CRXDSA is read only and write to this register has no effect.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 CRXBSA 23 22 21 20 19 CRXBSA 15 14 13 12 11 CRXBSA 7 6 5 4 3 CRXBSA BITS [31:0] DESCRIPTIONS CRXBSA Current Receive Buffer Start Address Receive Finite State Machine Register (RXFSM) The RXFSM shows the current value of the FSM (Finite State Machine) of RxDMA and RxFIFO controller. The RXFSM is read only and write to it has no effect. The RXFSM is used only for debug.
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:23] RX_FSM RxDMA FSM [22] Reserved - [21:16] RXBuf_FSM Receive Buffer FSM [15:12] RXFetch_FSM Receive Descriptor Fetch FSM [11:8] RXClose_FSM Receive Descriptor Close FSM [7:0] RFF_FSM RxFIFO Controller FSM Transmit Finite State Machine Register (TXFSM) The TXFSM shows the current value of the FSM (Finite State Machine) of TxDMA and TxFIFO controller. The TXFSM is read only and write to it has no effect. The TXFSM is used only for debug.
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:24] TX_FSM TxDMA FSM [23:22] Reserved - [21:16] TXBuf_FSM [15:12] TXFetch_FSM Transmit Descriptor Fetch FSM [11:8] TXClose_FSM Transmit Descriptor Close FSM [7:5] Reserved - [4:0] TFF_FSM TxFIFO Controller FSM Transmit Buffer FSM Finite State Machine Register 0 (FSM0) The FSM0 shows the current value of the FSM (Finite State Machine) of the function module in EMC. The FSM0 is read only and write to it has no effect.
W90N745CD/W90N745CDG Finite State Machine Register 1 (FSM1) The FSM1 shows the current value of the FSM (Finite State Machine) of the function module in EMC. The FSM1 is read only and write to it has no effect. The FSM1 is used only for debug.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 Reserved 23 22 21 20 19 Enable 15 Reserved 14 13 12 11 Reserved 7 6 5 4 3 Out Config BITS [31:24] DESCRIPTIONS Reserved The Function Enable outputs two function enable signals to external stimulus circuit. [23:22] Enable [21:8] Reserved [7:6] Out The Flag Out provides two output flags to trigger Logic Analyzer for debug. These two bits can be written at any time.
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG Debug Mode MAC Information Register (DMMIR) The DMMIR keeps the information of MAC module for debug.
W90N745CD/W90N745CDG BITS [31:5] [3:2] DESCRIPTIONS Reserved BistFail The BIST Fail indicates if the BIST test fails or succeeds. If the BistFail is low at the end, the embedded SRAM pass the BIST test, otherwise, it is faulty. The BistFail will be high once the BIST detects the error and remains high during the BIST operation. If BistFail[2] high indicates the embedded SRAM for TxFIFO BIST test failed. If BistFail[3] high indicates the embedded SRAM for RxFIFO BIST test failed.
W90N745CD/W90N745CDG 6.6 GDMA Controller The W90N745 has a two-channel general DMA controller, called the GDMA. The two-channel GDMA performs the following data transfers without the CPU intervention: y Memory-to-memory (memory to/from memory) y Memory –to – IO y IO- to -memory The on-chip GDMA can be started by the software or external DMA request nXDREQ. Software can also be used to restart the GDMA operation after it has been stopped.
W90N745CD/W90N745CDG 6.6.
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31] RESERVED - [30:28] TC_WIDTH nRTC/nWTC active width selection, from 1 to 7 HCLK cycles. REQ_SEL External request pin selection, if GDMAMS [3:2]=00, REQ_SEL will be don’t care. If REQ_SEL [27:26]=00, external request don’t use. If REQ_SEL [27:26]=01, use nXDREQ. If REQ_SEL [27:26]=10, external request don’t use. If REQ_SEL [27:26]=11, external request don’t use. REQ_ATV nXDREQ High/Low active selection 1’b0 = nXDREQ is LOW active.
W90N745CD/W90N745CDG Continued BITS DESCRIPTIONS AUTOIEN Auto initialization Enable 1’b0 = Disables auto initialization 1’b1 = Enables auto initialization, the GDMA_CSRC0/1, GDMA_CDST0/1,and GDMA_CTCNT0/1 registers are updated by the GDMA_SRC0/1,GDMA_DST0/1,and GDMA_TCNT0/1 registers automatically when transfer is complete. [18] TC Terminal Count 1’b0 = Channel does not expire 1’b1 = Channel expires; this bit is set only by GDMA hardware, and clear by software to write logic 0.
W90N745CD/W90N745CDG Continued BITS DESCRIPTIONS TWS Transfer Width Select 00 = One byte (8 bits) is transferred for every GDMA operation 01 = One half-word (16 bits) is transferred for every GDMA operation 10 = One word (32 bits) is transferred for every GDMA operation 11 = Reserved The GDMA_SCRB and GDMA_DSTB should be alignment under the TWS selection [11] SBMS Single/Block Mode Select 1’b0 = Selects single mode. It requires an external GDMA request for every incurring GDMA operation.
W90N745CD/W90N745CDG Continued BITS DESCRIPTIONS [4] Destination Address Direction 1’b0 = Destination address is incremented successively 1’b1 = Destination address is decremented successively DADIR [3:2] GDMAMS GDMA Mode Select 00 = Software mode (memory-to-memory) 01 = External nXDREQ mode for external device 10 = Reserved 11 = Reserved [1] Reserved - GDMAEN GDMA Enable 1’b0 = Disables the GDMA operation 1’b1 = Enables the GDMA operation; this bit will be clear automatically when the transfer
W90N745CD/W90N745CDG Channel 0/1 Destination Base Address Register (GDMA_DSTB0, DMA_DSTB1) Channel 0/1 Destination Base Address Register (GDMA_DSTB0, GDMA_DSTB1) The GDMA channel starts writing its data to the destination address as defined in this destination base address register. During a block transfer, the GDMA determines successive destination addresses by adding to or subtracting from the destination base address.
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:24] Reserved - [23:0] TFR_CNT The TFR_CNT represents the required number of GDMA transfers. The maximum transfer count is 16M –1.
W90N745CD/W90N745CDG Channel 0/1 Current Destination Register (GDMA_CDST0, GDMA_CDST1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GDMA_CDST0 0xFFF0_4014 R Channel 0 Current Destination Address Register 0x0000_0000 GDMA_CDST1 0xFFF0_4034 R Channel 1 Current Destination Address Register 0x0000_0000 31 30 23 22 15 14 7 6 29 28 27 CURRENT_DST_ADDR [31:24] 21 20 19 CURRENT_DST_ADDR [23:16] 13 12 11 CURRENT_DST_ADDR [15:8] 5 4 3 CURRENT_DST_ADDR [7:0] BITS [31:0] 26 25 24 18 17 1
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 Reserved 23 22 15 14 7 6 21 20 19 CURENT_TFR_CNT [23:16] 13 12 11 CURRENT_TFR_CNT [15:8] 5 4 3 CURRENT_TFR_CNT [7:0] BITS DESCRIPTIONS [31:24] Reserved [23:0] CURRENT_TFR_CNT Current Transfer Count register The current transfer count register indicates the number of transfer being performed - 167 - Publication Release Date: September 22, 2006 Revision A2
W90N745CD/W90N745CDG 6.7 USB Host Controller The Universal Serial Bus (USB) is a low-cost, low-to-mid-speed peripheral interface standard intended for modem, scanners, PDAs, keyboards, mice, and other devices that do not require a highbandwidth parallel interface. The USB is a 4-wire serial cable bus that supports serial data exchange between a Host Controller and a network of peripheral devices. The attached peripherals share USB bandwidth through a host-scheduled, token-based protocol.
W90N745CD/W90N745CDG Interrupt Processing Interrupts are the communication method for HC-initiated communication with the Host Controller Driver. There are several events that may trigger an interrupt from the Host Controller. Each specific event sets a specific bit in the HcInterruptStatus register. Host Controller Bus Master The Host Controller Bus Master is the central block in the data path. The Host Controller Bus Master coordinates all access to the AHB Interface.
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG Host Controller Revision Register REGISTER OFFSET ADDRESS R/W HcRevision 0xFFF0_5000 R 31 30 29 23 22 21 15 14 13 7 6 5 DESCRIPTION RESET VALUE Host Controller Revision Register 28 27 Reserved 20 19 Reserved 12 11 Reserved 4 3 Revision BITS 0x0000_0010 26 25 24 18 17 16 10 9 8 2 1 0 DESCRIPTION [31:8] Reserved Reserved. Read/Write 0's [7:0] Revision Indicates the Open HCI Specification revision number implemented by the Hardware.
W90N745CD/W90N745CDG BITS DESCRIPTION [31:11] Reserved [10] RWCE Reserved. Read/Write 0's RemoteWakeupConnectedEnable If a remote wakeup signal is supported, this bit enables that operation. Since there is no remote wakeup signal supported, this bit is ignored. RemoteWakeupConnected [9] RWC This bit indicated whether the HC supports a remote wakeup signal. This implementation does not support any such signal. The bit is hard-coded to ‘0.
W90N745CD/W90N745CDG Host Controller Command Status Register REGISTER ADDRESS HcCommandStatus 0xFFF0_5008 R/W RESET VALUE DESCRIPTION R/W Host Controller Command Status Register 31 30 29 28 23 22 21 15 14 20 Reserved 13 12 7 6 5 4 Reserved BITS 0x0000_0000 27 26 25 24 Reserved 19 18 17 16 10 9 8 2 BLF 1 CLF 0 HCR 11 Reserved 3 OCR DESCRIPTION [31:18] Reserved [17:16] SOC [15:4] Reserved [3] OCR Reserved ScheduleOverrunCount This field is increment every time th
W90N745CD/W90N745CDG Host Controller Interrupt Status Register All bits are set by hardware and cleared by software.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTION WritebackDoneHead [1] WDH Set after the Host HccaDoneHead. Controller has written HcDoneHead to SchedulingOverrun [0] SCHO Set when the List Processor determines a Schedule Overrun has occurred. Host Controller Interrupt Enable Register Writing a ‘1’ to a bit in this register sets the corresponding bit, while writing a ‘0’ leaves the bit unchanged.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTION FrameNumberOverflowEnable [5] FNOE 0: Ignore 1: Enable interrupt generation due to Frame Number Overflow. [4] UnrecoverableErrorEnable UREE This event is not implemented. All writes to this bit are ignored. ResumeDetectedEnable [3] RDTE 0: Ignore 1: Enable interrupt generation due to Resume Detected. StartOfFrameEnable [2] SOFE 0: Ignore 1: Enable interrupt generation due to Start of Frame.
W90N745CD/W90N745CDG BITS [31] DESCRIPTION MIE MasterInterruptEnable Global interrupt disable. A write of ‘1’ disables all interrupts. OwnershipChangeEnable [30] OCE 0: Ignore 1: Disable interrupt generation due to Ownership Change. [29:7] Reserved Reserved. Read/Write 0's RootHubStatusChangeEnable [6] RHSCE 0: Ignore 1: Disable interrupt generation due to Root Hub Status Change. FrameNumberOverflowEnable [5] FNOE 0: Ignore 1: Disable interrupt generation due to Frame Number Overflow.
W90N745CD/W90N745CDG Host Controller Communication Area Register REGISTER ADDRESS R/W HcHCCA 0xFFF0_5018 R/W 31 30 DESCRIPTION Host Controller Register 29 28 Communication RESET VALUE Area 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 Reserved 2 1 0 HCCA 23 22 21 20 15 14 13 12 7 6 5 4 HCCA HCCA BITS DESCRIPTION HCCA [31:8] [7:0] HCCA Pointer to HCCA base address.
W90N745CD/W90N745CDG Host Controller Control Head ED Register REGISTER ADDRESS HcControlHeadED 31 0xFFF0_5020 30 R/W DESCRIPTION RESET VALUE R/W Host Controller Control Head ED Register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHED 23 22 21 20 CHED 15 14 13 12 7 6 5 4 CHED CHED Reserved BITS DESCRIPTION ControlHeadED [31:4] CHED [3:0] Reserved Pointer to the Control List Head ED.
W90N745CD/W90N745CDG Host Controller Bulk Head ED Register REGISTER OFFSET ADDRESS HcBulkHEADED 0xFFF0_5028 R/W DESCRIPTION RESET VALUE R/W Host Controller Bulk Head ED Register 31 30 29 28 23 22 21 20 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BHED BHED 15 14 13 12 BHED 7 6 5 4 BHED Reserved BITS DESCRIPTION [31:4] BHED [3:0] Reserved BulkHeadED. Pointer to the Bulk List Head ED. Reserved.
W90N745CD/W90N745CDG Host Controller Done Head Register REGISTER ADDRESS HcDoneHead 0xFFF0_5030 R/W DESCRIPTION RESET VALUE R/W Host Controller Done Head Register 31 30 29 28 23 22 21 20 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DOHD DOHD 15 14 13 12 DOHD 7 6 5 4 DOHD Reserved BITS DESCRIPTION [31:4] DOHD [3:0] Reserved DoneHead. Pointer to the current Done List Head ED. Reserved.
W90N745CD/W90N745CDG BITS DESCRIPTION 31 FrameIntervalToggle FINTVT This bit is toggled by HCD when it loads a new value into Frame Interval. FSLargestDataPacket [30:16] FSLDP [15:14] Reserved [13:0] FINTV This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. Reserved. Read/Write 0's Frame Interval This field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here.
W90N745CD/W90N745CDG Host Controller Frame Number Register REGISTER ADDRESS R/W HcFmNumber 0xFFF0_503C R DESCRIPTION RESET VALUE Host Controller Frame Number Register 31 30 29 28 23 22 21 20 27 0x0000_0000 26 25 24 18 17 16 11 10 9 8 3 2 1 0 Reserved 19 Reserved 15 14 13 12 FRMN 7 6 5 4 FRMN BITS DESCRIPTION [31:16] Reserved [15:0] FRMN Reserved.
W90N745CD/W90N745CDG BITS DESCRIPTION [31:14] Reserved Reserved. Read/Write 0's PeriodicStart [13:0] PERST This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 18 17 16 POTPGT 23 22 21 20 19 Reserved 15 14 13 Reserved 7 6 5 12 11 10 9 8 OCPM OCPM DEVT NPSW PSWM 3 2 1 0 4 NDSP BITS DESCRIPTION PowerOnToPowerGoodTime [31:24] [23:13] POTPGT Reserved This field value is represented as the number of 2 ms intervals, which ensuring that the power switching is effective within 2 ms. Only bits [25:24] is implemented as R/W. The remaining bits are read only as ‘0’.
W90N745CD/W90N745CDG Host Controller Root Hub Descriptor B Register This register is only reset by a power-on reset. It is written during system initialization to configure the Root Hub. These bits should not be written during normal operation.
W90N745CD/W90N745CDG Host Controller Root Hub Status Register This register is reset by the USBRESET state.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTION OverCurrentIndicator [1] This bit reflects the state of the OVRCUR pin. This field is only valid if NoOverCurrentProtection and OverCurrentProtectionMode are cleared. 0 = No over-current condition 1 = Over-current condition OVRCI (Read) LocalPowerStatus Not Supported. Always read '0'. [0] LOPS (Write) ClearGlobalPower Writing a '1' issues a ClearGlobalPower command to the ports. Writing a '0' has no effect.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTION PortOverCurrentIndicatorChange [19] POCIC This bit is set when OverCurrentIndicator changes. Writing a '1' clears this bit. Writing a '0' has no effect. PortSuspendStatusChange [18] PSSC This bit indicates the completion of the selective resume sequence for the port. 0 = Port is not resumed. 1 = Port resume is complete.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTION (Read) PortResetStatus [4] SPR 0 = Port reset signal is not active. 1 = Port reset signal is active. (Write) SetPortReset Writing a '1' sets PortResetStatus. Writing a '0' has no effect. (Read) PortOverCurrentIndicator [3] CPS table of none-2 supports global over-current reporting. This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set.
W90N745CD/W90N745CDG USB Operational Mode Enable Register This register selects which operational mode is enabled. Bits defined as write-only are read as 0's.
W90N745CD/W90N745CDG 6.8 USB Device Controller The USB controller interfaces the AHB bus and the USB bus. The USB controller contains both the AHB master interface and AHB slave interface. CPU programs the USB controller through the AHB slave interface. For IN or OUT transfer, the USB controller needs to write data to memory or read data from memory through the AHB master interface. The USB controller also contains the USB transceiver to interface the USB. 6.8.
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:8] Reserved [7] CCMD USB Class Command Decode Control Enable 0: Disable, the H/W circuit doesn’t need to decode USB class command. It will return a stall status when it received a USB Class Command. 1: Enable, the H/W circuit decodes USB class command. It will assert an interrupt event when it received a USB Class Command. VCMD USB Vendor Command Decode Enable 0: Disable, the H/W circuit doesn’t need to decode USB vendor command.
W90N745CD/W90N745CDG USB Class or Vendor command Register (USB_CVCMD) REGISTER ADDRESS USB_CVCMD 0xFFF0_6004 31 30 R/W R/W 29 DESCRIPTION RESET VALUE USB class or vendor command register 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved CVI_LG BITS DESCRIPTIONS [31:5] [4:0] Reserved CVI_LG Byte Length for Class and Vendor Command and Get Descriptor Return Data Packet USB Interrupt Enab
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:16] Reserved [15] RUM_CLKI Interrupt enable for RESUME (for clock is stopped) 0: Disable 1: Enable [14] RST_ENDI Interrupt enable for USB reset end 0: Disable 1: Enable [13] USB_CGI Interrupt Enable for Device Configured 0: Disable 1: Enable Note: the interrupt occurs when device configured or dis-configured.
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:16] Reserved Interrupt status for RESUME (for clock is stopped) [15] RUM_CLKS 0: No Interrupt Generated 1: Interrupt Generated Interrupt status for USB reset end [14] RSTENDS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for USB Device Configured [13] USB_CGS 0: No Interrupt Generated 1: Interrupt Generated(configured and dis-configured) Interrupt Status for USB Bus Transition [12] USB_BTS 0: No Interrupt Generated 1: Interrupt G
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG 31 30 29 23 22 21 28 Reserved 20 27 26 25 24 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RUM_CLKC RSTENDC USB_CGC USB_BTC CVSC CDIC CDOC VENC 7 6 5 4 3 2 1 0 CLAC GSTRC GCFGC GDEVC ERRC RUMC SUSC RSTC BITS DESCRIPTIONS [31:16] Reserved [15] RUM_CLKC Interrupt status clear for RESUME (for clock is stopped) 0: NO Operation 1: Clear Interrupt Status [14] RSTENDC Interrupt status clear for USB reset end 0: NO Operation 1: Clear Interru
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 23 22 21 Reserved 20 19 18 17 16 10 9 8 STR6_EN STR5_EN Reserved 15 14 13 12 11 Reserved 7 6 5 4 3 2 1 0 STR4_EN STR3_EN STR2_EN STR1_EN INF4_EN INF3_EN INF2_EN INF1_EN BITS DESCRIPTIONS [31:10] Reserved USB String Descriptor-6 Control [9] STR6_EN 0: Disable 1: Enable USB String Descriptor-5 Control [8] STR5_EN 0: Disable 1: Enable USB String Descriptor-4 Control [7] STR4_EN 0: Disable 1: Enable USB String Desc
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG USB Control transfer-out port 1 (USB_ODATA1) REGISTER ADDRESS USB_ODATA1 0xFFF0601C 31 30 R/W R DESCRIPTION RESET VALUE USB control transfer-out port 1 register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA1 23 22 21 20 ODATA1 15 14 13 12 ODATA1 7 6 5 4 ODATA1 BITS [31:0] DESCRIPTIONS ODATA1 Control Transfer-out data 1 USB Control transfer-out port 2 (USB_ODATA2) REGISTER ADDRESS R/W USB_ODATA2 0xFFF06020 R 31 30
W90N745CD/W90N745CDG USB Control transfer-out port 3 (USB_ODATA3) REGISTER ADDRESS USB_ODATA3 0xFFF06024 31 30 R/W R 29 DESCRIPTION RESET VALUE USB control transfer-out port 3 register 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA3 23 22 21 20 ODATA3 15 14 13 12 ODATA3 7 6 5 4 ODATA3 BITS [31:0] DESCRIPTIONS ODATA3 Control Transfer-out data 3 USB Control transfer-in data port0 Register (USB_IDATA0) REGISTER USB_IDATA0 31 ADDRESS R/W 0xFFF060
W90N745CD/W90N745CDG USB Control transfer-in data port 1 Register (USB_IDATA1) REGISTER USB_IDATA1 31 ADDRESS R/W 0xFFF0602C 30 R/W 29 DESCRIPTION RESET VALUE USB control transfer-in data port 1 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA1 23 22 21 20 IDATA1 15 14 13 12 IDATA1 7 6 5 4 IDATA1 BITS [31:6] DESCRIPTIONS IDATA1 Control transfer-in data1 USB Control transfer-in data port 2 Register (USB_IDATA2) REGISTER USB_IDATA2 31 ADDRESS R/W 0
W90N745CD/W90N745CDG USB Control transfer-in data port 3 Register (USB_IDATA3) REGISTER USB_IDATA3 31 ADDRESS R/W 0xFFF06034 R/W 30 29 DESCRIPTION RESET VALUE USB control transfer-in data port 3 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA3 23 22 21 20 IDATA3 15 14 13 12 IDATA3 7 6 5 4 IDATA3 BITS [31:6] DESCRIPTIONS IDATA3 Control transfer-in data3 USB SIE Status Register (USB_SIE) REGISTER USB_SIE 31 ADDRESS R/W 0xFFF06038 30 R 29 DESCR
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:2] Reserved [1] USB_DPS USB Bus D+ Signal Status 0: USB Bus D+ Signal is low 1: USB Bus D+ Signal is high USB_DMS USB Bus D- Signal Status 0: USB Bus D- Signal is low 1: USB Bus D- Signal is high [0] USB Engine Register (USB_ENG) REGISTER USB_ENG ADDRESS 0xFFF0603C R/W DESCRIPTION R/W RESET VALUE USB Engine Register 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 Reserved 19 18 17 16 10 9 8 3 2 1 0 SDO_RD CV_LDA CV_STL
W90N745CD/W90N745CDG Continued. BITS [1] [0] DESCRIPTIONS CV_STL USB Class and Vendor Command Stall Control 0: NO Operation 1: Return Stall for Class and Vendor Command NOTE: this bit will auto clear after 32 HCLK CV_DAT USB Class and Vendor Command return data control 0: NO Operation 1: The Data Packet for Data Input of Class and Vendor Command or Get Descriptor command is ready.
W90N745CD/W90N745CDG USB Configured Value Register (USB_CONFD) REGISTER USB_CONFD 31 ADDRESS R/W 0xFFF06044 R/W 30 29 DESCRIPTION RESET VALUE USB Configured Value register 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 CONFD BITS DESCRIPTIONS [31:8] [7:0] Reserved CONFD Software configured value USB Endpoint A Information Register (EPA_INFO) REGISTER EPA_INFO 31 Reserved 23 ADDRESS R/W 0xF
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31] Reserved [30:29] EPA_TYPE Endpoint A type 00: reserved 01: bulk 10: interrupt 11: isochronous [28] EPA_DIR Endpoint A direction 0: OUT 1: IN [27:26] Reserved [25:16] EPA_MPS Endpoint A max.
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:6] Reserved [6] EPA_ZERO Send zero length packet to HOST [5] EPA_STL_CLR CLEAR the Endpoint A stall(WRITE ONLY) Endpoint A threshold (only for ISO) [4] 1: once available space in FIFO over 16 bytes, DMA accesses memory EPA_THRE 0: once available space in FIFO over 32 bytes, DMA accesses memory [3] EPA_STL Set the Endpoint A stall [2] EPA_RDY The memory is ready for Endpoint A to access [1] EPA_RST Endpoint A reset [0] EPA_EN Endpoint A enab
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:6] Reserved [5] EPA_CF_IE Endpoint A clear feature interrupt enable [4] EPA_BUS_ERR_IE Endpoint A system bus error interrupt enable [3] EPA_DMA_IE Endpoint A DMA transfer complete interrupt enable [2] EPA_ALT_IE Endpoint A alternate setting interrupt enable [1] EPA_TK_IE Endpoint A token input interrupt enable [0] EPA_STL_IE Endpoint A stall interrupt enable USB Endpoint A Interrupt Clear Register (EPA_IC) REGISTER EPA_IC ADDRESS 0xFFF0605
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG USB Endpoint A Address Register (EPA_ADDR) REGISTER EPA_ADDR ADDRESS R/W 0xFFF0605C R/W DESCRIPTION RESET VALUE USB endpoint A address register 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 EPA_ADDR 20 19 18 17 16 10 9 8 2 1 0 EPA_ADDR 15 14 13 12 11 EPA_ADDR 7 6 5 4 3 EPA_ADDR BITS [31:0] DESCRIPTIONS EPA_ADDR Endpoint A transfer address USB Endpoint A transfer length Register (EPA_LENTH) REGISTER EPA_LENTH 31 ADDRESS R/W 0xFFF06060
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:20] [19:0] Reserved EPA_LENTH Endpoint A transfer length USB Endpoint B Information Register (EPB_INFO) REGISTER EPB_INFO 31 Reserved 23 ADDRESS R/W 0xFFF06064 R/W 30 DESCRIPTION USB endpoint B information register 29 EPB_TYPE 22 RESET VALUE 28 27 EPB_DIR 21 26 0x0000_0000 25 Reserved 20 24 EPB_MPS 19 18 17 16 11 10 9 8 1 0 EPB_MPS 15 14 13 12 EPB_ALT 7 6 EPB_INF 5 4 3 2 EPB_CFG BITS EPB_NUM DESCRIPTIONS [31] Reser
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG USB Endpoint B Interrupt Clear Register (EPB_IC) REGISTER EPB_IC 31 ADDRESS R/W 0xFFF06070 30 W 29 DESCRIPTION USB endpoint register 28 B interrupt 27 RESET VALUE clear 0x0000_0000 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 Reserved 5 4 3 2 1 0 EPB_CF_IC EPB_BUS_ERR_IC EPB_DMA_IC EPB_ALT_IC EPB_TK_IC EPB_STL_IC BITS DESCRIPTIONS [31:6] Reserved [5] EPB_CF_IC Endpoint B clear feature inte
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 Reserved 5 4 3 2 1 0 EPB_CF_IS EPB_BUS_ERR_IS EPB_DMA_IS EPB_ALT_IS EPB_TK_IS EPB_STL_IS BITS DESCRIPTIONS [31:6] Reserved [5] EPB_CF_IS Endpoint B clear feature interrupt status [4] EPB_DMA_IS Endpoint B system bus error interrupt status [3] EPB_DMA_IS Endpoint B DMA transfer complete interrupt status [2] EPB_ALT_IS Endpoint B alter
W90N745CD/W90N745CDG BITS [31:0] DESCRIPTIONS EPB_ADDR Endpoint B transfer address USB Endpoint B transfer length Register (EPB_LENTH) REGISTER EPB_LENTH 31 ADDRESS R/W 0xFFF0607C 30 R/W 29 DESCRIPTION USB endpoint register 28 B RESET VALUE transfer length 0x0000_0000 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 EPB_LENTH 13 12 11 10 9 8 2 1 0 EPB_LENTH 7 6 5 4 3 EPB_LENTH BITS DESCRIPTIONS [31:20] [19:0] Reserved EPB_LENTH Endpoint B tr
W90N745CD/W90N745CDG 31 Reserved 23 30 29 EPC_TYPE 22 28 27 EPC_DIR 21 20 26 25 Reserved 24 EPC_MPS 19 18 17 16 11 10 9 8 1 0 EPC_MPS 15 14 13 12 EPC_ALT 7 6 EPC_INF 5 4 3 EPC_CFG BITS 2 EPC_NUM DESCRIPTIONS [31] Reserved Endpoint C type 00: reserved [30:29] EPC_TYPE 01: bulk 10: interrupt 11: isochronous Endpoint C direction [28] EPC_DIR 0: OUT 1: IN [27:26] Reserved [25:16] EPC_MPS Endpoint C max.
W90N745CD/W90N745CDG USB Endpoint C Control Register (EPC_CTL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPC_CTL 0xFFF06084 R/W USB endpoint C control register 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 3 2 1 0 Reserved EPC_ZERO EPC_STL_CLR EPC_THRE EPC_STL EPC_RDY EPC_RST EPC_EN BITS DESCRIPTIONS [31:7] Reserved [6] EPC_ZERO Send zero length packet back to HOST [5] EPC_STL_
W90N745CD/W90N745CDG USB Endpoint C interrupt enable Register (EPC_IE) REGISTER EPC_IE 31 30 ADDRESS R/W DESCRIPTION 0xFFF0608 8 R/W USB endpoint C Interrupt Enable register 29 28 27 RESET VALUE 0x0000_0000 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 Reserved 5 4 3 2 1 0 EPC_CF_IE EPC_BUS_ERR_IE EPC_DMA_IE EPC_ALT_IE EPC_TK_IE EPC_STL_IE BITS DESCRIPTIONS [31:6] Reserved [5] EPC_CF_IE Endpoint C clear feature in
W90N745CD/W90N745CDG 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EPC_ALT_IC EPC_TK_IC EPC_STL_IC Reserved Reserved 15 14 13 12 Reserved 7 6 Reserved 5 4 EPC_CF_IC EPC_BUS_ERR_IC EPC_DMA_IC BITS DESCRIPTIONS [31:6] Reserved [5] EPC_CF_IC Endpoint C clear feature interrupt clear [4] EPC_DMA_IC Endpoint C system bus error interrupt clear [3] EPC_DMA_IC Endpoint C DMA transfer complete interrupt clear [2] EPC_ALT_IC Endpoint C alternate
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 Reserved 4 EPC_CF_IS 3 EPC_BUS_ERR_IS EPC_DMA_IS BITS EPC_ALT_IS EPC_TK_IS EPC_STL_IS DESCRIPTIONS [31:6] Reserved [5] EPC_CF_IS Endpoint C clear feature interrupt status [4] EPC_BUS_ERR_IS Endpoint A system bus error interrupt status [3] EPC_DMA_IS Endpoint A DMA transfer complete interrupt status [2] EPC_ALT_IS Endpoint A al
W90N745CD/W90N745CDG BITS [31:0] DESCRIPTIONS EPC_ADDR Endpoint C transfer address USB Endpoint C transfer length Register (EPC_LENTH) REGISTER ADDRESS EPC_LENTH 31 0xFFF0_6098 30 29 R/W DESCRIPTION R/W USB endpoint C transfer length register 28 RESET VALUE 0x0000_0000 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 EPC_LENTH 13 12 11 10 9 8 2 1 0 EPC_LENTH 7 6 5 4 3 EPC_LENTH BITS DESCRIPTIONS [31:20] [19:0] Reserved EPC_LENTH Endpoint C trans
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 EPA_XFER 13 12 11 10 9 8 2 1 0 EPA_XFER 7 6 5 4 3 EPA_XFER BITS DESCRIPTIONS [31:20] [19:0] Reserved EPA_XFER Endpoint A remain transfer length USB Endpoint A Remain packet length Register (EPA_PKT) REGISTER ADDRESS EPA_PKT 0xFFF0_60A0 31 30 R/W RESET VALUE DESCRIPTION R/W USB endpoint A remain packet length register 29 28 0x0000_0000 27 26 25 24 19 18 17 16
W90N745CD/W90N745CDG USB Endpoint B Remain transfer length Register (EPB_XFER) REGISTER EPB_XFER 31 ADDRESS R/W DESCRIPTION 0xFFF0_60A4 R/W USB endpoint B remain transfer length register 30 29 28 RESET VALUE 0x0000_0000 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 EPB_XFER 13 12 11 10 9 8 2 1 0 EPB_XFER 7 6 5 4 3 EPB_XFER BITS DESCRIPTIONS [31:20] [19:0] Reserved EPB_XFER Endpoint B remain transfer length USB Endpoint B Remain packet length Regi
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:10] [9:0] Reserved EPB_PKT Endpoint B remain packet length USB Endpoint C Remain transfer length Register (EPC_XFER) REGISTER EPC_XFER 31 ADDRESS 0xFFF0_60AC 30 R/W DESCRIPTION R/W USB endpoint C remain transfer length register 29 28 RESET VALUE 0x0000_0000 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 EPC_XFER 13 12 11 10 9 8 2 1 0 EPC_XFER 7 6 5 4 3 EPC_XFER BITS DESCRIPTIONS [31:20] [19:0] Reserved
W90N745CD/W90N745CDG USB Endpoint C Remain packet length Register (EPC_PKT) REGISTER EPC_PKT 31 ADDRESS R/W 0xFFF0_60B0 R/W 30 29 DESCRIPTION USB endpoint length register 28 C 27 remain RESET VALUE packet 0x0000_0000 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 EPC_PKT 4 3 EPC_PKT BITS DESCRIPTIONS [31:10] [9:0] Reserved EPC_PKT Endpoint C remain packet length - 230 - 2 1 0
W90N745CD/W90N745CDG 6.9 Audio Controller The audio controller consists of I²S/AC-link protocol to interface with external audio CODEC. One 8-level deep FIFO for read path and write path and each level has 32-bit width (16 bits for right channel and 16 bits for left channel). One DMA controller handles the data movement between FIFO and memory. The following are the property of the DMA.
W90N745CD/W90N745CDG The 16 bits I²S and MSB-justified format are support, the timing diagram is shown as Figure 6.9.2 LRC LK L e ft 1 2 R ig h t 3 1 2 BCK DATA B2 M SB LSB M SB I2S b u s LRC LK L e ft 1 2 R ig h t 3 1 2 BCK DATA M SB B2 LSB B3 M SB B2 M S B – J u s tif ie d f o r m a t Figure 6.9.2 The format of I²S The sampling rate, bit shift clock frequency could be set by the control register ACTL_I²SCON. 6.9.
W90N745CD/W90N745CDG The signal format is shown as Figure 6.9.4 Frame (48 KHz) Data phase Tag phase SYN 12.288 MHz BCL . . . . . . DIN . . . . . . . . . . . . DOU B255 B0 MS B1 B15 B16 Slot 0 LS B35 B36 Slot 1 B55 B56 Slot 2 B75 B76 B95 B96 Slot 4 Slot 3 B255 Slot 5 –12 Figure 6.9.
W90N745CD/W90N745CDG Continued. SLOT # CMD DATA (slot 2) PCM LEFT (slot 3) PCM RIGHT (slot 4) BIT DESCRIPTION 19 - 4 Control register write data. It should be cleared to 0 if current operation is read.
W90N745CD/W90N745CDG 6.9.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Reserved Reserved Reserved R_DMA_IRQ T_DMA_IRQ 7 6 5 4 3 FIFO_TH Reserved Reserved BITS Reserved - [14] Reserved - [13] Reserved - [11] 2 I²S_AC_PIN_SEL 1 BLOCK_EN[1:0] Reserved R_DMA_IRQ When recording, when the DMA destination current address reach the DMA destination end address or middle address, the R_DMA_IRQ bit will be set to 1 automatically, and this bit cou
W90N745CD/W90N745CDG Sub-block reset control register (ACTL_RESET) REGISTER ACTL_RESET ADDRESS R/W 0xFFF0_9004 R/W DESCRIPTION RESET VALUE Sub block reset control 0x0000_0000 The value in ACTL_RESET register control the reset operation in each sub block.
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG The value in ACTL_RDSTB register is the record destination base address of DMA, and only could be changed by CPU. 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 AUDIO_RDSTB[31:24] 23 22 21 20 19 AUDIO_RDSTB[23:16] 15 14 13 12 11 AUDIO_RDSTB[15:8] 7 6 5 4 3 AUDIO_RDSTB[7:0] BITS [31:0] DESCRIPTIONS AUDIO_RDSTB[31:0] 32-bit record destination base address The AUDIO_RDSTB[31:0] bits is read/write.
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:0] 32-bit record destination address length AUDIO_RDST_L[31:0] The AUDIO_RDST_L[31:0] bits is read/write. DMA destination current address (ACTL_RDSTC) REGISTER ACTL_RDSTC ADDRESS 0xFFF0_9010 R/W RO DESCRIPTION RESET VALUE DMA record destination current address 0x0000_0000 The value in ACTL_RDSTC is the DMA record destination current address, this register could only be read by CPU.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 17 16 9 8 1 0 Reserved 23 22 21 20 19 18 Reserved 15 14 13 12 11 10 Reserved 7 6 5 4 3 Reserved 2 R_FIFO_FULL BITS R_DMA_END_IRQ R_DMA_MIDDLE_IRQ DESCRIPTIONS [31:3] Reserved Record FIFO full indicator bit [2] R_FIFO_FULL R_FIFO_FULL=0, the record FIFO not full R_FIFO_FULL=1, the record FIFO is full The R_FIFO_READY bit is read only DMA end address interrupt request bit for record [1] R_DMA_END_IRQ R_DMA_END_IRQ=0, mean
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 AUDIO_PDSTB[31:24] 23 22 21 20 19 AUDIO_PDSTB[23:16] 15 14 13 12 11 AUDIO_PDSTB[15:8] 7 6 5 4 3 AUDIO_PDSTB[7:0] BITS [31:0] DESCRIPTIONS AUDIO_PDSTB[31:0] 32-bit play destination base address The AUDIO_PDSTB[31:0] bits is read/write.
W90N745CD/W90N745CDG BITS [31:0] DESCRIPTIONS 32-bit play destination address length AUDIO_PDST_L[31:0] The AUDIO_PDST_L[31:0] bits is read/write. DMA destination current address (ACTL_PDSTC) REGISTER ADDRESS R/W 0xFFF0_9020 RO ACTL_PDSTC DESCRIPTION RESET VALUE DMA play destination current address 0x0000_0000 The value in ACTL_PDSTC is the DMA play destination current address, this register could only be read by CPU.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 17 16 9 8 1 0 Reserved 23 22 21 20 19 18 Reserved 15 14 13 12 11 10 Reserved 7 6 5 4 3 Reserved 2 P_FIFO_EMPTY P_DMA_END_IRQ P_DMA_MIDDLE_IRQ BITS DESCRIPTIONS [31:3] Reserved Playback FIFO empty indicator bit [2] P_FIFO_EMPTY P_FIFO_EMPTY=0, the playback FIFO is not empty P_FIFO_EMPTY=1, the playback FIFO is empty The P_FIFO_EMPTY bit is read only DMA end address interrupt request bit for playback [1] P_DMA_END_IRQ P_D
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 PRS[3:0] 13 12 11 10 9 8 2 1 0 Reserved 7 6 BCLK_SEL[1:0] 5 4 3 FS_SEL MCLK_SEL FORMAT BITS [31:20] Reserved DESCRIPTIONS Reserved I²S frequency pre-scaler selection bits.
W90N745CD/W90N745CDG Continued BITS DESCRIPTIONS I²S serial data clock frequency selection bit [7:6] BCLK_SEL [1:0] BCLK_SEL[1:0]=00, 32fs is selected (fs is sampling rate), when FS_SEL=0, the frequency of bit clock is MCLK/8, when FS_SEL=1, the frequency of bit clock is MCLK/12. BCLK_SEL[1:0]=01, 48fs is selected (only when FS_SEL=1, this term could be selection), when FS_SEL=1, the frequency of bit clock is MCLK/8.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 Reserved 5 4 AC_BCLK_PU_EN AC_R_FINISH AC_W_FINISH BITS [6] [5] [4] [3] AC_W_RES AC_C_RES Reserved DESCRIPTIONS Reserved - AC_BCLK_PU_EN This bit controls the AC_BCLK pin pull-high resister.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTIONS AC_W_RES AC-link warm reset control bit, when this bit is set to 1, (AC-link begin warn reset procedure, after warn reset procedure finished, this bit will be cleared automatically) the interface signal AC_SYNC is high, when this bit is set to 0, the interface signal AC_SYNC is controlled by AC_BCLK input when this bit is set to 1. Note the AC-link spec. shows it need at least 10 us high duration of AC_SYNC to warn reset AC97.
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:5] Reserved Frame valid indicated bits [4] VALID_FRAME=1, any one of slot is valid VALID_FRAME=0, no any slot is valid The VALID_FRAME bits are read/write VALID_FRAME Slot valid indicated bits [3:0] SLOT_VALID[0]= 1/0, indicate Slot 1 valid/invalid SLOT_VALID[1]= 1/0, indicate Slot 2 valid/invalid SLOT_VALID[2]= 1/0, indicate Slot 3 valid/invalid SLOT_VALID[3]= 1/0, indicate Slot 4 valid/invalid The SLOT_VALID[3:0] bits are read/write SLOT_VALID [3:0] Th
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:8] Reserved Read/Write select bit [7] R_WB [6:0] R_INDEX[6:0] R_WB=1, a read specified by R_INDEX[6:0] will occur, and the data will appear in next frame R_WB=0, a write specified by R_INDEX[6:0] will occur, and the write data is put at out slot 2 The R_WB bit is read/write External AC97 CODEC control register index (address) bits The R_INDEX[6:0] bits are read/write AC-link output slot 2 (ACTL_ACOS2) REGISTER ACTL_ACOS2 ADDRESS R/W 0xFFF0_9038 R/W
W90N745CD/W90N745CDG AC-link input slot 0 (ACTL_ACIS0) REGISTER ACTL_ACIS0 ADDRESS R/W 0xFFF0_903C R DESCRIPTION RESET VALUE AC-link in slot 0 0x0000_0000 The ACTL_ACIS0 store the shift in slot 0 data of AC-link.
W90N745CD/W90N745CDG AC-link input slot 1 (ACTL_ACIS1) REGISTER ACTL_ACIS1 ADDRESS R/W 0xFFF0_9040 R DESCRIPTION RESET VALUE AC-link in slot 1 0x0000_0000 The ACTL_ACIS1 stores the shift in slot 1 data of AC-link. 31 30 29 28 27 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 4 R_INDEX[6] 3 2 R_INDEX[5:0] BITS [31:9] [8:2] 1 0 SLOT_REQ[1:0] DESCRIPTIONS Reserved R_INDEX[6:0] Register index.
W90N745CD/W90N745CDG AC-link input slot 2 (ACTL_ACIS2) REGISTER ACTL_ACIS2 ADDRESS R/W 0xFFF0_9044 R DESCRIPTION RESET VALUE AC-link in slot 2 0x0000_0000 The ACTL_ACIS2 stores the shift in slot 2 data of AC-link. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 RD[15:8] 7 6 5 4 RD[7:0] BITS DESCRIPTIONS [31:16] Reserved [15:0] RD[15:0] AC-link read data.
W90N745CD/W90N745CDG 6.10 Universal Asynchronous Receiver/Transmitter Controller Asynchronous serial communication block include 4 UART blocks and accessory logic. They can be described as follow: • UART0 It is merely a general purpose UART. It does not include any accessory function.
W90N745CD/W90N745CDG • FIFO Number : 16-byte receiving FIFO and 16 byte transmitting FIFO Modem Function : N/A Accessory Function : IrDA SIR (optional) I/O Pin : TXD2, RXD2. I/O Pin Share with : UART1 (Bluetooth function) UART3 It is also merely a general purpose UART. It does not include any accessory function. It share four I/O pins with AC97/I²S.
W90N745CD/W90N745CDG 6.10.1 UART0 UART0 is a general UART block. It is same as the UART in W90N740 but without Modem I/O signals. More detail function description, please refer to section 7.10.5 General UARTcontroller description Table 6.10.
W90N745CD/W90N745CDG Table 6.10.
W90N745CD/W90N745CDG BITS [31:3] DESCRIPTIONS Reserved UBCR is a 3 bits register which is used to select clock source to generate suitable baud rate: 000: 15Mhz from external crystal [2:0] UBCR 100: 30Mhz divided from PLL 480Mhz 101: 43.6Mhz divided from PLL 480Mhz 110: 48Mhz divided from PLL 480Mhz 111: 60Mhz divided from PLL 480Mhz 6.10.3 UART2 UART2 contains 2 features: general UART and IrDA SIR decoder/encoder. UART is same as the UART of W90N740 but without modem function.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 3 2 Reserved INV_RX INV_TX Reserved Reserved LB BITS TX_SELECT IrDA_EN DESCRIPTIONS [31:7] Reserved [6] INV_RX [5] INV_TX [4:3] Reserved Reserved 1: Inverse RX input signal 0: No inversion 1: Inverse TX output signal 0: No inversion Reserved IrDA loop back mode for self test.
W90N745CD/W90N745CDG 6.10.4 UART3 UART3 is a general UART block. It is same as the UART in W90N740 but with some Modem I/O signals. More detail general UART function description, please refer to next section 7.10.5 General UART controller. Table 6.10.
W90N745CD/W90N745CDG UART3 Modem Status Register (UART3_MSR) REGISTER ADDRESS R/W UART3_MSR 0xFFF8_0318 31 30 R DESCRIPTION RESET VALUE UART 3 Modem Status Register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 3 2 1 0 Reserved Reserved DSR# Reserved Reserved Reserved DDSR Reserved Note: UART3_MSR is subset of MSR in W90N745. Please refer to section 7.10.5 ‘General UART Controller’. 6.10.
W90N745CD/W90N745CDG y Line break generation and detection y False start bit detection y Full prioritized interrupt system controls y Loop back mode for internal diagnostic testing 6.10.5.1.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 8-bit Received Data BITS DESCRIPTIONS By reading this register, the UART will return an 8-bit data received from SIN pin (LSB first).
W90N745CD/W90N745CDG UART Interrupt Enable Register (UART_IER) REGISTER OFFSET R/W UART_IER 0x04 R/W 31 30 DESCRIPTION RESET VALUE Interrupt Enable Register (DLAB = 0) 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 4 3 2 1 0 nDBGACK_EN MSIE RLSIE THREIE RDAIE Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 RESERVED BITS [31:5] DESCRIPTIONS Reserved ICE debug mode acknowledge enable 0 = When DBGACK is high, the UART receiver time-out clock wil
W90N745CD/W90N745CDG UART Divider Latch (Low Byte) Register (UART_DLL) REGISTER OFFSET R/W UART_DLL 0x00 R/W 31 30 DESCRIPTION RESET VALUE Divisor Latch Register (LS) (DLAB = 1) 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Baud Rate Divider (Low Byte) BITS [7:0] DESCRIPTIONS Baud Rate Divider (Low Byte) The low byte of the baud rate divider UART Divisor Latch (High Byte) Register (UART_DL
W90N745CD/W90N745CDG BITS DESCRIPTIONS Baud Rate Divider (High Byte) [7:0] The high byte of the baud rate divider This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows Baud Rate = Crystal Clock / {16 * [Divisor + 2]} Note: This definition is different from 16550 UART Interrupt Identification Register (UART_IIR) REGISTER OFFSET R/W UART_IIR 0x08 R 31 30 DESCRIPTION RESET VALUE Interrupt Identification Register 29 28 0x8181_8181 27 26 25 24 19 18 17 16 11 10
W90N745CD/W90N745CDG Table 6.10.
W90N745CD/W90N745CDG BITS DESCRIPTIONS RX FIFO Interrupt (Irpt_RDA) Trigger Level [7:6] RFITL [7:6] Irpt_RDA Trigger Level (Bytes) 00 01 01 04 10 08 11 14 RFITL [3] [2] [1] [0] DMS DMA Mode Select The DMA function is not implemented in this version. TFR TX FIFO Reset Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO. The TX FIFO becomes empty (TX pointer is reset to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is generated.
W90N745CD/W90N745CDG BITS DESCRIPTIONS Divider Latch Access Bit [7] DLAB 0 = It is used to access RBR, THR or IER. 1 = It is used to access Divisor Latch Registers {DLL, DLM} Break Control Bit [6] BCB When this bit is set to logic 1, the serial data output (SOUT) is forced to the Spacing State (logic 0). This bit acts only on SOUT and has no effect on the transmitter logic.
W90N745CD/W90N745CDG UART Modem Control Register (UART_MCR) REGISTER OFFSET R/W UART_MCR 0x10 R/W 31 30 29 DESCRIPTION RESET VALUE 0x0000_0000 Modem Control Register (Optional) 28 27 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 Reserved BITS [31:5] 4 3 2 1 0 LBME Reserve Reserve Reserved DTR# DESCRIPTIONS Reserved - Loop-back Mode Enable 0 = Disable [4] LBME 1 = When the loop-back mode is enabled, the following
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 3 2 1 0 ERR_RX TE THRE BII FEI PEI OEI RFDR BITS [31:8] DESCRIPTIONS Reserved - RX FIFO Error 0 = RX FIFO works normally [7] ERR_RX 1 = There is at least one parity error (PE), framing error (FE), or break indication (BI) in the FIFO. ERR_RX is cleared when CPU reads the LSR and if there are no subsequent errors in the RX FIFO.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTIONS Parity Error Indicator [2] This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU reads the contents of the LSR. PEI Overrun Error Indicator [1] An overrun error will occur only after the RX FIFO is full and the next character has been completely received in the shift register. The character in the shift register is overwritten, but it is not transferred to the RX FIFO.
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:6] Reserved [5] DSR# [4:2] Reserved [1] DDSR [0] Reserved - Complement version of data set ready (DSR#) input (This bit is selected by IP) DSR# State Change (This bit is selected by IP) This bit is set whenever DSR# input has changed state, and it will be reset if the CPU reads the MSR. - Whenever any of MSR [3:0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing MSR is a null operation (not suggested).
W90N745CD/W90N745CDG 6.10.6 High speed UART Controller The High Speed Universal Asynchronous Receiver/Transmitter (HS_UART) performs a serial-toparallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from the CPU.
W90N745CD/W90N745CDG Continued.
W90N745CD/W90N745CDG HSUART Transmit Holding Register (HSUART_THR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_THR 0x00 W Transmit Holding Register (DLAB = 0) Undefined 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 8-bit Transmitted Data BITS DESCRIPTIONS [7:0] By writing to this register, the UART will send out an 8-bit data through the SOUT pin (LSB first).
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:5] Reserved ICE debug mode acknowledge enable 0 = When DBGACK is high, the UART receiver time-out clock will be held 1 = No matter what DBGACK is high or not, the UART receiver timerout clock will not be held [4] nDBGACK_EN [3] MSIE MODEM Status Interrupt (Irpt_MOS) Enable 0 = Mask off Irpt_MOS 1 = Enable Irpt_MOS [2] RLSIE Receive Line Status Interrupt (Irpt_RLS) Enable 0 = Mask off Irpt_RLS 1 = Enable Irpt_RLS [1] THREIE Transmit Holding Register
W90N745CD/W90N745CDG BITS DESCRIPTIONS [31:8] Reserved - [7:0] Baud Rate Divisor (Low Byte) The low byte of the baud rate divider HSUART Divisor Latch (High Byte) Register (HSUART_DLM) REGISTER OFFSET HSUART_DLM 0x04 31 30 R/W DESCRIPTION RESET VALUE R/W Divisor Latch Register (MS) (DLAB = 1) 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Baud Rate Divider (High Byte) BITS DESCRIPTIONS
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 FMES 5 RFTLS 4 DMS BITS [31:8] IID NIP DESCRIPTIONS Reserved FIFO Mode Enable Status [7] FMES This bit indicates whether the FIFO mode is enabled or not. Since the FIFO mode is always enable, this bit always shows the logical 1 when CPU is reading this register.
W90N745CD/W90N745CDG Interrupt Control Functions INTERRUPT RESET CONTROL IIR [3:0] PRIORITY INTERRUPT TYPE INTERRUPT SOURCE ---1 -- None 0110 Highest Receiver Line Status (Irpt_RLS) None Overrun error, parity error, framing error, or break interrupt 0100 Second Received Data Available (Irpt_RDA) Receiver FIFO threshold level is reached Receiver FIFO drops below the threshold level Second Receiver FIFO Timeout (Irpt_TOUT) Receiver FIFO is nonempty and no activities are occurred in the rece
W90N745CD/W90N745CDG BITS [31:8] DESCRIPTIONS Reserved RX FIFO Interrupt (Irpt_RDA) Trigger Level [7:4] [3] RFITL DMS RFITL Irpt_RDA Trigger Level (Bytes) 0000 01 0001 04 0010 08 0011 14 0100 30 0101 46 0110 62 others 62 DMA Mode Select The DMA function is not implemented in this version. TX FIFO Reset [2] TFR Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO. The TX FIFO becomes empty (TX pointer is reset to 0) after such reset.
W90N745CD/W90N745CDG HSUART Line Control Register (HSUART_LCR) REGISTER OFFSET HSUART_LCR 0x0C R/W DESCRIPTION RESET VALUE R/W Line Control Register BITS 0x0000_0000 DESCRIPTIONS [31:8] Reserved [7] DLAB [6] BCB [5] SPE [4] EPE [3] PBE [2] NSB Divider Latch Access Bit 0 = It is used to access RBR, THR or IER. 1 = It is used to access Divisor Latch Registers {DLL, DLM}.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 3 2 DLAB BCB SPE EPE PBE NSB WLS HSUART Modem Control Register (HSUART_MCR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_MCR 0x10 R/W Modem Control Register (Optional) 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RTS Reserved Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved
W90N745CD/W90N745CDG Continued. BITS [3:2] DESCRIPTIONS Reserved Complement version of RTS# (Request-To-Send) signal [1] Writing 0x00 to MCR, RTS# bit are set to logic 1’s; RTS# Writing 0x0f to MCR, RTS# bit are reset to logic 0’s.
W90N745CD/W90N745CDG Continued. BITS DESCRIPTIONS Transmitter Holding Register Empty 0 = THR is not empty. [5] THRE 1 = THR is empty. THRE is set when the last data word of TX FIFO is transferred to Transmitter Shift Register (TSR). The CPU resets this bit when the THR (or TX FIFO) is loaded. This bit also causes the UART to issue an interrupt (Irpt_THRE) to the CPU when IER [1]=1.
W90N745CD/W90N745CDG HSUART Modem Status Register (HSUART_MSR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_MSR 0x18 R MODEM Status Register (Optional) 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 CTS# Reserved BITS Reserved DCTS DESCRIPTIONS [31:5] Reserved [4] CTS# [3:1] Reserved [0] 4 DCTS Complement version of clear to send (CTS#) input (This bit is selected by IP)
W90N745CD/W90N745CDG HSUART Time Out Register (HSUART_TOR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_TOR 0x1C R/W Time Out Register 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 TOIE TOIC BITS DESCRIPTIONS [31:8] Reserved [7] TOIE Time Out Interrupt Enable The feature of receiver time out interrupt is enabled only when TOR [7] = IER[0] = 1.
W90N745CD/W90N745CDG 6.11 Timer/Watchdog Controller 6.11.1 General Timer Controller The timer module includes two channels, TIMER0 and TIMER1, which allow you to easily implement a counting scheme for use. The timer can perform functions like frequency measurement, event counting, interval measurement, clock generation, delay timing, and so on. The timer possesses features such as adjustable resolution, programmable counting period, and detailed information.
W90N745CD/W90N745CDG 31 30 29 nDBGACK_EN CEN IE 23 22 21 28 27 26 25 24 CRST CACT Reserved 19 18 17 16 11 10 9 8 3 2 1 0 MODE[1:0] 20 Reserved 15 14 13 12 Reserved 7 6 5 4 PRESCALE[7:0] BITS DESCRIPTIONS ICE debug mode acknowledge enable [31] nDBGACK_EN 0 = When DBGACK is high, the TIMER counter will be held 1 = No matter DBGACK is high or not, the TIMER counter will not be held Counter Enable [30] CEN 0 = Stops/Suspends counting 1 = Starts counting Interrupt E
W90N745CD/W90N745CDG Continued BITS DESCRIPTIONS Counter Reset Set this bit will reset the TIMER counter, and also force CEN to 0. [26] CRST 0 = No effect. 1 = Reset Timer’s prescale counter, internal 24-bit counter and CEN. Timer is in Active [25] CACT This bit indicates the counter status of timer. 0 = Timer is not active. 1 = Timer is in active. [24:8] Reserved Reserved Prescale [7:0] PRESCALE Clock input is divided by PRESCALE+1 before it is fed to the counter.
W90N745CD/W90N745CDG BITS [31:24] [23:0] DESCRIPTIONS Reserved TIC Reserved Timer Initial Count This is a 24-bit value representing the initial count. Timer will reload this value whenever the counter is decremented to zero. NOTE1: Never write 0x0 in TIC, or the core will run into unknown state. NOTE2: No matter CEN is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.
W90N745CD/W90N745CDG Timer Interrupt Status Register (TISR) REGISTER TISR 31 ADDRESS R/W 0xFFF8_1018 R/W 30 DESCRIPTION RESET VALUE Timer Interrupt Status Register 29 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 TIF1 TIF0 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 4 3 Reserved BITS DESCRIPTIONS Timer Interrupt Flag 1 This bit indicates the interrupt status of Timer channel 1.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 WTE WTIE 5 4 WTIS BITS [31:11] WTCLK nDBGACK_EN WTTME 3 2 1 0 WTIF WTRF WTRE WTR DESCRIPTIONS Reserved Reserved Watchdog Timer Clock [10] WTCLK This bit is used for deciding whether the Watchdog timer clock input is divided by 256 or not. Clock source of Watchdog timer is Crystal input.
W90N745CD/W90N745CDG Continued BITS DESCRIPTIONS Watchdog Timer Interrupt Enable [6] WTIE 0 = Disable the Watchdog timer interrupt 1 = Enable the Watchdog timer interrupt Watchdog Timer Interval Select These two bits select the interval for the Watchdog timer. No matter which interval is chosen, the reset timeout is always occurred 512 WDT clock cycles later than the interrupt timeout.
W90N745CD/W90N745CDG Continued BITS DESCRIPTIONS Watchdog Timer Reset Enable [1] WTRE Setting this bit will enable the Watchdog timer reset function. 0 = Disable Watchdog timer reset function 1 = Enable Watchdog timer reset function Watchdog Timer Reset [0] WTR This bit brings the Watchdog timer into a known state. It helps reset the Watchdog timer before a timeout situation occurring. Failing to set WTR before timeout will initiates an interrupt if WTIE is set.
W90N745CD/W90N745CDG 6.12 Advanced Interrupt Controller An interrupt temporarily changes the sequence of program execution to react to a particular event such as power failure, watchdog timer timeout, transmit/receive request from Ethernet MAC Controller, and so on. The ARM7TDMI processor provides two modes of interrupt, the Fast Interrupt (FIQ) mode for critical session and the Interrupt (IRQ) mode for general purpose. The IRQ exception is occurred when the nIRQ input is asserted.
W90N745CD/W90N745CDG 6.12.1 Interrupt Sources Table 6.12.
W90N745CD/W90N745CDG AIC Functional Description Hardware Interrupt Vectoring The hardware interrupt vectoring can be used to shorten the interrupt latency. If not used, priority determination must be carried out by software. When the Interrupt Priority Encoding Register (AIC_IPER) is read, it will return an integer representing the channel that is active and having the highest priority.
W90N745CD/W90N745CDG Interrupt Masking Each interrupt source, including FIQ, can be enabled or disabled individually by using the command registers AIC_MECR and AIC_MDCR. The status of interrupt mask can be read in the read only register AIC_IMR. A disabled interrupt doesn’t affect the servicing of other interrupts.
W90N745CD/W90N745CDG ACTION NORMAL MODE Calculate active interrupt ICE/DEBUG MODE Read AIC_IPER Read AIC_IPER Determine and return the vector of the active interrupt Read AIC_IPER Read AIC_IPER Push on internal stack the current priority level Read AIC_IPER Write AIC_IPER Acknowledge the interrupt (Note 1) Read AIC_IPER Write AIC_IPER No effect (Note 2) Read AIC_IPER Notes: y nIRQ de-assertion and automatic interrupt clearing if the source is programmed as level sensitive.
W90N745CD/W90N745CDG AIC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR16 0xFFF8_2040 R/W Source Control Register 16 0x0000_0047 AIC_SCR17 0xFFF8_2044 R/W Source Control Register 17 0x0000_0047 AIC_SCR18 0xFFF8_2048 R/W Source Control Register 18 0x0000_0047 AIC_SCR19 0xFFF8_204C R/W Source Control Register 19 0x0000_0047 AIC_SCR20 0xFFF8_2050 R/W Source Control Register 20 0x0000_0047 AIC_SCR21 0xFFF8_2054 R/W Source Control Register 21 0x0000_0047 AIC
W90N745CD/W90N745CDG AIC Source Control Registers (AIC_SCR1 ~ AIC_SCR31) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR1 0xFFF8_2004 R/W Source Control Register 1 0x0000_0047 AIC_SCR2 0xFFF8_2008 R/W Source Control Register 2 0x0000_0047 yyy yyy yyy yyy yyy AIC_SCR28 0xFFF8_2070 R/W Source Control Register 28 0x0000_0047 AIC_SCR29 0xFFF8_2074 R/W Source Control Register 29 0x0000_0047 AIC_SCR30 0xFFF8_2078 R/W Source Control Register 30 0x0000_0047 AIC_SCR31 0xFFF8_207C R/W S
W90N745CD/W90N745CDG Continued BITS [5:3] DESCRIPTIONS Reserved Reserved Priority Level [2:0] Every interrupt source must be assigned a priority level during initiation. Among them, priority level 0 has the highest priority and priority level 7 the lowest. Interrupt sources with priority level 0 are promoted to FIQ. Interrupt sources with priority level other than 0 belong to IRQ. For interrupt sources of the same priority level that located in the lower channel number has higher priority.
W90N745CD/W90N745CDG AIC Interrupt Active Status Register (AIC_IASR) REGISTER ADDRESS R/W AIC_IASR 0xFFF8_2104 R DESCRIPTION RESET VALUE 0x0000_0000 Interrupt Active Status Register 31 30 29 28 27 26 25 24 IAS31 IAS30 IAS29 IAS28 IAS27 IAS26 IAS25 IAS24 23 22 21 20 19 18 17 16 IAS23 IAS22 IAS21 IAS20 IAS19 IAS18 IAS17 IAS16 15 14 13 12 11 10 9 8 IAS15 IAS14 IAS13 IAS12 IAS11 IAS10 IAS9 IAS8 7 6 5 4 3 2 1 0 IAS7 IAS6 IAS5 IAS4 IAS3 IAS2
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 IS31 IS30 IS29 IS28 IS27 IS26 IS25 IS24 23 22 21 20 19 18 17 16 IS23 IS22 IS21 IS20 IS19 IS18 IS17 IS16 15 14 13 12 11 10 9 8 IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8 7 6 5 4 3 2 1 0 IS7 IS6 IS5 IS4 IS3 IS2 IS1 RESERVED BITS DESCRIPTIONS This register identifies those interrupt channels whose are both active and enabled.
W90N745CD/W90N745CDG BITS [6:2] DESCRIPTIONS Vector When the AIC generates the interrupt, VECTOR represents the interrupt channel number that is active, enabled, and has the highest priority. If the representing interrupt channel possesses a priority level 0, then the interrupt asserted is FIQ; otherwise, it is IRQ. The value of VECTOR is copied to the register AIC_ISNR thereafter by the AIC. This register was restored a value 0 after it was read by the interrupt handler.
W90N745CD/W90N745CDG AIC Interrupt Mask Register (AIC_IMR) REGISTER ADDRESS R/W AIC_IMR 0xFFF8_2114 R DESCRIPTION RESET VALUE 0x0000_0000 Interrupt Mask Register 31 30 29 28 27 26 25 24 IM31 IM30 IM29 IM28 IM27 IM26 IM25 IM24 23 22 21 20 19 18 17 16 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16 15 14 13 12 11 10 9 8 IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 7 6 5 4 3 2 1 0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 RESERVED BITS DESCRIPTIONS [31:1] IM x [
W90N745CD/W90N745CDG The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted interrupt is FIQ or IRQ. If both IRQ and FIQ are equal to 0, it means there is no interrupt occurred. BITS [31:2] DESCRIPTIONS Reserved Reserved IRQ [1]: Interrupt Request [1] IRQ 0 = nIRQ line is inactive. 1 = nIRQ line is active. FIQ [0]: Fast Interrupt Request [0] FIQ 0 = nFIQ line is inactive.
W90N745CD/W90N745CDG AIC Mask Disable Command Register (AIC_MDCR) REGISTER ADDRESS R/W AIC_MDCR 0xFFF8_2124 W DESCRIPTION RESET VALUE Mask Disable Command Register Undefined 31 30 29 28 27 26 25 24 MDC31 MDC30 MDC29 MDC28 MDC27 MDC26 MDC25 MDC24 23 22 21 20 19 18 17 16 MDC23 MDC22 MDC21 MDC20 MDC19 MDC18 MDC17 MDC16 15 14 13 12 11 10 9 8 MDC15 MDC14 MDC13 MDC12 MDC11 MDC10 MDC9 MDC8 7 6 5 4 3 2 1 0 MDC7 MDC6 MDC5 MDC4 MDC3 MDC2 MDC1 RE
W90N745CD/W90N745CDG BITS [31:1] DESCRIPTIONS When the W90N745 is under debugging or verification, software can activate any interrupt channel by setting the corresponding bit in this register. This feature is useful in hardware verification or software debugging. SSCx SSCx: Source Set Command 0 = No effect.
W90N745CD/W90N745CDG AIC End of Service Command Register (AIC_EOSCR) REGISTER ADDRESS R/W W AIC_EOSCR 0xFFF8_2130 DESCRIPTION RESET VALUE End of Service Command Register Undefined 31 30 29 28 27 26 25 24 --- --- --- --- --- --- --- --- 23 22 21 20 19 18 17 16 --- --- --- --- --- --- --- --- 15 14 13 12 11 10 9 8 --- --- --- --- --- --- --- --- 7 6 5 4 3 2 1 0 --- --- --- --- --- --- --- --- BITS [31:0] DESCRIPTIONS EOSCR This regis
W90N745CD/W90N745CDG BITS [31:1] [0] DESCRIPTIONS Reserved TEST Reserved This register indicates whether AIC_IPER will be cleared or not after been read. If bit0 of AIC_TEST has been set, ICE or debug monitor can read AIC_IPER for verification and the AIC_IPER will not be cleared automatically. Write access to the AIC_IPER will perform the interrupt stacking in this mode. TEST: ICE/Debug mode 0 = normal mode. 1 = ICE/Debug mode.
W90N745CD/W90N745CDG 6.13 General-Purpose Input/Output The General-Purpose Input/Output (GPIO) module possesses 31 pins and serves multiple function purposes. Each port can be configured by software to meet various system configurations and design requirements. Software must configure each pin before starting the main program.
W90N745CD/W90N745CDG Table 6.13.
W90N745CD/W90N745CDG 6.13.
W90N745CD/W90N745CDG GPIO Register Description, continued. REGISTER ADDRESS R/W GPIO_DATAIN5 0xFFF8_305C R GPIO_DBNCECON 0xFFF8_3070 R/W GPIO_XICFG 0xFFF8_3074 R/W GPIO_XISTATUS 0xFFF8_3078 R/W DESCRIPTION RESET VALUE GPIO Port5 Data Input Register GPIO Input Debounce Control Register Extend Interrupt Configure Register Extend Interrupt Status Register 0xXXXX_XXXX 0x0000_0000 0xXXXX_XXX0 0xXXXX_XXX0 6.13.
W90N745CD/W90N745CDG Continued 11 PT0CFG2 10 NAME TYPE NAME 01 TYPE NAME 00 TYPE NAME TYPE O GPIO2 I/O AC97DATAO PORT0_2 DSR3 I PWM1 O or I²SDATAO 11 PT0CFG3 10 NAME TYPE NAME 01 TYPE NAME 00 TYPE NAME TYPE O GPIO3 I/O AC97SYNC PORT0_3 TXD3 O PWM2 O or I²SLRCLK 11 PT0CFG4 10 NAME PORT0_4 TYPE RXD3 O NAME PWM3 01 TYPE O 00 NAME TYPE AC97BITCLK I or I²SBITCLK NAME TYPE GPIO4 I/O O GPIO Port0 Direction Register (GPIO_DIR0) REGISTER ADDRESS GPIO_
W90N745CD/W90N745CDG BITS DESCRIPTION [31:20] RESERVED [19:16] PUPEN0 [15:5] RESERVED [4:0] GPIO3 -GPIO0 port pin internal pull-up resister enable There are 4 bits for this register, the corresponding bit is set to “1” will enable pull-up resister on IO pin. 1 = enable 0 = disable After power on the pull-up resisters are disabled. NOTE: GPIO4 is used as AC97 BITCLK input, an IO pad with Schmitt trigger input buffer PDB04SDGZ is implemented for this pin.
W90N745CD/W90N745CDG GPIO Port0 Data Input Register (GPIO_DATAIN0) REGISTER GPIO_DATAIN0 31 ADDRESS R/W 0xFFF8_300C R/W 30 29 DESCRIPTION RESET VALUE GPIO port0 data input register 28 27 0xXXXX_XXXX 26 25 24 18 17 16 10 9 8 2 1 0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 RESERVED DATAIN0 BITS DESCRIPTION [31:5] RESERVED [4:0] DATAIN0 PORT0 data input value The DATAIN0 indicates the status of each GPIO0~GPIO4 port pin regardless of it
W90N745CD/W90N745CDG *In the following pin definition, mark with shading is default function.
W90N745CD/W90N745CDG Continued. [1:0] GPIO19 ~ GPIO18 output mode enable 1 = enable 0 = disable NOTE: Output mode enable bits are valid only when bit PT1CFG1-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit.
W90N745CD/W90N745CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 RESERVED DATAIN1[1:0] BITS DESCRIPTION [31:2] RESERVED [1:0] DATAIN1 Port1 input data register The DATAIN1 indicates the status of each GPIO19~GPIO18 pin regardless of its operation mode. The reserved bits are read as 0s.
W90N745CD/W90N745CDG PT2CFG1 PORT2_1 PT2CFG2 PORT2_2 PT2CFG3 PORT2_3 PT2CFG4 PORT2_4 PT2CFG5 PORT2_5 PT2CFG6 PORT2_6 PT2CFG7 PORT2_7 PT2CFG8 PORT2_8 PT2CFG9 PORT2_9 11 Name 10 Type RESERVED 11 Name Type 11 RESERVED 11 Name Type 11 Type 11 Type 11 Type 11 KPCOL1 I PHY_CRSDV I GPIO21 I/O 01 Type 11 Type Name Type Name Type KPCOL2 I PHY_RXD[0] I GPIO22 I/O 01 RESERVED 00 Name Type Name Type Name Type KPCOL3 I PHY_RXD[1] I GPIO23 I/O 01 00 Name Type Nam
W90N745CD/W90N745CDG GPIO Port2 Direction Register (GPIO_DIR2) REGISTER ADDRESS GPIO_DIR2 31 R/W 0xFFF8_3024 30 R/W 29 DESCRIPTION GPIO port2 in/out direction control and pull-up enable register 28 27 26 RESERVED 23 22 21 RESET VALUE 25 0x0000_0000 24 PUPEN2[9:8] 20 19 18 17 16 10 9 8 PUPEN2[7:0] 15 14 13 12 11 RESERVED 7 6 5 OMDEN2[9:8] 4 3 2 1 0 OMDEN2[7:0] BITS [31:26] DESCRIPTION RESERVED - [25:16] PUPEN2 GPIO29 ~ GPIO20 port pin internal pull-up resist
W90N745CD/W90N745CDG PGPIO Port2 Data Output Register (GPIO_DATAOUT2) REGISTER GPIO_DATAOUT2 31 ADDRESS R/W 0xFFF8_3028 R/W 30 29 DESCRIPTION RESET VALUE GPIO port2 data output register 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 DATAOUT2[9:8] 4 3 2 1 0 DATAOUT2[7:0] BITS [31:10] DESCRIPTION RESERVED PORT2 data output value [9:0] Writing data to this register will reflect the data value on the corre
W90N745CD/W90N745CDG BITS [31:10] DESCRIPTION RESERVED Port2 input data register [9:0] The DATAIN2 indicates the status of each GPIO18~GPIO27 pin regardless of its operation mode. The reserved bits will be read as 0s.
W90N745CD/W90N745CDG GPIO Port4 Direction Register (GPIO_DIR4) REGISTER ADDRESS GPIO_DIR4 31 R/W 0xFFF8_3044 30 DESCRIPTION GPIO port4 in/out direction control and pull-up enable register R/W 29 28 27 RESERVED 23 22 21 RESET VALUE 26 PUPEN4[ 10] 20 19 0x0000_0000 25 24 RESERVED 18 17 16 10 9 8 RESERVED 15 14 13 12 11 RESERVED 7 6 5 OMDEN4 [10] 4 3 2 RESERVED 1 0 RESERVED BITS [31:27] DESCRIPTION RESERVED - [26] PUPEN4 GPIO28 pin internal pull-up resister ena
W90N745CD/W90N745CDG GPIO Port4 Data Output Register (GPIO_DATAOUT4) REGISTER GPIO_DATAOUT4 31 ADDRESS R/W 0xFFF8_3048 R/W 30 29 28 DESCRIPTION RESET VALUE GPIO port4 data output register 27 0x0000_0000 26 25 24 18 17 16 10 9 8 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 DATAOUT4[10 ] 5 4 3 2 RESERVED 1 0 RESERVED BITS [31:11] DESCRIPTION RESERVED PORT4 data output value [10] DATAOUT4 Writing data to this register will reflect the data value o
W90N745CD/W90N745CDG BITS [31:11] DESCRIPTION RESERVED Port4 input data register [10:0] DATAIN4 The DATAIN4 indicates the status of GPIO28 pin regardless of its operation mode.
W90N745CD/W90N745CDG PT5CFG3 PORT5_3 PT5CFG4 PORT5_4 11 Name 10 Type Name 00 01 Type RESERVED RESERVED 11 10 Name Type Name Type RXD1 I GPIO8 I/O 01 00 Name Type Name Type Name Type Name Type PS2CLK O CTS1 I TXD2 IO GPIO9 I/O Continued PT5CFG5 PORT5_5 PT5CFG6 PORT5_6 PT5CFG7 PORT5_7 PT5CFG8 PORT5_8 PT5CFG9 PORT5_9 PT5CFG10 PORT5_10 11 10 01 00 Name Type Name Type Name Type Name Type PS2DATA I/O RTS1 IO RXD2 I GPIO10 I/O 11 10 01 00 Name T
W90N745CD/W90N745CDG 11 PT5CFG11 Name PORT5_11 10 Type Name RESERVED Name PORT5_12 Type RESERVED 11 PT5CFG12 01 Name Type Name Type nIRQ0 I GPIO16 I/O 10 01 00 Name Type Name Type Name Type USBOVCUR I nIRQ1 I GPIO17 I/O Type RESERVED 00 GPIO Port5 Direction Register (GPIO_DIR5) REGISTER GPIO_DIR5 31 ADDRESS 0xFFF8_3054 30 29 R/W DESCRIPTION GPIO port5 in/out direction control and pull-up enable register R/W 28 27 RESERVED 23 22 RESET VALUE 26 0x0000_0
W90N745CD/W90N745CDG GPIO Port5 Data Output Register (GPIO_DATAOUT5) REGISTER GPIO_DATAOUT5 31 ADDRESS R/W 0xFFF8_3058 R/W 30 29 DESCRIPTION RESET VALUE GPIO port5 data output register 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 1 0 RESERVED 23 22 21 20 RESERVED 15 14 13 12 RESERVED 7 6 DATAOUT5[12:8] 5 4 3 2 DATAOUT5[7:0] BITS [31:13] DESCRIPTION RESERVED PORT5 data output value [12:0] Writing data to this register will reflect the data value on the corre
W90N745CD/W90N745CDG BITS [31:13] DESCRIPTION RESERVED Port5 input data register [12:0] The DATAIN5 indicates the status of each GPIO17~GPIO5 pin regardless of its operation mode. The reserved bits will be read as 0s.
W90N745CD/W90N745CDG GPIO Interrupt Configuration Register (GPIO_XICFG) REGISTER ADDRESS GPIO_XICFG 31 0xFFF8_3074 30 R/W R/W 29 DESCRIPTION RESET VALUE Extend interrupt configure register 0xXXXX_XX00 28 27 26 25 24 18 17 16 10 9 8 3 2 1 0 EnIRQ2 DBE2 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 EnIRQ3 DBE3 5 4 ISTYPE3 BITS [31:8] ISTYPE2 DESCRIPTION RESERVED Enable nIRQ3 Setting this bit 1 to enable nIRQ3.
W90N745CD/W90N745CDG Continued BITS [3] [2] DESCRIPTION EnIRQ2 Enable nIRQ2 Setting this bit 1 to enable nIRQ2 1 = Enable nIRQ2 0 = Disable nIRQ2 The AIC interrupt channel 31 is reserved for nIRQ3 and nIRQ2 (wire-OR), if this bit is set and nIRQ2 occur, then it will send an interrupt request signal into AIC module.
W90N745CD/W90N745CDG GPIO Interrupt Status Register (GPIO_XISTATUS) REGISTER GPIO_XISTATUS 31 ADDRESS R/W 0xFFF8_3078 R/W 30 29 28 DESCRIPTION RESET VALUE Extend interrupt status register 27 0xXXXX_XX00 26 25 24 18 17 16 10 9 8 2 1 0 nIRQ3 nIRQ2 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 RESERVED BITS [31:2] DESCRIPTION RESERVED Interrupt 3 status [1] nIRQ3 When interrupt input is detected with ISTYPE3 triggered condition, this flag wi
W90N745CD/W90N745CDG 6.14 I2C Interface I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Serial, 8-bit oriented bi-directional data transfers can be made up to 100 kbit/s in Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.
W90N745CD/W90N745CDG 6.14.1 I2C Protocol Normally, a standard communication consists of four parts: 1) START or Repeated START signal generation 2) Slave address transfer 3) Data transfer 4) STOP signal generation SCL 1 2 SDA A6 A5 7 8 9 1 2 3-7 8 9 A0 R/W ACK D7 D6 D5 - D1 D0 NACK ACK P S or Sr A4 - A1 MSB LSB MSB P or Sr LSB Sr Figure 6.14.
W90N745CD/W90N745CDG START or Repeated START signal When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal, usually referred to as the S-bit, is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH. The START signal denotes the beginning of a new data transfer. A Repeated START (Sr) is a START signal without first generating a STOP signal.
W90N745CD/W90N745CDG Data Transfer Once successful slave addressing has been achieved, the data transfer can proceed on a byte-bybyte basis in the direction specified by the RW bit sent by the master. Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a Not Acknowledge (NACK), the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle.
W90N745CD/W90N745CDG 6.14.2 I2C Serial Interface Control Registers Map R: read only, W: write only, R/W: both read and write NOTE1: The reset value of I2C_WR0/1 is 0x3F only when SCR, SDR and SER are connected to pull high resistor.
W90N745CD/W90N745CDG BITS [31:12] DESCRIPTIONS Reserved 2 [11] [10] I C_RxAC K 2 I C_BUSY Reserved Received Acknowledge From Slave (Read only) This flag represents acknowledge from the addressed slave. 0 = Acknowledge received (ACK). 1 = Not acknowledge received (NACK). I2C Bus Busy (Read only) 0 = After STOP signal detected. 1 = After START signal detected. I C_AL Arbitration Lost (Read only) This bit is set when the I2C core lost arbitration.
W90N745CD/W90N745CDG I2C Prescale Register 0/1 (I2C_DIVIDER 0 /1) REGISTER 2 I C_DIVIDER0 2 I C_DIVIDER1 31 ADDRESS 0xFFF8_6004 0xFFF8_6104 30 29 R/W DESCRIPTION R/W RESET VALUE 2 0x0000_0000 2 0x0000_0000 I C Clock Prescale Register 0 R/W I C Clock Prescale Register 1 28 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 DIVIDER[15:8] 7 6 5 4 3 DIVIDER[7:0] BITS DESCRIPTIONS Clock Prescale Register [15:0] DIVIDER It is use
W90N745CD/W90N745CDG I2C Command Register 0/1 (I2C_CMDR 0/1) REGISTER ADDRESS 2 R/W DESCRIPTION RESET VALUE 2 I C_CMDR0 0xFFF8_6008 R/W I C Command Register 0 0x0000_0000 I2C_CMDR1 0xFFF8_6108 R/W I2C Command Register 1 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 4 3 2 1 0 START STOP READ WRITE ACK Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 Reserved 2 NOTE: Software can write this register only when I C_EN = 1.
W90N745CD/W90N745CDG I2C Software Mode Register 0/1(I2C_SWR 0/1) REGISTER 2 ADDRESS R/W DESCRIPTION RESET VALUE 2 I C_SWR0 0xFFF8_600C R/W I C Software Mode Control Register 0 0x0000_003F I2C_SWR1 0xFFF8_610C R/W I2C Software Mode Control Register 1 0x0000_003F 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 Reserved 5 4 3 2 1 0 Reserved SDR SCR Reserved SDW SCW 2 2 Note: This register is used as softw
W90N745CD/W90N745CDG I2C Data Receive Register 0/1 (I2C_RxR 0/1) REGISTER 2 OFFSET R/W DESCRIPTION RESET VALUE 2 I C_RXR0 0xFFF8_6010 R I C Data Receive Register 0 0x0000_0000 I2C_RXR1 0xFFF8_6110 R I2C Data Receive Register 1 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Rx [7:0] BITS DESCRIPTIONS [31:8] Reserved [7:0] Rx Reserved Data Receive Register The last byte received
W90N745CD/W90N745CDG I2C Data Transmit Register 0/1 (I2C_TxR 0/1) REGISTER 2 ADDRESS R/W DESCRIPTION RESET VALUE 2 I C_TXR0 0xFFF8_6014 R/W I C Data Transmit Register 0x0000_0000 I2C_TXR1 0xFFF8_6114 R/W I2C Data Transmit Register 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Tx [31:24] 23 22 21 20 Tx [23:16] 15 14 13 12 Tx [15:8] 7 6 5 4 Tx [7:0] BITS DESCRIPTIONS Data Transmit Register The I2C core used 32-bit transmit buffer and provide mu
W90N745CD/W90N745CDG 6.15 Universal Serial Interface The USI is a synchronous serial interface performs a serial-to-parallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from CPU. It can generate an interrupt signal when data transfer is finished and can be cleared by writing 1 to the interrupt flag.
W90N745CD/W90N745CDG 6.15.1 USI Timing Diagram The timing diagram of USI is shown as following. mw_ss_o mw_sclk_o mw_so_o MSB (Tx[7]) Tx[6] Tx[5] Tx[4] Tx[3] Tx[2] Tx[1] LSB (Tx[0]) mw_si_i MSB (Rx[7]) Rx[6] Rx[5] Rx[4] Rx[3] Rx[2] Rx[1] LSB (Rx[0]) CNTRL[LSB]=0, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08, CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0, SSR[SS_LVL]=0 Figure 6.15.
W90N745CD/W90N745CDG 6.15.
W90N745CD/W90N745CDG USI_Control and Status Register (USI_CNTRL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_CNTRL 0xFFF8_6200 R/W USI Control and Status Register 31 30 29 28 0x0000_0004 27 26 25 24 19 18 17 16 IE IF 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 SLEEP 7 6 5 11 10 Reserved LSB 3 2 1 0 Tx_NEG Rx_NEG GO_BUSY 4 Tx_BIT_LEN BITS Tx_NUM DESCRIPTIONS [31:18] Reserved [17] IE Interrupt Enable 0 = Disable USI Interrupt.
W90N745CD/W90N745CDG Continued BITS [11] DESCRIPTIONS Reserved Reserved LSB Send LSB First 0 = The MSB is transmitted/received first (which bit in TxX/RxX register that is depends on the Tx_BIT_LEN field in the CNTRL register). 1 = The LSB is sent first on the line (bit TxX[0]), and the first bit received from the line will be put in the LSB position in the Rx register (bit RxX[0]).
W90N745CD/W90N745CDG USI Divider Register (USI_DIVIDER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_Divider 0xFFF8_6204 R/W USI Clock Divider Register 31 30 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 DIVIDER[15:8] 7 6 5 4 3 DIVIDER[7:0] BITS DESCRIPTIONS Clock Divider Register The value in this field is the frequency divider of the system clock pclk to generate the serial clock on the output mw_sclk_o.
W90N745CD/W90N745CDG USI Slave Select Register (USI_SSR) REGISTER USI_SSR 31 ADDRESS R/W DESCRIPTION RESET VALUE 0xFFF8_6208 R/W USI Slave Select Register 30 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ASS SS_LVL Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved BITS [3] [2] SSR[1:0] DESCRIPTIONS ASS SS_LVL Automatic Slave Select 0 = If this bit is cleared, slave select signals are asserted and deasserted by setting and clear
W90N745CD/W90N745CDG USI Data Receive Register 0/1/2/3 (USI_Rx0/1/2/3) REGISTER ADDRESS R/W USI_RX0 0xFFF8_6210 R USI Data Receive Register 0 0x0000_0000 USI_RX1 0xFFF8_6214 R USI Data Receive Register 1 0x0000_0000 USI_RX2 0xFFF8_6218 R USI Data Receive Register 2 0x0000_0000 USI_RX3 0xFFF8_621C R USI Data Receive Register 3 0x0000_0000 31 30 29 DESCRIPTION 28 RESET VALUE 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Rx [31:24] 23 22 21 20 Rx [23:16] 15 14 13
W90N745CD/W90N745CDG Data Transmit Register 0/1/2/3 (Tx0/1/2/3) REGISTER ADDRESS R/W USI_TX0 0xFFF8_6210 W USI Data Transmit Register 0 0x0000_0000 USI_TX1 0xFFF8_6214 W USI Data Transmit Register 1 0x0000_0000 USI_TX2 0xFFF8_6218 W USI Data Transmit Register 2 0x0000_0000 USI_TX3 0xFFF8_621C W USI Data Transmit Register 3 0x0000_0000 31 30 29 DESCRIPTION 28 RESET VALUE 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Tx [31:24] 23 22 21 20 Tx [23:16] 15 14 13 12
W90N745CD/W90N745CDG 6.16 PWM The W90N745 have 4 channels PWM timers. They can be divided into two groups. Each group has 1 Prescaler, 1 clock divider, 2 clock selectors, 2 16-bit counters, 2 16-bit comparators, 1 Dead-Zone generator. They are all driven by PCLK (80 MHz). Each channel can be used as a timer and issue interrupt independently. Two channels PWM timers in one group share the same prescaler. Clock divider provides each channel with 5 clock sources (1, 1/2, 1/4, 1/8, 1/16).
W90N745CD/W90N745CDG 6.16.1 PWM Double Buffering and Reload Automatically W90N745 PWM Timers have a double buffering function, enabling the reload value changed for next timer operation without stopping current timer operation. Although new timer value is set, current timer operation still operate successfully. The counter value can be written into PWM_CNR0, PWM_CNR1, PWM_CNR2, PWM_CNR3 and current counter value can be read from PWM_PDR0, PWM_PDR1, PWM_PDR2, PWM_PDR3.
W90N745CD/W90N745CDG 6.16.3 Dead Zone Generator W90N745 PWM is implemented with Dead Zone generator. They are built for power device protection. This function enables generation of a programmable time gap at the rising of PWM output waveform. User can program PWM_PPR [31:24] and PWM_PPR [23:16] to determine the Dead Zone interval. Dead zone generator operation PWM_out1 PWM_out1_n PWM_out1_DZ PWM_out1_n_DZ Dead zone interval 6.16.4 PWM Timer Start Procedure 1. Setup clock selector (PWM_CSR) 2.
W90N745CD/W90N745CDG 6.16.
W90N745CD/W90N745CDG PWM Prescaler Register (PWM_PPR) REGISTER ADDRESS PWM_PPR 0xFFF8_7000 31 30 R/W DESCRIPTION RESET VALUE R/W PWM Prescaler Register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DZI1 23 22 21 20 DZI0 15 14 13 12 CP1 7 6 5 4 CP0 BITS [31:24] DESCRIPTIONS DZI1 DZI1: Dead zone interval register 1, these 8-bit determine dead zone length. The 1 unit time of dead zone length is received from clock selector 2.
W90N745CD/W90N745CDG PWM Clock Select Register (PWM_CSR) REGISTER ADDRESS PWM_CSR 0xFFF8_7004 31 30 R/W DESCRIPTION RESET VALUE R/W PWM Clock Select Register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 Reserved 13 12 CSR3 7 6 Reserved 5 CSR1 BITS Reserved 4 CSR2 3 2 Reserved 1 0 CSR0 DESCRIPTIONS [14:12] CSR3 Select clock input for channel 3 [10:8] CSR2 Select clock input for channel 2.
W90N745CD/W90N745CDG PWM Control Register (PWM_PCR) REGISTER ADDRESS PWM_PCR 0xFFF8_7008 31 30 R/W DESCRIPTION RESET VALUE R/W PWM Control Register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 PCR19 PCR18 PCR17 PCR16 Reserved 23 22 21 20 Reserved 15 14 13 12 11 10 9 8 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 PCR09 PCR08 7 6 5 4 3 2 1 0 PCR07 PCR06 PCR05 PCR04 PCR03 PCR02 PCR01 PCR00 BITS DESCRIPTIONS Channel 3 toggle/one shot mode [19] PCR 19 1 = togg
W90N745CD/W90N745CDG Continued BITS DESCRIPTIONS Channel 2 enable/disable [12] PCR 12 1 = enable 0 = disable Channel 1 toggle/one shot mode [11] PCR 11 1 = toggle mode 0 = one shot mode Channel 1 Inverter on/off [10] PCR 10 1 = inverter on 0 = inverter off [09] PCR 09 Reserved Channel 1 enable/disable [08] PCR 08 1 = enable 0 = disable [07] PCR 07 Reserved [06] PCR 06 Reserved Dead-Zone generator 1 enable/disable [05] PCR 05 1 = enable dead-zone generator 0 = disable dead-zone gene
W90N745CD/W90N745CDG PWM Counter Register 0/1/2/3 (PWM_CNR0/1/2/3) REGISTER ADDRESS PWM_CNR0 0xFFF8_700C R/W PWM Counter Register 0 0x0000_0000 PWM_CNR1 0xFFF8_7018 R/W PWM Counter Register 1 0x0000_0000 PWM_CNR2 0xFFF8_7024 R/W PWM Counter Register 2 0x0000_0000 PWM_CNR3 0xFFF8_7030 R/W PWM Counter Register 3 0x0000_0000 31 30 R/W 29 DESCRIPTION 28 RESET VALUE 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 CNRx[15:8] 7 6 5
W90N745CD/W90N745CDG PWM Comparator Register 0/1/2/3 (PWM_CMR0/1/2/3) REGISTER ADDRESS PWM_CMR0 0xFFF8_7010 R/W PWM Comparator Register 0 0x0000_0000 PWM_CMR1 0xFFF8_701C R/W PWM Comparator Register 1 0x0000_0000 PWM_CMR2 0xFFF8_7028 R/W PWM Comparator Register 2 0x0000_0000 PWM_CMR3 0xFFF8_7034 R/W PWM Comparator Register 3 0x0000_0000 31 30 R/W 29 DESCRIPTION 28 RESET VALUE 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 CMR
W90N745CD/W90N745CDG PWM Data Register 0/1/2/3 (PWM_PDR 0/1/2/3) REGISTER ADDRESS R/W PWM_PDR0 0xFFF8_7014 R PWM Data Register 0 0x0000_0000 PWM_PDR1 0xFFF8_7020 R PWM Data Register 1 0x0000_0000 PWM_PDR2 0xFFF8_702C R PWM Data Register 2 0x0000_0000 PWM_PDR3 0xFFF8_7038 R PWM Data Register 3 0x0000_0000 31 30 29 DESCRIPTION 28 RESET VALUE 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 PDRx[15:8] 7 6 5 4 3 PDRx[7:0]
W90N745CD/W90N745CDG PWM Interrupt Enable Register (PWM_PIER) REGISTER ADDRESS PWM_PIER 0xFFF8_703C 31 R/W 30 DESCRIPTION RESET VALUE R/W PWM Interrupt Enable Register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PIER3 PIER2 PIER1 PIER0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 Reserved BITS 4 DESCRIPTIONS [31:4] Reserved - [3] PIER3 Enable/Disable PWM counter channel 3 interrupt request 1 = enable 0 = disable [2] PIER2 Ena
W90N745CD/W90N745CDG PWM Interrupt Indication Register (PWM_PIIR) REGISTER ADDRESS R/W/C PWM_PIIR 0xFFF8_7040 R/C 31 30 29 DESCRIPTION RESET VALUE PWM Interrupt Indication Register 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PIIR3 PIIR2 PIIR1 PIIR0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved BITS DESCRIPTIONS [3] PIIR3 PWM counter channel 3 interrupt flag [2] PIIR2 PWM counter channel 2 interrupt flag [1] PIIR1 PWM c
W90N745CD/W90N745CDG 6.17 Keypad Interface W90N745 Keypad Interface (KPI) is an APB slave with 4-row scan output and 8-column scan input. KPI scans an array up to 16x8 with an external 4 to 16 decoder. It can also be programmed to scan 8x8 or 4x8 key array. If the 4x8 array is selected then external decoder is not necessary because the scan signals are dived by W90N745 itself.
W90N745CD/W90N745CDG Figure 6.17.1 W90N745 Keypad Interface 6.17.
W90N745CD/W90N745CDG 6.17.
W90N745CD/W90N745CDG Continued BITS DESCRIPTION Key pad scan enable [18] ENKP Setting this bit high enable the key scan function. 1 = enable key pad scan 0 = disable key pad scan Key array size [17:16] KSIZE KSIZE Key array size 2’b00 4x8, 3x8, 2x8, 1x8 2’b01 8x8, 7x8, 6x8, 5x8 2’b1x 16x8, 15x8, 14x8, 13x8, 12x8, 11x8, 10x8, 9x8 Debounce terminal count [15:8] DBTC Debounce counter counts the number of consecutive scans that decoded the same keys.
W90N745CD/W90N745CDG Figure 6.17.
W90N745CD/W90N745CDG BITS DESCRIPTION [31:26] RESERVED [25] EN3KY Enable three-keys detection Setting this bit enables hardware to detect 3 keys specified by software Enable three-key reset Setting this bit enable hardware reset when three-key is detected.
W90N745CD/W90N745CDG KeyPad Interface Low Power Mode Configuration Register (KPILPCONF) REGISTER ADDRESS R/W KPILPCOF 0xFFF8_8008 W/R 31 30 29 DESCRIPTION RESET VALUE Low power configuration register 28 27 0x0000_0000 26 25 24 18 17 16 RESERVED 23 22 21 20 19 WAKE 15 14 13 12 11 10 9 8 3 2 1 0 LPWCEN 7 6 5 4 RESERVED BITS [31:17] LPWR DESCRIPTION RESERVED Lower power wakeup enable [16] WAKE Setting this bit enables low power wakeup 1 = wakeup enable 0 = not en
W90N745CD/W90N745CDG Key Pad Interface Status Register (KPISTATUS) REGISTER ADDRESS R/W KPISTATUS 0xFFF8_800C R/O 31 30 29 DESCRIPTION key pad status register 28 RESET VALUE 0x0000_0000 27 26 25 24 RESERVED 23 22 21 20 19 18 17 16 RESERVED INT 3 K R S T PDWAKE 3KEY 2KEY 1KEY 15 13 12 11 10 9 8 14 RESERVED 7 KEY1R 6 5 RESERVED KEY1C 4 3 KEY0R 1 0 KEY0C BITS [31:22] 2 DESCRIPTION RESERVED Key interrupt [21] INT This bit indicates the key scan interru
W90N745CD/W90N745CDG Continued BITS DESCRIPTION Double-key press [17] 2KEY This bit indicates that 2 keys have been detected. Software can read {KEY1R, KEY1C} and {KEY0R, KEY0C} to know which two keys are pressed. Single-key press [16] 1KEY [15] RESERVED This bit indicates that 1 key has been detected. Software can read {KEY0R, KEY0C} to know which key is pressed. KEY1 row address [14:11] KEY1R [10:8] KEY1C [7] RESERVED This value indicates key1 row address.
W90N745CD/W90N745CDG 6.18 PS2 Host Interface Controller W90N745 PS2 host controller interface is an APB slave consisted of PS2 protocol. It is used to connect to your IBM keyboard or other device through PS2 interface. For example, the IBM keyboard will sends scan codes to the host controller, and the scan codes will tell your Keyboard Bios what keys you have pressed or released. Besides Scan codes, commands can also be sent to the keyboard from host.
W90N745CD/W90N745CDG 6.18.
W90N745CD/W90N745CDG 6.18.
W90N745CD/W90N745CDG PS2 Host Controller Status Register (PS2_STS) REGISTER ADDRESS PS2STS 31 0xFFF8_9004 30 R/W DESCRIPTION R/W 29 RESET VALUE Status register 28 0x0000_0000 27 26 25 24 18 17 16 10 9 8 2 1 0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 RESERVED 5 4 TX_err TX_IRQ BITS [31:6] 3 RESERVED RX_IRQ DESCRIPTIONS RESERVED This Transmit Error Status bit indicates software that device doesn’t response ACK after Host wrote a command to it
W90N745CD/W90N745CDG PS2 Host Controller RX Scan Code Register (PS2_SCANCODE) REGISTER ADDRESS PS2SCANCODE 31 R/W 0xFFFF_9008 30 DESCRIPTION R/W 29 RESET VALUE PS2 Host RX Scan Code Register 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RX_shift_key RESERVED 7 6 5 4 3 2 RX_releaseRX_extend 1 0 RX_SCAN_CODE BITS DESCRIPTIONS [31:11] RESERVED - [10] RX_shift_key This Receive Shift Key bit indicates that left or right
W90N745CD/W90N745CDG PS2 Host Controller RX ASCII Code Register (PS2_ASCII) REGISTER ADDRESS R/W PS2ASCII 0xFFF8_900C R/W 31 30 29 DESCRIPTION RESET VALUE PS2 Host RX ASCII Code Register 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 RX_ASCII_CODE BITS [31:8] DESCRIPTIONS RESERVED PS2 Host Controller Received Data Filed [7:0] RX_ASCII_CODE This field stores the ASCII data content transmitted
W90N745CD/W90N745CDG 7. ELECTRICAL SPECIFICATIONS 7.1 Absolute Maximum Ratings Ambient temperature .................................……………............................. -40 °C ~ +85°C Storage temperature ..................................................…….................... -40 °C ~ +125°C Voltage on any pin ...............................................................…….......... -0.5V ~ 6V Power supply voltage (Core logic) ..............................…...........………..….. -0.5V ~ 1.
W90N745CD/W90N745CDG Continued. SYMBOL PARAMETER CONDITION MIN. MAX. UNIT ICC1 1.8V Supply Current FCPU = 80MHz - 150 mA ICC2 3.3V Supply Current FCPU = 80MHz - 60 mA ICCRTC RTC 1.8V Supply Current FRTC 32.768KHZ - 7 uA IIH Input High Current VIN = 2.4 V -1 1 µA IIL Input Low Current VIN = 0.4 V -1 1 µA IIHP Input High Current (pull-up) VIN = 2.4 V -15 -10 µA IILP Input Low Current (pull-up) VIN = 0.
W90N745CD/W90N745CDG Continued. PARAMETER IOL IOH MIN. TYP. MAX. Low level output current @VOL = 0.4V 4mA 4.9mA 7.4mA 9.8mA Low level output current @VOL = 0.4V 8mA 9.7mA 14.9mA 19.5mA Low level output current @VOL = 0.4V 12mA 14.6mA 22.3mA 29.3mA High level output current @VOH = 2.4V 4mA 6.3mA 12.8mA 21.2mA High level output current @VOH = 2.4V 8mA 12.7mA 25.6mA 42.4mA High level output current @VOH = 2.4V 12mA 19.0mA 38.4mA 63.
W90N745CD/W90N745CDG 7.3 AC Specifications 7.3.1 EBI/SDRAM Interface AC Characteristics 1.5V MCLK TDSU D[31:0] TDH Iutput Valid 1.5V SDRAM input to W90P710 MCLK D[31:0] 1.5V TDO 1.5V Output Valid W90P710 write to SDRAM SYMBOL PARAMETER MIN. MAX.
W90N745CD/W90N745CDG 7.3.
W90N745CD/W90N745CDG 7.3.3 USB Transceiver AC Characteristics Rise Time CL Differential Data Lines CL Fall Time 90% 90% 10% 10% tR Full Speed: 4 to 20ns at CL = 50pF tF Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF Data Signal Rise and Fall Time USB Transceiver AC Characteristics SYMBOL DESCRIPTION CONDITIONS MIN MAX UNIT TR Rise Time CL = 50 pF 4 20 ns TF Fall Time CL = 50 pF 4 20 ns TRFM Rise/Fall Time Matching 90 110 % TDRATE Full Speed Data Rate 11.97 12.
W90N745CD/W90N745CDG SYMBOL DESCRIPTION TFREQ RMII reference clock frequency TDUTY RMII clock duty TTXO MIN TYP MAX 50 UNIT MHz 35% 50% 65% ns Transmit data output delay 5 - 15 ns TTXH Transmit data hold time 2 - - ns TRXS Receive data setup time 4 - - ns TRXH Receive data hold time 2 - - ns PHY_MDC TMDO TMDH PHY_MDIO (Write) valid data TMDS PHY_MDIO (Read) SYMBOL TMDH valid data DESCRIPTION MIN MAX UNIT 15 ns TMDO MDIO Output Delay Time 0 TMDSU MDIO
W90N745CD/W90N745CDG 7.3.5 AC97/I2S Interface AC Characteristics TCLK_PERIOD AC97_BCLK TOD AC97_DATAO AC97_SYNC TISU TIHD TOH AC97_DATAI SYMBOLS DESCRIPTION MIN TYP. MAX UNIT TCLK_PERIOD AC97 Bit Clock Frequency -- 12.
W90N745CD/W90N745CDG TBCLK_PERIOD I2S_BCLK Tout_delay I2S_DATAO I2S_RLCLK TDOH TDIS TDIH I2S_DATAI SYMBOLS DESCRIPTION MIN MAX Note:depend on codec spec.
W90N745CD/W90N745CDG 7.3.
W90N745CD/W90N745CDG 7.3.
W90N745CD/W90N745CDG SYMBOL DESCRIPTION MIN MAX UNIT FUSI USI clock frequency - 20 MHz TCLKH USI clock high time 12.5 - ns TCLKL USI clock low time - - ns TISU Data input setup time - 14 ns TIH Data input hold time 0 - ns Tlead USI enable lead time 12.5 - ns Tlag USI enable lag time 12.5 - ns TOD USI output data valid time - 30 ns 7.3.
W90N745CD/W90N745CDG SYMBOL DESCRIPTION MIN. MAX.
W90N745CD/W90N745CDG 8. ORDERING INFORMATION PART NUMBER NAME PACKAGE DESCRIPTION W90N745CD LQFP128 128 Leads, body 14 x 14 x 1.4 mm W90N745CDG LQFP128 128 Leads, body 14 x 14 x 1.
W90N745CD/W90N745CDG 9. PACKAGE SPECIFICATIONS 128L LQFP (14X14X1.4 mm footprint 2.
W90N745CD/W90N745CDG 10.
W90N745CD/W90N745CDG Cache Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAHCNF 0xFFF0_2000 R/W Cache configuration register 0x0000_0000 CAHCON 0xFFF0_2004 R/W Cache control register 0x0000_0000 CAHADR 0xFFF0_2008 R/W Cache address register 0x0000_0000 EMC Registers Map REGISTER ADDRESS CAMCMR 0xFFF0_3000 CAMEN R/W DESCRIPTION RESET VALUE 0x0000_0000 0xFFF0_3004 R/W CAM Command Register R/W CAM Enable Register CAM0M 0xFFF0_3008 R/W CAM0 Most Significant
W90N745CD/W90N745CDG EMC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM12M 0xFFF0_3068 R/W CAM12 Most Significant Word Register 0x0000_0000 CAM12L 0xFFF0_306C R/W CAM12 Least Significant Word Register 0x0000_0000 CAM13M 0xFFF0_3070 R/W CAM13 Most Significant Word Register 0x0000_0000 CAM13L 0xFFF0_3074 R/W CAM13 Least Significant Word Register 0x0000_0000 CAM14M 0xFFF0_3078 R/W CAM14 Most Significant Word Register 0x0000_0000 CAM14L 0xFFF0_307C R/W CAM1
W90N745CD/W90N745CDG EMC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RXFSM 0xFFF0_3200 R Receive Finite State Machine Register 0x0081_1101 TXFSM 0xFFF0_3204 R Transmit Finite State Machine Register 0x0101_1101 FSM0 0xFFF0_3208 R Finite State Machine Register 0 0x0001_0101 FSM1 0xFFF0_320C R Finite State Machine Register 1 0x1100_0100 DCR 0xFFF0_3210 DMMIR BISTR 0x0000_003F 0xFFF0_3214 R/W Debug Configuration Register R Debug Mode MAC Information Regis
W90N745CD/W90N745CDG USB Host Controller Registers Map REGISTER DESCRIPTION RESET VALUE ADDRESS R/W HcRevision 0xFFF0_5000 R HcControl 0xFFF0_5004 R/W Host Controller Control Register 0x0000_0000 HcCommandStatus 0xFFF0_5008 R/W Host Controller Command Status Register 0x0000_0000 HcInterruptStatus 0xFFF0_500C R/W Host Controller Interrupt Status Register 0x0000_0000 HcInterruptEnbale 0xFFF0_5010 R/W Host Controller Interrupt Enable Register 0x0000_0000 HcInterruptDisbale 0xFFF0_5014 R/W
W90N745CD/W90N745CDG USB Device Register Map REGISTER OFFSET R/W DESCRIPTION RESET VALUE USB_CTL 0xFFF0_6000 R/W USB control register 0x0000_0000 VCMD 0xFFF0_6004 R/W USB class or vendor command register 0x0000_0000 USB_IE 0xFFF0_6008 R/W USB interrupt enable register 0x0000_0000 USB_IS 0xFFF0_600C R USB interrupt status register 0x0000_0000 USB_IC 0xFFF0_6010 R/W USB interrupt status clear register 0x0000_0000 USB_IFSTR 0xFFF0_6014 R/W USB interface and string register 0x0
W90N745CD/W90N745CDG USB Device Register Map, continued REGISTER OFFSET R/W DESCRIPTION RESET VALUE EPB_LENTH 0xFFF0_607C R/W USB endpoint B transfer length register 0x0000_0000 EPC_INFO 0xFFF0_6080 R/W USB endpoint C information register 0x0000_0000 EPC_CTL 0xFFF0_6084 R/W USB endpoint C control register 0x0000_0000 EPC_IE 0xFFF0_6 088 R/W USB endpoint C Interrupt Enable register 0x0000_0000 EPC_IC 0xFFF0_608C W USB endpoint C interrupt clear register 0x0000_0000 EPC_IS 0xFFF0_6090
W90N745CD/W90N745CDG Audio Control Register Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE ACTL_PDSTC 0xFFF0_9020 R ACTL_PSR 0xFFF0_9024 R/W ACTL_I²SCON 0xFFF0_9028 R/W I²S control register ACTL_ACCON 0xFFF0_902C R/W AC-link control register 0x0000_0000 ACTL_ACOS0 0xFFF0_9030 R/W AC-link out slot 0 0x0000_0000 ACTL_ACOS1 0xFFF0_9034 R/W AC-link out slot 1 0x0000_0080 ACTL_ACOS2 0xFFF0_9038 R/W AC-link out slot 2 0x0000_0000 ACTL_ACIS0 0xFFF0_903C R AC-link in sl
W90N745CD/W90N745CDG High Speed UART1 Control Registers Map REGISTER ADDRESS R/W UART1_RBR 0xFFF8_0100 R Receive Buffer Register (DLAB = 0) Undefined UART1_THR 0xFFF8_0100 W Transmit Holding Register (DLAB = 0) Undefined UART1_IER 0xFFF8_0104 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000 UART1_DLL 0xFFF8_0100 R/W UART1_DLM 0xFFF8_0104 R/W UART1_IIR 0xFFF8_0108 R Interrupt Identification Register UART1_FCR 0xFFF8_0108 W FIFO Control Register Undefined UART1_LCR 0xFFF8
W90N745CD/W90N745CDG UART2_IRCR 0xFFF8_0220 R/W IrDA Control Register 0x0000_0040 UART3 Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART3_RBR 0xFFF8_0300 R Receive Buffer Register (DLAB = 0) Undefined UART3_THR 0xFFF8_0300 W Transmit Holding Register (DLAB = 0) Undefined Interrupt Enable Register (DLAB = 0) 0x0000_0000 UART3_IER 0xFFF8_0304 R/W UART3_DLL 0xFFF8_0300 R/W UART3_DLM 0xFFF8_0304 R/W UART3_IIR Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Registe
W90N745CD/W90N745CDG AIC Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR1 0xFFF8_2004 R/W Source Control Register 1 0x0000_0047 AIC_SCR2 0xFFF8_2008 R/W Source Control Register 2 0x0000_0047 AIC_SCR3 0xFFF8_200C R/W Source Control Register 3 0x0000_0047 AIC_SCR4 0xFFF8_2010 R/W Source Control Register 4 0x0000_0047 AIC_SCR5 0xFFF8_2014 R/W Source Control Register 5 0x0000_0047 AIC_SCR6 0xFFF8_2018 R/W Source Control Register 6 0x0000_0047 AIC_SCR7
W90N745CD/W90N745CDG AIC Control Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION AIC_IRSR 0xFFF8_2100 R Interrupt Raw Status Register 0x0000_0000 AIC_IASR 0xFFF8_2104 R Interrupt Active Status Register 0x0000_0000 AIC_ISR 0xFFF8_2108 R Interrupt Status Register 0x0000_0000 AIC_IPER 0xFFF8_210C R Interrupt Priority Encoding Register 0x0000_0000 AIC_ISNR 0xFFF8_2110 R Interrupt Source Number Register 0x0000_0000 AIC_IMR 0xFFF8_2114 R Interrupt Mask Register 0x0000_0
W90N745CD/W90N745CDG GPIO Control Register Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG5 0xFFF8_3050 R/W GPIO Port5 Configuration Register 0x0000_0000 GPIO_DIR5 0xFFF8_3054 R/W GPIO Port5 Direction Control Register 0x0000_0000 GPIO_DATAOUT5 0xFFF8_3058 R/W GPIO Port5 Data Output Register 0x0000_0000 GPIO_DATAIN5 GPIO Port5 Data Input Register 0xXXXX_XXXX GPIO_DBNCECON 0xFFF8_3070 R/W GPIO Input Debounce Control Register 0x0000_0000 GPIO_XICFG 0xFFF8_3074 R/W
W90N745CD/W90N745CDG USI Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_CNTRL 0xFFF8_6200 R/W Control and Status Register 0x0000_0004 USI_DIVIDER 0xFFF8_6204 R/W Clock Divider Register 0x0000_0000 USI_SSR 0xFFF8_6208 R/W Slave Select Register 0x0000_0000 Reserved 0xFFF8_620C N/A Reserved USI_Rx0 0xFFF8_6210 R Data Receive Register 0 0x0000_0000 USI_Rx1 0xFFF8_6214 R Data Receive Register 1 0x0000_0000 USI_Rx2 0xFFF8_6218 R Data Receive Register 2 0x0000_0000
W90N745CD/W90N745CDG KPI Control Register Map REGISTER KPICONF ADDRESS R/W DESCRIPTION 0xFFF8_8000 R/W Keypad controller configuration Register RESET VALUE 0x0000_0000 KPI3KCONF 0xFFF8_8004 R/W Keypad controller 3-keys configuration register 0x0000_0000 KPILPCONF 0xFFF8_8008 R/W Keypad controller low power configuration 0x0000_0000 register KPISTATUS 0xFFF8_800C R/O Keypad controller status register 0x0000_0000 PS2 Control Register Map REGISTER ADDRESS R/W/C DESCRIPTION RESET VALUE PS2CMD 0
W90N745CD/W90N745CDG Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life.
