W90P710CD/W90P710CDG 32-BIT ARM7TDMI-BASED MCU W90P710CD/W90P710CDG 16/32-bit ARM microcontroller Product Data Sheet -1- Publication Release Date: September 19, 2006 Revision B2
W90P710CD/W90P710CDG Revision History REVISION DATE COMMENTS A 2005/12/02 Draft A.1 2005/12/21 Modify the register definition A.2 2006/01/17 Modify SD description Update LCD C version design spec. A.3 2006/07/07 Update Smartcard C version design spec. Add RTC 32.768K clock measurment apllication note. Add RTC application note. Change EBI SDRAM control register SDCONFx[13] AUTOPR definition. B 2006/07/26 Modify LCD register map section 7.2.
W90P710CD/W90P710CDG Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 6 2. FEATURES ................................................................................................................................. 6 3. PIN DIAGRAM .......................................................................................................................... 13 4. PIN ASSIGNMENT .................................
W90P710CD/W90P710CDG 6.8.1 6.8.2 6.8.3 6.9 SD Host Controller...................................................................................................... 234 6.9.1 6.9.2 6.9.3 6.10 RTC Register Map......................................................................................................426 RTC Application Note .................................................................................................439 Smart Card Host Interface ..............................................
W90P710CD/W90P710CDG 6.19 Universal Serial Interface............................................................................................ 483 6.19.1 6.19.2 6.20 PWM ........................................................................................................................... 491 6.20.1 6.20.2 6.20.3 6.20.4 6.20.5 6.20.6 6.21 KeyPad Interface Register Map..................................................................................503 Register Description ........................
W90P710CD/W90P710CDG 1. GENERAL DESCRIPTION The W90P710 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which designed by Advanced RISC Machines, Ltd. It offers 4K-byte I-cache/SRAM and 4K-byte Dcache/SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost sensitive and power sensitive applications. One 10/100 Mb MAC of Ethernet controller is built-in to reduce total system cost.
W90P710CD/W90P710CDG Ethernet MAC Controller y DMA engine with burst mode y MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx) y Data alignment logic y Endian translation y 100/10-Mbit per second operation y Full compliance with IEEE standard 802.
W90P710CD/W90P710CDG (5) LCD Post processing y Support for one OSD (On-Screen-Display) overlay y Support various OSD function y Programmable parameters for different display panel (6) Others y Color-look up table size 256x32 bit for TFT used when displaying 1bpp, 2bpp, 4bpp, 8bpp image y Dedicated DMA for block transfer mode DMA Controller y 2-channel General DMA for memory-to-memory data transfers without CPU intervention y Initialed by a software or external DMA request y Increments or
W90P710CD/W90P710CDG Advanced Interrupt Controller y 31 interrupt sources, including 6 external interrupt sources y Programmable normal or fast interrupt mode (IRQ, FIQ) y Programmable as either edge-triggered or level-sensitive for 6 external interrupt sources y Programmable as either low-active or high-active for 6 external interrupt sources y Priority methodology is encoded to allow for interrupt daisy-chaining y Automatically mask out the lower priority interrupt during interrupt nesting US
W90P710CD/W90P710CDG 4-Channel PWM y Four 16-bit timers with PWM y Two 8-bit pre-scalers & Two 4-bit dividers y Programmable duty control of output waveform y Auto reload mode or one-shot pulse mode y Dead-zone generator I2C Master y Two Channel I2C y Compatible with Philips I2C standard, support master mode only y Support multi master operation y Clock stretching and wait state generation y Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer y
W90P710CD/W90P710CDG y When reach middle and end address of destination address, a DMA_IRQ is requested to CPU automatically Smart Card Host Interface (SCHI) y ISO-7816 compliant y PC/SC T=0, T=1 compliant y 16-byte transmitter FIFO and 16-byte receiver FIFO y FIFO threshold interrupt to optimize system performance y Programmable transmission clock frequency y Versatile baud rate configuration y UART-like register file structure y General-purpose C4, C8 channels SD Host Interface y Direc
W90P710CD/W90P710CDG Operation Voltage Range y 3.0 ~ 3.6 V for IO Buffer y 1.62 ~ 1.
W90P710CD/W90P710CDG 3.
W90P710CD/W90P710CDG 4. PIN ASSIGNMENT Table 4.1 W90P710 Pins Assignment PIN NAME 176-PIN LQFP Clock & Reset ( 5 pins ) EXTAL (15M) XTAL (15M) EXTAL32 (32.768K) XTAL32 (32.
W90P710CD/W90P710CDG Table 4.
W90P710CD/W90P710CDG Table 4.
W90P710CD/W90P710CDG Table 4.
W90P710CD/W90P710CDG Table 4.
W90P710CD/W90P710CDG Table 4.
W90P710CD/W90P710CDG 5. PIN DESCRIPTION Table 5.1 W90P710 Pins Description PIN NAME IO TYPE DESCRIPTION Clock & Reset EXTAL (15M) XTAL (15M) EXTAL32(32.768 K) XTAL32(32.
W90P710CD/W90P710CDG Table 5.
W90P710CD/W90P710CDG Table 5.
W90P710CD/W90P710CDG Table 5.
W90P710CD/W90P710CDG Table 5.1 W90P710 Pins Description (Continued) Pin Name SCHI/SD/XDMA SC0_RST / SD_DAT0 / GPIO [27] / VD[15] SC0_PRES / SD_DAT1 / GPIO [26] VD[14] SC0_nPWR / SD_DAT2 / GPIO [25] / VD[13] SC1_DAT / SD_DAT3 / GPIO [24] / VD[12] SC1_CLK / GPIO [23] / VD[11] SC1_RST / SD_CD / GPIO [22] / VD[10] SC1_PRES / nXDREQ / GPIO [21] / VD[9] SC1_nPWR / nXDACK / GPIO [20] / VD[8] IO Type IO IO IO IO IO IO IO IO Description Smart Card Reset Output to Card 0.
W90P710CD/W90P710CDG Table 5.1 W90P710 Pins Description (Continued) Pin Name IO Type Description Power/Ground VDD18 VSS18 VDD33 VSS33 USBVDD USBVSS DVDD18 DVSS18 AVDD18 AVSS18 P G P G P G P G P G Core Logic power (1.8V) Core Logic ground (0V) IO Buffer power (3.3V) IO Buffer ground (0V) USB power (3.3V) USB ground (0V) PLL Digital power (1.8V) PLL Digital ground (0V) PLL Analog power (1.
W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List PIN NO. DEFAULT FUNCTION0 FUNCTION1 FUNCTION2 FUNCTION3 USB1.
W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO.
W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO.
W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO.
W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO.
W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO.
W90P710CD/W90P710CDG Table 5.2 W90P710 176-pin LQFP Multi-function List (Continued) PIN NO.
W90P710CD/W90P710CDG 6. 6.1 FUNCTIONAL DESCRIPTION ARM7TDMI CPU CORE The ARM7TDMI CPU core is a member of the Advanced RISC Machines (ARM) family of generalpurpose 32-bit microprocessors, which offer high performance for very low power consumption. The architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set Computers.
W90P710CD/W90P710CDG 6.2 System Manager 6.2.1 Overview The W90P710 System Manager has the following functions. y System memory map y Data bus connection with external memory y Product identifier register y Bus arbitration y PLL module y Clock select and power saving control register y Power-On setting 6.2.2 System Memory Map W90P710 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable.
W90P710CD/W90P710CDG Cacheable space 0x7FFF_FFFF 512KB (Fixed) 0x7FF8.
W90P710CD/W90P710CDG Table 6.2.
W90P710CD/W90P710CDG Table 6.2.1 On-Chip Peripherals Memory Map (Continued) BASE ADDRESS DESCRIPTION APB Peripherals 0xFFF8_7000 Pulse Width Modulation (PWM) Control Registers 0xFFF8_8000 KeyPad Interface Control Register (KPI) 0xFFF8_9000 PS2 Control Registers 6.2.3 Address Bus Generation The W90P710 address bus generation is depended on the required data bus width of each memory bank. The data bus width is determined by DBWD bits in each bank’s control register.
W90P710CD/W90P710CDG Big endian In Big endian format, the W90P710 stores the most significant byte of a word at the lowest numbered byte, and the least significant byte at the highest-numbered byte. So the byte at address 0 of the memory system connects to data lines 31 through 24. For a word aligned address A, Fig6.2.3 shows how the word at address A, the half-word at addresses A and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when the D14 pin is Low.
W90P710CD/W90P710CDG Fig6.2.5 CPU registers Read/Write with external memory Table 6.2.3 and Table 6.2.4 Using big-endian and word access, Program/Data path between register and external memory WA = Address whose LSB is 0,4,8,C X = Don’t care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table6.2.
W90P710CD/W90P710CDG Table6.2.4 Word access read operation with Big Endian ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY) XD WIDTH WORD HALF WORD BYTE Bit Number CPU Reg Data 31 0 ABCD 31 0 CDAB 31 0 DCBA SA WA WA WA Bit Number SD Bit Number ED 31 0 ABCD 31 0 ABCD 31 0 CD AB 31 0 31 0 CD XX CD AB 31 0 D C B A 31 0 31 0 D C X X D C B X XA WA WA WA+2 WA WA+1 WA+2 WA+3 SDQM [3-0] AAAA XXAA XXAA XXXA XXXA XXXA XXXA Bit Number XD Bit Number Ext.
W90P710CD/W90P710CDG Table6.2.6 Half-word access read operation with Big Endian ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY) XD WIDTH WORD HALF WORD BYTE Bit Number CPU Reg Data 15 0 AB 15 0 CD 15 0 CD 15 0 DC SA HAL HAU HA HA Bit Number SD Bit Number ED 15 0 AB 15 0 AB 15 0 CD 15 0 CD 15 0 CD 15 0 CD 15 0 DC 15 0 DX 15 0 DC XA HAL HAL HA HA HA+1 SDQM [3-0] AAUU UUAA XXAA XXXA XXXA Bit Number XD Bit Number Ext.
W90P710CD/W90P710CDG Table6.2.
W90P710CD/W90P710CDG Table 6.2.9 and Table 6.2.10 Using little-endian and word access, Program/Data path between register and external memory WA = Address whose LSB is 0,4,8,C X = Don’t care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table6.2.
W90P710CD/W90P710CDG Table 6.2.11 and Table 6.2.12 Using little-endian and half-word access, Program/Data path between register and external memory. HA = Address whose LSB is 0,2,4,6,8,A,C,E HAL = Address whose LSB is 0,4,8,C HAU = Address whose LSB is 2,6,A,E X = Don’t care nWBE [3-0] / SDQM [3-0] = A means active and U means inactive Table6.2.
W90P710CD/W90P710CDG Table 6.2.13 and Table 6.2.14 Using little-endian and byte access, Program/Data path between register and external memory. BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F BAL = Address whose LSB is 0,2,4,6,8,A,C,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F BA0 = Address whose LSB is 0,4,8,C BA1 = Address whose LSB is 1,5,9,D BA2 = Address whose LSB is 2,6,A,E BA3 = Address whose LSB is 3,7,B,F Table6.2.
W90P710CD/W90P710CDG 6.2.5 Bus Arbitration The W90P710’s internal function blocks or external devices can request mastership of the system bus and then hold the system bus in order to perform data transfers. Because the design of W90P710 bus allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal units or external devices simultaneously request bus mastership.
W90P710CD/W90P710CDG 6.2.5.2 Rotate Priority Mode In Rotate Priority Mode (PRTMOD=1), the IPEN and IPACT bits have no function (i.e. can be ignored). W90P710 uses a round robin arbitration scheme ensures that all bus masters have equal chance to gain the bus and that a retracted master does not lock up the bus. 6.2.6 Power management W90P710 provide three power management scenarios to reduce power consumption.
W90P710CD/W90P710CDG IDLE Period FOUT (PLL) HCLK idle_state MCLK (ARM) HCLK (cache) HCLK (memc) Case1. IDLE=1, PD=0, MIDLE=0 Fig. 6.2.7 Clock management for system idle mode IDLE Period FOUT (PLL) HCLK idle_state MCLK (ARM) HCLK (cache) HCLK (memc) Case2. IDLE=1, PD=0, MIDLE=1 Fig. 6.2.8 Clock management for system and memory idle mode Power Down Mode This mode provides the minimum power consumption.
W90P710CD/W90P710CDG 65536 clocks EXTAL HCLK idle _state wake up by pheripheral's interrupts pd_state HCLK (cache) Case3. IDLE=0, PD=1, MIDLE=0 Fig 6.2.9 Clock management for system power down mode and wake up 6.2.7 Power-On Setting After power on reset, there are eight Power-On setting pins to configure W90P710 system configuration.
W90P710CD/W90P710CDG 6.2.
W90P710CD/W90P710CDG BITS DESCRIPTION Package Type Select [31:30] PACKAGE [29:24] VERSION [23:0] CHIPID These two bits are power-on setting latched from pin D[9:8] Package [31:30] 1 1 Package Type 176-pin Package Version of chip The chip identifier 0x090.
W90P710CD/W90P710CDG PLL Control Register0 （PLLCON0） W90P710 provides two clock generation options – crystal and oscillator. The external clock via EXTAL(15M) Minput pin as the reference clock input of PLL module. The external clock can bypass the PLL and be used to the internal system clock by pull-down the data D15 pin. Using PLL’s output clock for the internal system clock, D15 pin must be pull-up.
W90P710CD/W90P710CDG EXTAL USBCKS FIN INDV[4:0] GP0 PLL Input Divider (NR) Charge Pump PFD FBDV[8:0] VCO 1 48MHz Gen Output 480MHz Divider FOUT (NO) Internal System Clock 0 Clock Divider & Selector Feedback Divider (NF) USB Module 0 1 ECLKS CLKS[2:0] OTDV[1:0] Fig 6.2.8.
W90P710CD/W90P710CDG BITS DESCRIPTION [31:29] RESERVED [28] PS2 PS2 controller clock enable bit 0 = Disable PS2 controller clock 1 = Enable PS2 controller clock Keypad controller clock enable bit [27] KPI 0 = Disable keypad controller clock 1 = Enable keypad controller clock Smart Card Host controller 1 clock enable bit [26] SCH1 0 = Disable smart card host controller 1 clock 1 = Enable smart card host controller 1 clock Smart Card Host controller 0 clock enable bit [25] SCH0 0 = Disable smar
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION PWM controller clock enable bit [17] PWM 0 = Disable PWM controller clock 1 = Enable PWM controller clock Audio Controller clock enable bit [16] AC97 0 = Disable AC97 controller clock 1 = Enable AC97 controller clock USB host/device 48MHz clock source Select bit [15] USBCKS 0 = USB clock 48MHz input from internal PLL (480MHz/10) 1 = USB clock 48MHz input from external GPIO0 pin, this pin direction must set to input.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION UART0 controller clock enable bit [5] UART0 0 = Disable UART0 controller clock 1 = Enable UART0 controller clock External clock select 0 = External clock from EXTAL pin is used as system clock [4] ECLKS 1 = PLL output clock is used as system clock After power on reset, the content of ECLKS is the Power-On Setting value. You can program this bit to change the system clock source.
W90P710CD/W90P710CDG PLL Control Register 1（PLLCON1） W90P710 provides extra PLL for LCD controller programmable pixel clock and provide 12.288/16.934 MHz clock source to Audio Controller. It uses the same 15MHz crystal clock input source with system PLL mentioned above.
W90P710CD/W90P710CDG EXTAL FIN INDV1[4:0] PFD FBDV1[8:0] PLL1 Input Divider (NR) Charge Pump VCO to LCD controller Output 480MHz Divider FOUT (NO) to Audio Controller Feedback Divider (NF) OTDV1[1:0] Fig 6.2.8.
W90P710CD/W90P710CDG IIS Clock Control Register (I2SCKCON) REGISTER ADDRESS R/W I2SCKCON 0xFFF0_0014 R/W 31 30 29 23 22 21 15 14 13 7 6 5 RESET VALUE I2S PLL clock Control Register 28 27 RESERVED 20 19 RESERVED 12 11 RESERVED 4 3 PRESCALE BITS [31:9] DESCRIPTION 0x0000_0000 26 25 24 18 17 16 10 9 2 1 8 IISPLLEN 0 DESCRIPTION RESERVED IIS PLL clock source enable [8] I2SPLLEN Set this bit will enable PLL1 clock output to audio I2S clock input.
W90P710CD/W90P710CDG BITS [31:8] DESCRIPTION RESERVED nIRQ3 wake up polarity [7] IRQWAKEUPPOL[3] 1 = nIRQ3 is high level wake up 0 = nIRQ3 is low level wake up nIRQ2 wake up polarity [6] IRQWAKEUPPOL[2] 1 = nIRQ2 is high level wake up 0 = nIRQ2 is low level wake up nIRQ1 wake up polarity [5] IRQWAKEUPPOL[1] 1 = nIRQ1 is high level wake up 0 = nIRQ1 is low level wake up nIRQ0 wake up polarity [4] IRQWAKEUPPOL[0] 1 = nIRQ0 is high level wake up 0 = nIRQ0 is low level wake up nIRQ3 wake up enab
W90P710CD/W90P710CDG 31 30 29 23 22 21 15 14 13 7 6 5 RESERVED 28 27 RESERVED 20 19 RESERVED 12 11 RESERVED 4 3 26 25 24 18 17 16 10 9 8 2 1 IRQWAKEFLAG 0 This register is used to record the wakeup events, after clock recovery, software should check these flags to identify which nIRQ is used to wakeup the system. And clear the flags in IRQ interrupt sevice routine.
W90P710CD/W90P710CDG BITS [31:3] DESCRIPTION RESERVED Memory controller IDLE enable Setting both MIDLE and IDLE bits HIGH will let memory controller enter IDLE mode, the clock source of memory controller will be halted while ARM CORE enter IDLE mode. [2] MIDLE 1=memory controller will be forced into IDLE mode, (clock of memory controller will be halted), when IDLE bit is set. 0 = memory controller still active when IDLE bit is set.
W90P710CD/W90P710CDG BITS [31:1] DESCRIPTION RESERVED USBHnD[0]: USB transceiver control [0] USBHnD There are two USB1.1 built-in transceivers for data transmission. One is dedicated for USB host and the other is shared with USB device. Software can program this bit to switch the transceiver path.
W90P710CD/W90P710CDG 6.3 External Bus Interface 6.3.1 EBI Overview W90P710 supports External Bus Interface (EBI), which controls the access to the external memory (ROM/FLASH, SDRAM) and External I/O devices. The EBI has seven chip selects to select one ROM/FLASH bank, two SDRAM banks, and four External I/O banks.The address bus is 22 bits. It supports 8-bit, 16-bit, and 32-bit external data bus width for each bank.
W90P710CD/W90P710CDG 6.3.2.1 SDRAM Components Supported Table 6.3.2.
W90P710CD/W90P710CDG SDRAM Data Bus Width: 16-bit A14 A13 (BS1) (BS0) R ** C R Total Type RxC R/C 16M 2Mx8 11x9 16M 1Mx16 11x8 C ** 9 64M 8Mx8 12x9 R 10 11 C 10 11 64M 4Mx16 12x8 R 10 9 C 10 9 R 10 C 10 R 10 11 10* 22 C 10 11 10* 22* R 10 11 10* 22 21 C 10 11 10* 22* AP 24* 9 8 7 6 5 10 9 10* 22 21 20 19 18 17 16 15 64M 128M 128M 2Mx32 11x8 16Mx8 12x10 8Mx16 12x9 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 10
W90P710CD/W90P710CDG SDRAM Data Bus Width: 8-bit A14 A13 Total Type RxC R/C 16M 2Mx8 11x9 R ** C 16M 1Mx16 11x8 R C ** 8 64M 8Mx8 12x9 R 9 10 C 9 10 64M 4Mx16 12x8 R 9 8 C 9 8 R 9 C 9 R C 64M 128M 128M 2Mx32 16Mx8 8Mx16 11x8 12x10 12x9 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 9 ** 9* 20 19 18 17 16 15 14 13 12 11 10 ** 9 ** 9* AP 23* 8 7 6 5 4 3 2 1 0 ** 8 ** 8* 9 19 18 17 16 15 14 13 12 11 10 ** 8*
W90P710CD/W90P710CDG 6.3.2.3 SDRAM Interface A [ 1 0 :0 ] A [ 2 1 :0 ] A [ 1 0 :0 ] A13 BS0 A14 BS1 D Q [ [ 3 1 :0 ] D [ 3 1 :0 ] M CLK CLK M CKE CKE nSCS0 n S C S [ 1 :0 ] nCS nSRAS nRAS nSCAS nCAS nSW E nW E n S D Q M [ 3 :0 ] n S D Q M [ 3 :0 ] D Q M [ 3 :0 ] SDRAM 64M b 512Kx4x32 W 90P710 Fig 6.3.1 SDRAM Interface 6.3.
W90P710CD/W90P710CDG EBI Control Register (EBICON) REGISTER ADDRESS EBICON 0xFFF0_1000 31 30 R/W DESCRIPTION R/W EBI control register 29 28 RESERVED 23 22 21 14 13 0x0001_0000 27 26 25 24 EXBE3 EXBE2 EXBE1 EXBE0 19 18 17 16 REFEN REFMOD CLKEN 11 10 9 8 3 2 1 0 20 RESERVED 15 RESET VALUE 12 REFRAT 7 6 5 4 REFRAT BITS [31:28] WAITVT LITTLE DESCRIPTION RESERVED External IO bank 3 byte enable [27] EXBE3 This function is used for some devices that with hig
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION External IO bank 0 byte enable This bit function description is the same as EXBE3 above. [24] EXBE0 1 = nWBE[3:0] pin is byte enable signals, nWE will be used as write strobe signal to SRAM 0 = nWBE[3:0] pin is byte write strobe signal [23:19] RESERVED Enable SDRAM refresh cycle for SDRAM bank0 & bank1 [18] REFEN This bit set will start the auto-refresh cycle to SDRAM. The refresh rate is according to REFRAT bits.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION Valid time of nWAIT signal W90P710 recognizes the nWAIT signal at the next “nth” MCLK rising edge after the nOE or nWBE active cycle. WAITVT bits determine the n. [2:1] WAITVT [2:1] WAITVT 0 0 1 1 nth MCLK 0 1 0 1 1 2 3 4 Little Endian mode [0] After power on reset, the content of LITTLE is the Power-On Setting value from D14 pin. If pin D14 is pull-down, the external memory format is Big Endian mode.
W90P710CD/W90P710CDG BITS DESCRIPTION BASADDR Base address pointer of ROM/Flash bank The start address is calculated as ROM/Flash bank base pointer << 18. The base address pointer together with the “SIZE” bits constitutes the whole address range of each bank.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION Boot ROM/FLASH data bus width This ROM/Flash bank is designed for a boot ROM. BASADDR bits determine its start address. The external data bus width is determined by the data bus signals D [13:12] power-on setting.
W90P710CD/W90P710CDG Fig 6.3.3 ROM/FLASH Page Read Operation Timing Configuration Registers（SDCONF0/1） The configuration registers enable software to set a number of operating parameters for the SDRAM controller. There are two configuration registers SDCONF0、SDCONF1 for SDRAM bank 0、bank 1 respectively. Each bank can have a different configuration.
W90P710CD/W90P710CDG BITS DESCRIPTION [31:19] BASADDR [18:16] RESERVED [15] MRSET [14] RESERVED [13] AUTOPR Base address pointer of SDRAM bank 0/1 The start address is calculated as SDRAM bank 0/1 base pointer << 18. The SDRAM base address pointer together with the “SIZE” bits constitutes the whole address range of each SDRAM bank. SDRAM Mode register set command for SDRAM bank 0/1 This bit set will issue a mode register set command to SDRAM.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION Number of column address bits in SDRAM bank 0/1 Indicates the number of column address bits in external SDRAM bank 0/1.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 tRDL [10:8] [7:6] [5:3] 3 2 tRP BITS [31:11] tRCD 1 0 tRAS DESCRIPTION RESERVED - tRCD SDRAM bank 0/1, /RAS to /CAS delay tRCD [10:8] 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 tRDL SDRAM bank 0/1, Last data in to pre-charge command tRDL [7:6] MCLK 0 0 1 0 1 2 1 0 3 1 1 4 tRP MCLK 1 2 3 4 5 6 7 8 SDRAM bank 0/1, Row pre-charge ti
W90P710CD/W90P710CDG Continued. BITS [2:0] DESCRIPTION tRAS SDRAM bank 0/1, Row active time tRAS [2:0] 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Fig 6.3.4 Access timing 1 of SDRAM Fig 6.3.
W90P710CD/W90P710CDG External I/O Control Registers（EXT0CON – EXT3CON） The W90P710 supports an external device control without glue logic. It is very cost effective because address decoding and control signals timing logic are not needed. Using these control registers you can configure special external I/O devices for providing the low cost external devices control solution.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION Address bus alignment for external I/O bank 0~3 [15] ADRS When ADRS is set, external address (A21~A0) bus is alignment to byte address format, that is, A0 is internal AHB address bus HADDR[0] and A1 is AHB bus HADDR[1] and so forth. And it ignores DBWD [1:0] setting. Access cycles of external I/O bank 0~3 This parameter means nWE, nWBE and nOE active time clock. Detail timing diagram please refer to Fig. 6.3.6 and 6.3.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION Address set-up before nECS for external I/O bank 0~3 [7:5] tACS 0 0 0 0 1 1 1 1 tACS [7:5] 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MCLK 0 1 2 3 4 5 6 7 Chip selection set-up time of external I/O bank 0~3 When ROM/Flash memory bank is configured, the access to its bank stretches chip selection time before the nOE or new signal is activated.
W90P710CD/W90P710CDG Fig 6.3.6 External I/O write operation timing Fig 6.3.
W90P710CD/W90P710CDG 2Mx16 SRAM W90P710 A[21:0] A[21:0] D[31:0] DQ[15:0] nECSn nCS nWE nWE nOE nOE nWBE_SDQM[1] nUB nWBE_SDQM[0] nLB Fig. 6.3.
W90P710CD/W90P710CDG BITS DESCRIPTION Latch DLH_CLK clock tree by HCLK positive edge [31:16] DLH_CLK_REF [15:9] RESERVED The SDRAM MCLK is generated by inserting a delay (XOR2) chain in HCLK positive or negedge edge to adjust the MCLK skew. So software can read these bits to expore MCLK and HCLK relationship. [31:24] is used for positive edge and [23:16] is for negedge edge.
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG 6.4 Cache Controller The W90P710 incorporates a 4KB Instruction cache, 4KB Data cache and 8 words write buffer. The ICache and D-Cache have similar organization except the cache size. To raise the cache-hit ratio, these two caches are configured two-way set associative addressing. Each cache has four words cache line size. When a miss occurs, four words must be fetched consecutively from external memory. The replacement algorithm is a LRU (Least Recently Used).
W90P710CD/W90P710CDG 6.4.3 Instruction Cache The Instruction cache (I-cache) is a 4K bytes two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache access cycle begins with an instruction request from the instruction unit in the core. In the case of a cache hit, the instruction is delivered to the instruction unit.
W90P710CD/W90P710CDG Instruction Cache Load and Lock The W90P710 supports a cache-locking feature that can be used to lock critical sections of code into ICache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular instruction SRAM. Lines locked are not replaced during misses and not affected by flush per line command.
W90P710CD/W90P710CDG 6.4.4 Data Cache The W90P710 data cache (D-Cache) is a 4KB two-way set associative cache. The cache organization is 128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache is designed for buffer write-through mode of operation and a least recently used (LRU) replacement algorithm is used to select a line when no empty lines are available. When D-Cache is disabled, the cache memory is served as 4KB On-chip RAM.
W90P710CD/W90P710CDG Write Hit：Data is written into both the cache and write buffer. The processor then continues to access the cache, while the cache controller simultaneously downloads the contents of the write buffer to main memory. This reduces the effective write memory cycle time from the time required for a main memory cycle to the cycle time of the high-speed cache. Write Miss：Data is only written into write buffer, not to the cache (write no allocate).
W90P710CD/W90P710CDG The unlock all operation is used to unlock the whole D-Cache. This operation is performed on all cache lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA and DCAH bits. 6.4.5 Write Buffer The W90P710 provides a write buffer to improve system performance. The write buffer can buffer up to eight words of data.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 WRBEN DCAEN ICAEN RESERVED 23 22 21 20 RESERVED 15 14 13 12 RESERVED 7 6 5 4 RESERVED BITS [31:3] DESCRIPTION RESERVED Write buffer enable [2] WRBEN Write buffer is disabled after reset. 1 = Enable write buffer 0 = Disable write buffer D-Cache enable [1] DCAEN D-Cache is disabled after reset.
W90P710CD/W90P710CDG REGISTER ADDRESS CAHCON 0xFFF0_2004 31 30 R/W DESCRIPTION RESET VALUE R/W Cache control register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 RESERVED 23 22 21 20 RESERVED 15 14 13 12 RESERVED 7 6 5 4 3 2 1 0 DRWB ULKS ULKA LDLK FLHS FLHA DCAH ICAH BITS DESCRIPTION [31:8] RESERVED [7] DRWB [6] ULKS [5] ULKA Drain write buffer Forces write buffer data to be written to main memory.
W90P710CD/W90P710CDG NOTE：When using the FLHA or ULKA command, you can set both ICAH and DCAH bits to execute entire I-Cache and D-Cache flushing or unlocking. But, FLHS and ULKS commands can only be executed with a cache line specified by CAHADR register in I-Cache or D-Cache at a time. If you set both ICAH and DCAH bits, and set FLHS or ULKS command bit, it will be treated as an invalid command and no operation is done and the command terminates with no exception.
W90P710CD/W90P710CDG Cache Test Register 0 (CTEST0) Cache test control register that configures the cache and tag ram testing enable or disable. In addition, this register controls the built-in-self-test (BIST) function of SRAM.
W90P710CD/W90P710CDG Cache Test Register 1 (CTEST1) Cache Test Register that will be read back to provide the status of cache RAM BIST. Whether the BIST is finish and all of bank of SRAM are tested successfully will be presented in this register.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION BIST test fail for data cache ram way 0 [2] BFAIL2 If this bit equals to “1”, it indicates the data cache ram for way 0 is tested fail by BIST. “0” means the test is passed. BIST test fail for instruction cache ram way 1 [1] BFAIL1 [0] BFAIL0 If this bit equals to “1”, it indicates the instruction cache ram for way 1 is tested fail by BIST. “0” means the test is passed. BIST test fail for instruction cache ram way 0 6.
W90P710CD/W90P710CDG 6.5.1 EMC Functional Description MII Management State Machine The MII management function of EMC is compliant to IEEE 802.3 Std. Through the MII management interface, software can access the control and status registers of the external PHY chip. Tow programmable register MIID (MAC MII Management Data Register) and MIIDA (MAC MII Management Data Control and Address Register) are for MII management function.
W90P710CD/W90P710CDG EMC Descriptors A link-list data structure named as descriptor is used to keep the control, status and data information of each frame. Through the descriptor, CPU and EMC exchange the information for frame reception and transmission. Two different descriptors are defined in W90P710. One named as Rx descriptor for frame reception and the other names as Tx descriptor for frame transmission. Each Rx descriptor consists of four words.
W90P710CD/W90P710CDG If the O=2’b00 indicates the CPU is the owner of Rx descriptor. After the CPU completes processing the frame, it modifies the ownership field to 2’b10 and releases the Rx descriptor to EMC RxDMA. Rx Status [29:16]: Receive Status This field keeps the status for frame reception. All status bits are updated by EMC. In the receive status, bits 29 to 23 are undefined and reserved for the future.
W90P710CD/W90P710CDG RXINTR [16]: Receive Interrupt The RXINTR indicates the frame stored in the data buffer pointed by Rx descriptor caused an interrupt condition. 1’b0: The frame doesn’t cause an interrupt. 1’b1: The frame caused an interrupt. RBC [15:0]: Receive Byte Count The RBC indicates the byte count of the frame stored in the data buffer pointed by Rx descriptor. The four bytes CRC field is also included in the receive byte count.
W90P710CD/W90P710CDG Rx Descriptor Word 2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved The Rx descriptor word 2 keeps obsolete information for MAC translation. Therefore, these information bits are undefined and should be ignored.
W90P710CD/W90P710CDG 6.5.1.
W90P710CD/W90P710CDG CRCApp [1]: CRC Append The CRCApp control the CRC append during frame transmission. If CRCApp is enabled, the 4-bytes CRC checksum will be appended to frame at the end of frame transmission. 1’b0: 4-bytes CRC appending is disabled. 1’b1: 4-bytes CRC appending is enabled. PadEN [0]: Padding Enable The PadEN control the PAD bits appending while the length of transmission frame is less than 60 bytes. If PadEN is enabled, EMC does the padding automatically.
W90P710CD/W90P710CDG Tx Descriptor Word 2 31 30 29 28 CCNT 27 26 25 24 Reserved SQE PAU TXHA 23 22 21 20 19 18 17 16 LC TXABT NCS EXDEF TXCP Reserved DEF TXINTR 15 14 13 12 11 10 9 8 3 2 1 0 TBC 7 6 5 4 TBC CCNT [31:28]: Collision Count The CCNT indicates the how many collision occurred consecutively during a packet transmission. If the packet incurred 16 consecutive collisions during transmission, the CCNT will be 4’h0 and bit TXABT will be set to 1.
W90P710CD/W90P710CDG LC [23]: Late Collision The LC indicates the collision occurred in the outside of 64 bytes collision window. This means after the 64 bytes of a frame has transmitted out to the network, the collision still occurred. The late collision check will only be done while EMC is operating on half-duplex mode. 1’b0: No collision occurred in the outside of 64 bytes collision window. 1’b1: Collision occurred in the outside of 64 bytes collision window.
W90P710CD/W90P710CDG TXINTR [16]: Transmit Interrupt The TXINTR indicates the packet transmission caused an interrupt condition. 1’b0: The packet transmission doesn’t cause an interrupt. 1’b1: The packet transmission caused an interrupt. TBC [15:0]: Transmit Byte Count The TBC indicates the byte count of the frame stored in the data buffer pointed by Tx descriptor for transmission.
W90P710CD/W90P710CDG 6.5.2 EMC Register Mapping The EMC implements many registers and the registers are separated into three types, the control registers, the status registers and diagnostic registers. The control registers are used by S/W to pass control information to EMC. The status registers are used to keep EMC operation status for S/W. And, the diagnostic registers are used for debug only.
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG 6.5.2.1 Register Details CAM Command Register (CAMCMR) The EMC of W90P710 supports CAM function for destination MAC address recognition. The CAMCMR control the CAM comparison function, and unicast, multicast, and broadcast packet reception.
W90P710CD/W90P710CDG Continued. BITS [2] DESCRIPTIONS ABP The Accept Broadcast Packet controls the broadcast packet reception. If ABP is enabled, EMC receives all incoming packet it’s destination MAC address is a broadcast address. 1’b0: EMC receives packet depends on the CAM comparison result. 1’b1: EMC receives all broadcast packets. [1] AMP The Accept Multicast Packet controls the multicast packet reception.
W90P710CD/W90P710CDG ECMP CCAM AUP AMP ABP RESULT 0 0 0 0 0 No Packet 0 0 0 0 1 B 0 0 0 1 0 M 0 0 0 1 1 M B 0 0 1 0 0 C U 0 0 1 0 1 C U B 0 0 1 1 0 C U M 0 0 1 1 1 C U M B 0 1 0 0 0 C U M B 0 1 0 0 1 C U M B 0 1 0 1 0 C U M B 0 1 0 1 1 C U M B 0 1 1 0 0 C U M B 0 1 1 0 1 C U M B 0 1 1 1 0 C U M B 0 1 1 1 1 C U M B 1 0 0 0 0 C 1 0 0 0 1 C B 1 0 0 1 0 C M
W90P710CD/W90P710CDG CAM Enable Register (CAMEN) The CAMEN controls the validation of each CAM entry. Each CAM entry must be enabled first before it can participate in the destination MAC address recognition.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS CAM entry 9 is enabled [9] CAM9EN 1’b0: CAM entry 9 disabled. 1’b1: CAM entry 9 enabled. CAM entry 8 is enabled [8] CAM8EN 1’b0: CAM entry 8 disabled. 1’b1: CAM entry 8 enabled. CAM entry 7 is enabled [7] CAM7EN 1’b0: CAM entry 7 disabled. 1’b1: CAM entry 7 enabled. CAM entry 6 is enabled [6] CAM6EN 1’b0: CAM entry 6 disabled. 1’b1: CAM entry 6 enabled. CAM entry 5 is enabled [5] CAM5EN 1’b0: CAM entry 5 disabled. 1’b1: CAM entry 5 enabled.
W90P710CD/W90P710CDG CAM Entry Registers (CAMxx) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM0M CAM0L 0xFFF0_3008 0xFFF0_300C R/W R/W CAM0 Most Significant Word Register CAM0 Least Significant Word Register 0x0000_0000 0x0000_0000 CAM1M 0xFFF0_3010 R/W CAM1 Most Significant Word Register 0x0000_0000 CAM1L 0xFFF0_3014 R/W CAM1 Least Significant Word Register 0x0000_0000 CAM2M 0xFFF0_3018 R/W CAM2 Most Significant Word Register 0x0000_0000 CAM2L 0xFFF0_301C R/W CAM2 Least Signi
W90P710CD/W90P710CDG CAMxM 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 MAC Address Byte 5 (MSB) 23 22 21 20 19 MAC Address Byte 4 15 14 13 12 11 MAC Address Byte 3 7 6 5 4 3 MAC Address Byte 2 BITS [31:0] DESCRIPTIONS CAMxM The CAMxM(CAMx Most Significant Word) keeps the bit 47~16 of MAC address. The x can be the 0~14. The register pair {CAMxM, CAMxL} represents a CAM entry and can keep a MAC address.
W90P710CD/W90P710CDG CAMxL 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 MAC Address Byte 1 23 22 21 20 19 MAC Address Byte 0 (LSB) 15 14 13 12 11 Reserved 7 6 5 4 3 Reserved BITS DESCRIPTIONS [31:16] CAMxL The CAMxL(CAMx Least Significant Word) keeps the bit 15~0 of MAC address. The x can be the 0~14. The register pair {CAMxM, CAMxL} represents a CAM entry and can keep a MAC address.
W90P710CD/W90P710CDG BITS DESCRIPTIONS Length/Type Field of PAUSE Control Frame [31:0] Length/Type In the PAUSE control frame, a length/type field is defined and will be 16’h8808. OP Code Field of PAUSE Control Frame [15:0] OP-Code In the PAUSE control frame, an op code field is defined and will be 16’h0001.
W90P710CD/W90P710CDG Transmit Descriptor Link List Start Address Register (TXDLSA) The Tx descriptor defined in EMC is a link-list data structure. The TXDLSA keeps the starting address of this link-list. In other words, the TXDLSA keeps the starting address of the 1st Tx descriptor. S/W must configure TXDLSA before enable bit TXON of MCMDR register.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 RXDLSA 23 22 21 20 19 RXDLSA 15 14 13 12 11 RXDLSA 7 6 5 4 3 RXDLSA BITS [31:0] DESCRIPTIONS The RXDLSA(Receive Descriptor Link-List Start Address) keeps the start address of receive descriptor link-list. If the S/W enables the bit RXON of MCMDR register, the content of RXDLSA will be loaded into the current receive descriptor start address register (CRXDSA). The RXDLSA doesn’t be updated by EMC.
W90P710CD/W90P710CDG BITS [31:25] [24] DESCRIPTIONS Reserved SWR The SWR (Software Reset) implements a reset function to make the EMC return default state. The SWR is a self-clear bit. This means after the software reset finished, the SWR will be cleared automatically. Enable SWR can also reset all control and status registers, except for OPMOD bit of MCMDR register. The EMC re-initial is needed after the software reset completed. 1’b0: Software reset completed. 1’b1: Enable software reset.
W90P710CD/W90P710CDG Continued. BITS [17] DESCRIPTIONS EnSQE The Enable SQE Checking controls the enable of SQE checking. The SQE checking is only available while EMC is operating on 10M bps and half duplex mode. In other words, the EnSQE cannot affect EMC operation, if the EMC is operating on 100M bps or full duplex mode. 1’b0: Disable SQE checking while EMC is operating on 10Mbps and half duplex mode. 1’b1: Enable SQE checking while EMC is operating on 10Mbps and half duplex mode.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS The Frame Transmission ON controls the normal packet transmission of EMC. If the TXON is set to high, the EMC starts the packet transmission process, including the Tx descriptor fetching, packet transmission and Tx descriptor modification. [8] TXON It is must to finish EMC initial sequence before enable TXON. Otherwise, the EMC operation is undefined.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS The Accept Runt Packet controls the runt packet, which length is less than 64 bytes, reception. If the ARP is set to high, the EMC will accept the runt packet. [2] ARP Otherwise, the runt packet will be dropped. 1’b0: The runt packet will be dropped by EMC. 1’b1: The runt packet will be accepted by EMC. The Accept Long Packet controls the long packet, which packet length is greater than 1518 bytes, reception.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 19 Reserved 15 14 13 12 MIIData 7 6 5 4 MIIData BITS [31:16] [15:0] DESCRIPTIONS Reserved - MIIData The MII Management Data is the 16 bits data that will be written into the registers of external PHY for MII Management write command or the data from the registers of external PHY for MII Management read command.
W90P710CD/W90P710CDG BITS [31:24] DESCRIPTIONS Reserved The MDC Clock Rating controls the MDC clock rating for MII Management I/F. [23:20] MDCCR Depend on the IEEE Std. 802.3 clause 22.2.2.11, the minimum period for MDC shall be 400ns. In other words, the maximum frequency for MDC is 2.5MHz. The MDC is divided from the AHB bus clock, the HCLK. Consequently, for different HCLKs the different ratios are required to generate appropriate MDC clock.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS The PHY Address keeps the address to differentiate which external PHY is the target of the MII management command. [12:8] PHYAD [7:5] Reserved - [4:0] PHYRAD The PHY Register Address keeps the address to indicate which register of external PHY is the target of the MII management command.
W90P710CD/W90P710CDG Management frame fields PRE ST OP PHYAD REGAD TA DATA IDLE READ 1…1 01 10 AAAAA RRRRR Z0 DDDDDDDDDDDDDDDD Z WRITE 1…1 01 01 AAAAA RRRRR 10 DDDDDDDDDDDDDDDD Z MII Management Function Configure Sequence READ WRITE 1. Set appropriate MDCCR. 1. Write data to MIID register 2. Set PHYAD and PHYRAD. 2. Set appropriate MDCCR. 3. Set Write to 1’b0 3. Set PHYAD and PHYRAD. 4. Set bit BUSY to 1’b1 to send a MII management frame out. 4.
W90P710CD/W90P710CDG BITS [31:22] DESCRIPTIONS Reserved [21:20] Blength [19:10] Reserved [9:8] TxTHD The DMA Burst Length defines the burst length of AHB bus cycle while EMC accesses system memory. 2’b00: 4 words 2’b01: 8 words 2’b10: 16 words 2’b11: 16 words The TxFIFO Low Threshold controls when TxDMA requests internal arbiter for data transfer between system memory and TxFIFO. The TxTHD defines not only the low threshold of TxFIFO, but also the high threshold.
W90P710CD/W90P710CDG Transmit Start Demand Register (TSDR) If the Tx descriptor is not available for use of TxDMA after the TXON of MCMDR register is enabled, the FSM (Finite State Machine) of TxDMA enters the Halt state and the frame transmission is halted. After the S/W has prepared the new Tx descriptor for frame transmission, it must issue a write command to TSDR register to make TxDMA leave Halt state and contiguous frame transmission.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 19 Reserved 15 14 13 12 RXMS 7 6 5 4 RXMS BITS [31:16] [15:0] DESCRIPTIONS Reserved - RXMS The Maximum Receive Frame Length defines the maximum frame length for received frame. If the frame length of received frame is greater than RXMS, and bit EnDFO of MIEN register is also enabled, the bit DFOI of MISTA register is set and the Rx interrupt is triggered.
W90P710CD/W90P710CDG BITS [31:25] [24] DESCRIPTIONS Reserved - EnTxBErr The Enable Transmit Bus Error Interrupt controls the TxBErr interrupt generation. If TxBErr of MISTA register is set, and both EnTxBErr and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnTxBErr or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the TxBErr of MISTA register is set. 1’b0: TxBErr of MISTA register is masked from Tx interrupt generation.
W90P710CD/W90P710CDG Continued. BITS [20] DESCRIPTIONS EnNCS The Enable No Carrier Sense Interrupt controls the NCS interrupt generation. If NCS of MISTA register is set, and both EnNCS and EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If EnNCS or EnTXINTR is disabled, no Tx interrupt is generated to CPU even the NCS of MISTA register is set. 1’b0: NCS of MISTA register is masked from Tx interrupt generation. 1’b1: NCS of MISTA register can participate in Tx interrupt generation.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS The EnTXINTR controls the Tx interrupt generation. [16] EnTXINTR If Enable Transmit Interrupt is enabled and TXINTR of MISTA register is high, EMC generates the Tx interrupt to CPU. If EnTXINTR is disabled, no Tx interrupt is generated to CPU even the status bits 17~24 of MISTA are set and the corresponding bits of MIEN are enabled. In other words, if S/W wants to receive Tx interrupt from EMC, this bit must be enabled.
W90P710CD/W90P710CDG Continued. BITS [9] DESCRIPTIONS EnDEN The Enable DMA Early Notification Interrupt controls the DENI interrupt generation. If DENI of MISTA register is set, and both EnDEN and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnDEN or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the DENI of MISTA register is set. 1’b0: DENI of MISTA register is masked from Rx interrupt generation.
W90P710CD/W90P710CDG Continued. BITS [4] DESCRIPTIONS EnRXGD The Enable Receive Good Interrupt controls the RXGD interrupt generation. If RXGD of MISTA register is set, and both EnRXGD and EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If EnRXGD or EnTXINTR is disabled, no Rx interrupt is generated to CPU even the RXGD of MISTA register is set. 1’b0: RXGD of MISTA register is masked from Rx interrupt generation. 1’b1: RXGD of MISTA register can participate in Rx interrupt generation.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS The Enable Receive Interrupt controls the Rx interrupt generation. [0] If EnRXINTR is enabled and RXINTR of MISTA register is high, EMC generates the Rx interrupt to CPU. If EnRXINTR is disabled, no Rx interrupt is generated to CPU even the status bits 1~14 of MISTA are set and the corresponding bits of MIEN are enabled. In other words, if S/W wants to receive Rx interrupt from EMC, this bit must be enabled.
W90P710CD/W90P710CDG BITS [31:25] DESCRIPTIONS Reserved The Transmit Bus Error Interrupt high indicates the memory controller replies ERROR response while EMC access system memory through TxDMA during packet transmission process. Reset EMC is recommended while TxBErr status is high. [24] TxBErr If the TxBErr is high and EnTxBErr of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TxBErr status. 1’b0: No ERROR response is received. 1’b1: ERROR response is received.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS The Transmit Abort Interrupt high indicates the packet incurred 16 consecutive collisions during transmission, and then the transmission process for this packet is aborted. The transmission abort is only available while EMC is operating on half-duplex mode. [21] TXABT If the TXABT is high and EnTXABT of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TXABT status.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS The Transmit Completion Interrupt indicates the packet transmission has completed correctly. [18] TXCP If the TXCP is high and EnTXCP of MIEN register is enabled, the TxINTR will be high. Write 1 to this bit clears the TXCP status. 1’b0: The packet transmission doesn’t complete. 1’b1: The packet transmission has completed. [17] TXEMP The Transmit FIFO Underflow Interrupt high indicates the TxFIFO underflow occurred during packet transmission.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS The Control Frame Receive Interrupt high indicates EMC receives a flow control frame. The CFR only available while EMC is operating on full duplex mode. [14] CFR If the CFR is high and EnCFR of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the CFR status. 1’b0: The EMC doesn’t receive the flow control frame. 1’b1: The EMC receives a flow control frame.
W90P710CD/W90P710CDG Continued. BITS [8] DESCRIPTIONS DFOI The Maximum Frame Length Interrupt high indicates the length of the incoming packet has exceeded the length limitation configured in DMARFC register and the incoming packet is dropped. If the DFOI is high and EnDFO of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the DFOI status. 1’b0: The length of the incoming packet doesn’t exceed the length limitation configured in DMARFC.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS The Receive Good Interrupt high indicates the frame reception has completed. [4] RXGD If the RXGD is high and EnRXGD of MIEN register is enabled, the RxINTR will be high. Write 1 to this bit clears the RXGD status. 1’b0: The frame reception has not complete yet. 1’b1: The frame reception has completed. The Packet Too Long Interrupt high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS The Receive Interrupt indicates the Rx interrupt status. If RXINTR high and its corresponding enable bit, EnRXINTR of MISTA register, is also high indicates the EMC generates Rx interrupt to CPU. If RXINTR is high but EnRXINTR of MISTA is disabled, no Rx interrupt is generated. [0] The RXINTR is logic OR result of the bits 1~14 in MISTA register do logic AND with the corresponding bits in MIEN register.
W90P710CD/W90P710CDG BITS [31:12] DESCRIPTIONS Reserved - TXHA The Transmission Halted high indicates the next normal packet transmission process will be halted because the bit TXON of MCMDR is disabled be S/W. 1’b0: Next normal packet transmission process will go on. 1’b1: Next normal packet transmission process will be halted. SQE The Signal Quality Error high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode.
W90P710CD/W90P710CDG Missed Packet Count Register (MPCNT) The MPCNT keeps the number of packets that were dropped due to various types of receive errors. The MPCNT is a read clear register. In addition, S/W also can write an initial value to MPCNT and the missed packet counter will start counting from that initial value. If the missed packet counter is overflow, the MMP of MISTA will be set.
W90P710CD/W90P710CDG REGISTER ADDRESS R/W MRPC 0xFFF0_30BC R 31 30 29 DESCRIPTION RESET VALUE MAC Receive Pause Count Register 28 27 0x0000_0000 26 25 24 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 19 Reserved 15 14 13 12 MRPC 7 6 5 4 MRPC BITS DESCRIPTIONS [31:16] Reserved [15:0] MRPC The MAC Receive Pause Count keeps the operand field of the PAUSE control frame. It indicates how many slot time (512 bit time) the Tx of EMC will be paused.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 MRPCC 7 6 5 4 3 MRPCC BITS [31:16] [15:0] DESCRIPTIONS Reserved - MRPCC The MAC Receive Pause Current Count shows the current value of that down count timer.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:16] Reserved [15:0] MREPC The MAC Remote Pause Count shows the current value of the down count timer that starts to count down from the value of operand of the transmitted PAUSE control frame. DMA Receive Frame Status Register (DMARFS) The DMARFS is used to keep the Length/Type field of each incoming Ethernet packet. This register is writing clear and writes 1 to corresponding bit clears the bit.
W90P710CD/W90P710CDG Current Transmit Descriptor Start Address Register (CTXDSA) The CTXDSA keeps the start address of Tx descriptor that is used by TxDMA currently. The CTXDSA is read only and write to this register has no effect.
W90P710CD/W90P710CDG BITS [31:0] DESCRIPTIONS CTXBSA Current Transmit Buffer Start Address Current Receive Descriptor Start Address Register (CRXDSA) The CRXDSA keeps the start address of Rx descriptor that is used by RxDMA currently. The CRXDSA is read only and write to this register has no effect.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 CRXBSA 23 22 21 20 19 CRXBSA 15 14 13 12 11 CRXBSA 7 6 5 4 3 CRXBSA BITS [31:0] DESCRIPTIONS CRXBSA Current Receive Buffer Start Address Receive Finite State Machine Register (RXFSM) The RXFSM shows the current value of the FSM (Finite State Machine) of RxDMA and RxFIFO controller. The RXFSM is read only and write to it has no effect. The RXFSM is used only for debug.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:23] RX_FSM RxDMA FSM [22] Reserved - [21:16] RXBuf_FSM Receive Buffer FSM [15:12] RXFetch_FSM Receive Descriptor Fetch FSM [11:8] RXClose_FSM Receive Descriptor Close FSM [7:0] RFF_FSM RxFIFO Controller FSM Transmit Finite State Machine Register (TXFSM) The TXFSM shows the current value of the FSM (Finite State Machine) of TxDMA and TxFIFO controller. The TXFSM is read only and write to it has no effect. The TXFSM is used only for debug.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:24] TX_FSM TxDMA FSM [23:22] Reserved - [21:16] TXBuf_FSM [15:12] TXFetch_FSM Transmit Descriptor Fetch FSM [11:8] TXClose_FSM Transmit Descriptor Close FSM [7:5] Reserved - [4:0] TFF_FSM TxFIFO Controller FSM Transmit Buffer FSM Finite State Machine Register 0 (FSM0) The FSM0 shows the current value of the FSM (Finite State Machine) of the function module in EMC. The FSM0 is read only and write to it has no effect.
W90P710CD/W90P710CDG Finite State Machine Register 1 (FSM1) The FSM1 shows the current value of the FSM (Finite State Machine) of the function module in EMC. The FSM1 is read only and write to it has no effect. The FSM1 is used only for debug.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 Reserved 23 22 21 20 19 Enable 15 Reserved 14 13 12 11 Reserved 7 6 5 4 3 Out Config BITS [31:24] DESCRIPTIONS Reserved The Function Enable outputs two function enable signals to external stimulus circuit. [23:22] Enable [21:8] Reserved [7:6] Out The Flag Out provides two output flags to trigger Logic Analyzer for debug. These two bits can be written at any time.
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG Debug Mode MAC Information Register (DMMIR) The DMMIR keeps the information of MAC module for debug.
W90P710CD/W90P710CDG BITS [31:5] [3:2] DESCRIPTIONS Reserved BistFail The BIST Fail indicates if the BIST test fails or succeeds. If the BistFail is low at the end, the embedded SRAM pass the BIST test, otherwise, it is faulty. The BistFail will be high once the BIST detects the error and remains high during the BIST operation. If BistFail[2] high indicates the embedded SRAM for TxFIFO BIST test failed. If BistFail[3] high indicates the embedded SRAM for RxFIFO BIST test failed.
W90P710CD/W90P710CDG 6.6 GDMA Controller The W90P710 has a two-channel general DMA controller, called the GDMA. The two-channel GDMA performs the following data transfers without the CPU intervention: y Memory-to-memory (memory to/from memory) y Memory –to – IO y IO- to -memory The on-chip GDMA can be started by the software or external DMA request nXDREQ. Software can also be used to restart the GDMA operation after it has been stopped.
W90P710CD/W90P710CDG 6.6.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31] RESERVED - [30:28] TC_WIDTH nRTC/nWTC active width selection, from 1 to 7 HCLK cycles. [27:26] REQ_SEL External request pin selection, if GDMAMS [3:2]=00, REQ_SEL will be don’t care. If REQ_SEL [27:26]=00, external request don’t use. If REQ_SEL [27:26]=01, use nXDREQ. If REQ_SEL [27:26]=10, external request don’t use. If REQ_SEL [27:26]=11, external request don’t use. [25] REQ_ATV nXDREQ High/Low active selection 1’b0 = nXDREQ is LOW active.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS AUTOIEN Auto initialization Enable 1’b0 = Disables auto initialization 1’b1 = Enables auto initialization, the GDMA_CSRC0/1, GDMA_CDST0/1,and GDMA_CTCNT0/1 registers are updated by the GDMA_SRC0/1,GDMA_DST0/1,and GDMA_TCNT0/1 registers automatically when transfer is complete. [18] TC Terminal Count 1’b0 = Channel does not expire 1’b1 = Channel expires; this bit is set only by GDMA hardware, and clear by software to write logic 0.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS [11] SBMS [10] Reserved Single/Block Mode Select 1’b0 = Selects single mode. It requires an external GDMA request for every incurring GDMA operation. 1’b1 = Selects block mode. It requires a single external GDMA request during the atomic GDMA operation. An atomic GDMA operation is defined as the sequence of GDMA operations until the transfer count register reaches zero.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS [4] Destination Address Direction 1’b0 = Destination address is incremented successively 1’b1 = Destination address is decremented successively DADIR [3:2] GDMAMS GDMA Mode Select 00 = Software mode (memory-to-memory) 01 = External nXDREQ mode for external device 10 = Reserved 11 = Reserved [1] Reserved - GDMAEN GDMA Enable 1’b0 = Disables the GDMA operation 1’b1 = Enables the GDMA operation; this bit will be clear automatically when the transfer
W90P710CD/W90P710CDG Channel 0/1 Destination Base Address Register (GDMA_DSTB0, DMA_DSTB1) Channel 0/1 Destination Base Address Register (GDMA_DSTB0, GDMA_DSTB1) The GDMA channel starts writing its data to the destination address as defined in this destination base address register. During a block transfer, the GDMA determines successive destination addresses by adding to or subtracting from the destination base address.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:24] Reserved - [23:0] TFR_CNT The TFR_CNT represents the required number of GDMA transfers. The maximum transfer count is 16M –1.
W90P710CD/W90P710CDG Channel 0/1 Current Destination Register (GDMA_CDST0, GDMA_CDST1) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GDMA_CDST0 0xFFF0_4014 R Channel 0 Current Destination Address Register 0x0000_0000 GDMA_CDST1 0xFFF0_4034 R Channel 1 Current Destination Address Register 0x0000_0000 31 30 23 22 15 14 7 6 29 28 27 CURRENT_DST_ADDR [31:24] 21 20 19 CURRENT_DST_ADDR [23:16] 13 12 11 CURRENT_DST_ADDR [15:8] 5 4 3 CURRENT_DST_ADDR [7:0] BITS [31:0] 26 25 24 18 17 1
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 Reserved 23 22 15 14 7 6 21 20 19 CURENT_TFR_CNT [23:16] 13 12 11 CURRENT_TFR_CNT [15:8] 5 4 3 CURRENT_TFR_CNT [7:0] BITS DESCRIPTIONS [31:24] Reserved [23:0] CURRENT_TFR_CNT Current Transfer Count register The current transfer count register indicates the number of transfer being performed - 170 -
W90P710CD/W90P710CDG 6.7 USB Host Controller The Universal Serial Bus (USB) is a low-cost, low-to-mid-speed peripheral interface standard intended for modem, scanners, PDAs, keyboards, mice, and other devices that do not require a highbandwidth parallel interface. The USB is a 4-wire serial cable bus that supports serial data exchange between a Host Controller and a network of peripheral devices. The attached peripherals share USB bandwidth through a host-scheduled, token-based protocol.
W90P710CD/W90P710CDG Interrupt Processing Interrupts are the communication method for HC-initiated communication with the Host Controller Driver. There are several events that may trigger an interrupt from the Host Controller. Each specific event sets a specific bit in the HcInterruptStatus register. Host Controller Bus Master The Host Controller Bus Master is the central block in the data path. The Host Controller Bus Master coordinates all access to the AHB Interface.
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG Host Controller Revision Register REGISTER OFFSET ADDRESS R/W HcRevision 0xFFF0_5000 R 31 30 29 23 22 21 15 14 13 7 6 5 RESET VALUE DESCRIPTION Host Controller Revision Register 28 27 Reserved 20 19 Reserved 12 11 Reserved 4 3 Revision BITS 0x0000_0010 26 25 24 18 17 16 10 9 8 2 1 0 DESCRIPTION [31:8] Reserved Reserved. Read/Write 0's [7:0] Revision Indicates the Open HCI Specification revision number implemented by the Hardware.
W90P710CD/W90P710CDG BITS DESCRIPTION [31:11] Reserved [10] RWCE [9] RWC Reserved. Read/Write 0's RemoteWakeupConnectedEnable [8] [7:6] [5] [4] [3] [2] [1:0] INR HCFS BLE CLE ISE PLE CBR If a remote wakeup signal is supported, this bit enables that operation. Since there is no remote wakeup signal supported, this bit is ignored. RemoteWakeupConnected This bit indicated whether the HC supports a remote wakeup signal. This implementation does not support any such signal.
W90P710CD/W90P710CDG Host Controller Command Status Register REGISTER ADDRESS HcCommandStatus 0xFFF0_5008 R/W RESET VALUE DESCRIPTION R/W Host Controller Command Status Register 31 30 29 28 23 22 21 15 14 20 Reserved 13 12 7 6 5 4 Reserved BITS 0x0000_0000 27 26 25 24 Reserved 19 18 17 16 10 9 8 2 BLF 1 CLF 0 HCR 11 Reserved 3 OCR DESCRIPTION [31:18] Reserved [17:16] SOC [15:4] Reserved [3] OCR Reserved ScheduleOverrunCount This field is increment every time th
W90P710CD/W90P710CDG Host Controller Interrupt Status Register All bits are set by hardware and cleared by software.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION WritebackDoneHead [1] WDH Set after the Host HccaDoneHead. Controller has written HcDoneHead to SchedulingOverrun [0] SCHO Set when the List Processor determines a Schedule Overrun has occurred. Host Controller Interrupt Enable Register Writing a ‘1’ to a bit in this register sets the corresponding bit, while writing a ‘0’ leaves the bit unchanged.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION FrameNumberOverflowEnable [5] FNOE 0: Ignore 1: Enable interrupt generation due to Frame Number Overflow. [4] UnrecoverableErrorEnable UREE This event is not implemented. All writes to this bit are ignored. ResumeDetectedEnable [3] RDTE 0: Ignore 1: Enable interrupt generation due to Resume Detected. StartOfFrameEnable [2] SOFE 0: Ignore 1: Enable interrupt generation due to Start of Frame.
W90P710CD/W90P710CDG BITS [31] DESCRIPTION MIE MasterInterruptEnable Global interrupt disable. A write of ‘1’ disables all interrupts. OwnershipChangeEnable [30] OCE 0: Ignore 1: Disable interrupt generation due to Ownership Change. [29:7] Reserved Reserved. Read/Write 0's RootHubStatusChangeEnable [6] RHSCE 0: Ignore 1: Disable interrupt generation due to Root Hub Status Change. FrameNumberOverflowEnable [5] FNOE 0: Ignore 1: Disable interrupt generation due to Frame Number Overflow.
W90P710CD/W90P710CDG Host Controller Communication Area Register REGISTER ADDRESS HcHCCA 0xFFF0_5018 31 30 R/W RESET VALUE DESCRIPTION R/W Host Controller Communication Area Register 0x0000_0000 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 Reserved 2 1 0 HCCA 23 22 21 20 HCCA 15 14 13 12 7 6 5 4 HCCA BITS DESCRIPTION HCCA [31:8] [7:0] HCCA Pointer to HCCA base address.
W90P710CD/W90P710CDG Host Controller Control Head ED Register REGISTER ADDRESS HcControlHeadED 31 0xFFF0_5020 30 R/W DESCRIPTION RESET VALUE R/W Host Controller Control Head ED Register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHED 23 22 21 20 CHED 15 14 13 12 7 6 5 4 CHED CHED Reserved BITS DESCRIPTION ControlHeadED [31:4] CHED [3:0] Reserved Pointer to the Control List Head ED.
W90P710CD/W90P710CDG Host Controller Bulk Head ED Register OFFSET ADDRESS REGISTER HcBulkHEADED 0xFFF0_5028 31 30 R/W RESET VALUE DESCRIPTION R/W Host Controller Bulk Head ED Register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BHED 23 22 21 20 15 14 13 12 7 6 5 4 BHED BHED BHED Reserved BITS DESCRIPTION [31:4] BHED [3:0] Reserved BulkHeadED. Pointer to the Bulk List Head ED. Reserved.
W90P710CD/W90P710CDG Host Controller Done Head Register REGISTER ADDRESS HcDoneHead 0xFFF0_5030 31 30 R/W RESET VALUE DESCRIPTION R/W Host Controller Done Head Register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DOHD 23 22 21 20 15 14 13 12 7 6 5 4 DOHD DOHD DOHD Reserved BITS DESCRIPTION [31:4] DOHD [3:0] Reserved DoneHead. Pointer to the current Done List Head ED. Reserved.
W90P710CD/W90P710CDG BITS DESCRIPTION 31 FrameIntervalToggle FINTVT This bit is toggled by HCD when it loads a new value into Frame Interval. FSLargestDataPacket [30:16] FSLDP [15:14] Reserved [13:0] FINTV This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. Reserved. Read/Write 0's Frame Interval This field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here.
W90P710CD/W90P710CDG Host Controller Frame Number Register REGISTER ADDRESS R/W HcFmNumber 0xFFF0_503C R 31 30 29 RESET VALUE DESCRIPTION Host Controller Frame Number Register 28 27 0x0000_0000 26 25 24 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 15 14 13 12 7 6 5 4 19 Reserved FRMN FRMN BITS [31:16] DESCRIPTION Reserved Reserved.
W90P710CD/W90P710CDG BITS DESCRIPTION [31:14] Reserved Reserved. Read/Write 0's PeriodicStart [13:0] PERST This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 POTPGT 23 22 21 20 19 Reserved 15 14 13 Reserved 7 6 5 12 11 10 9 8 OCPM OCPM DEVT NPSW PSWM 3 2 1 0 4 NDSP BITS DESCRIPTION PowerOnToPowerGoodTime [31:24] [23:13] POTPGT Reserved This field value is represented as the number of 2 ms intervals, which ensuring that the power switching is effective within 2 ms. Only bits [25:24] is implemented as R/W. The remaining bits are read only as ‘0’.
W90P710CD/W90P710CDG Host Controller Root Hub Descriptor B Register This register is only reset by a power-on reset. It is written during system initialization to configure the Root Hub. These bits should not be written during normal operation.
W90P710CD/W90P710CDG Host Controller Root Hub Status Register This register is reset by the USBRESET state.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION OverCurrentIndicator [1] This bit reflects the state of the OVRCUR pin. This field is only valid if NoOverCurrentProtection and OverCurrentProtectionMode are cleared. 0 = No over-current condition 1 = Over-current condition OVRCI (Read) LocalPowerStatus Not Supported. Always read '0'. [0] LOPS (Write) ClearGlobalPower Writing a '1' issues a ClearGlobalPower command to the ports. Writing a '0' has no effect.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION PortOverCurrentIndicatorChange [19] POCIC This bit is set when OverCurrentIndicator changes. Writing a '1' clears this bit. Writing a '0' has no effect. PortSuspendStatusChange [18] PSSC This bit indicates the completion of the selective resume sequence for the port. 0 = Port is not resumed. 1 = Port resume is complete.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTION (Read) PortOverCurrentIndicator [3] CPS table of none-2 supports global over-current reporting. This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set. 0 = No over-current condition 1 = Over-current condition (Write) ClearPortSuspend Writing a '1' initiates the selective resume sequence for the port. Writing a '0' has no effect.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 11 10 9 3 OVRCUR 2 1 8 SIEPD 0 Reserved 23 22 21 20 19 Reserved 15 14 13 7 6 5 12 Reserved 4 Reserved BITS [31:9] Reserved DBREG BIT DESCRIPTION Reserved [8] SIEPD [7:4] Reserved Reserved. Read/write 0 SIE Pipeline Disable When set, waits for all USB bus activity to complete prior to returning completion status to the List Processor.
W90P710CD/W90P710CDG 6.8.1 USB Endpoints It consists of four endpoints, designated EP0, EPA, EPB and EPC. Each is intended for a particular use as described below: EP0: the default endpoint uses control transfer (In/Out) to handle configuration and control functions required by the USB specification. Maximum packed size is 16 bytes. EPA: designed as a general endpoint. This endpoint could be programmed to be an Interrupt IN endpoint or an Isochronous IN endpoint or a Bulk In endpoint or Bulk OUT endpoint.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:9] Reserved WakeUp 0: no effect. 1: Generating remote wake-up signal to drive a K-state on USB bus. This function to bring the suspended USB bus to activation with resume state. CCMD USB Class Command Decode Control Enable 0: Disable, the H/W circuit doesn’t need to decode USB class command. It will return a stall status when it received a USB Class Command. 1: Enable, the H/W circuit decodes USB class command.
W90P710CD/W90P710CDG USB Class or Vendor command Register (USB_CVCMD) REGISTER ADDRESS USB_CVCMD 0xFFF0_6004 R/W DESCRIPTION R/W USB class or vendor command register 31 30 29 28 23 22 21 20 RESET VALUE 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved CVI_LG BITS DESCRIPTIONS [31:5] [4:0] Reserved CVI_LG Byte Length for Class and Vendor Command and Get Descriptor Return Data Packet USB Interrupt Enab
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:16] Reserved [15] RUM_CLKI Interrupt enable for RESUME (for clock is stopped) 0: Disable 1: Enable [14] RST_ENDI Interrupt enable for USB reset end 0: Disable 1: Enable USB_CGI Interrupt Enable for Device Configured 0: Disable 1: Enable Note: the interrupt occurs when device configured or dis-configured.
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:16] Reserved Interrupt status for RESUME (for clock is stopped) [15] RUM_CLKS 0: No Interrupt Generated 1: Interrupt Generated Interrupt status for USB reset end [14] RSTENDS 0: No Interrupt Generated 1: Interrupt Generated Interrupt Status for USB Device Configured [13] USB_CGS 0: No Interrupt Generated 1: Interrupt Generated(configured and dis-configured) Interrupt Status for USB Bus Transition [12] USB_BTS 0: No Interrupt Generated 1: Interrupt G
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG 31 30 29 23 22 21 28 Reserved 20 27 26 25 24 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RUM_CLKC RSTENDC USB_CGC USB_BTC CVSC CDIC CDOC VENC 7 6 5 4 3 2 1 0 CLAC GSTRC GCFGC GDEVC ERRC RUMC SUSC RSTC BITS DESCRIPTIONS [31:16] Reserved [15] RUM_CLKC Interrupt status clear for RESUME (for clock is stopped) 0: NO Operation 1: Clear Interrupt Status [14] RSTENDC Interrupt status clear for USB reset end 0: NO Operation 1: Clear Interru
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG 31 23 30 22 29 28 27 26 25 24 21 Reserved 20 19 18 17 16 10 9 8 STR6_EN STR5_EN Reserved 15 14 13 12 11 Reserved 7 6 5 4 3 2 1 0 STR4_EN STR3_EN STR2_EN STR1_EN INF4_EN INF3_EN INF2_EN INF1_EN BITS DESCRIPTIONS [31:10] Reserved USB String Descriptor-6 Control [9] STR6_EN 0: Disable 1: Enable USB String Descriptor-5 Control [8] STR5_EN 0: Disable 1: Enable USB String Descriptor-4 Control [7] STR4_EN 0: Disable 1: Enable USB String Descr
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG USB Control transfer-out port 1 (USB_ODATA1) REGISTER ADDRESS USB_ODATA1 0xFFF0601C 31 30 R/W R DESCRIPTION RESET VALUE USB control transfer-out port 1 register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA1 23 22 21 20 ODATA1 15 14 13 12 ODATA1 7 6 5 4 ODATA1 BITS [31:0] DESCRIPTIONS ODATA1 Control Transfer-out data 1 USB Control transfer-out port 2 (USB_ODATA2) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USB_ODAT
W90P710CD/W90P710CDG USB Control transfer-out port 3 (USB_ODATA3) REGISTER USB_ODATA3 31 ADDRESS 0xFFF06024 30 R/W R 29 DESCRIPTION RESET VALUE USB control transfer-out port 3 register 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA3 23 22 21 20 ODATA3 15 14 13 12 ODATA3 7 6 5 4 ODATA3 BITS [31:0] DESCRIPTIONS ODATA3 Control Transfer-out data 3 USB Control transfer-in data port0 Register (USB_IDATA0) REGISTER USB_IDATA0 ADDRESS R/W 0xFFF06028 R
W90P710CD/W90P710CDG USB Control transfer-in data port 1 Register (USB_IDATA1) REGISTER USB_IDATA1 ADDRESS R/W 0xFFF0602C R/W DESCRIPTION RESET VALUE USB control transfer-in data port 1 31 30 29 28 23 22 21 20 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA1 IDATA1 15 14 13 12 IDATA1 7 6 5 4 IDATA1 BITS [31:6] DESCRIPTIONS IDATA1 Control transfer-in data1 USB Control transfer-in data port 2 Register (USB_IDATA2) REGISTER USB_IDATA2 31 ADDRESS R/W
W90P710CD/W90P710CDG USB Control transfer-in data port 3 Register (USB_IDATA3) REGISTER USB_IDATA3 31 ADDRESS R/W 0xFFF06034 R/W 30 29 DESCRIPTION RESET VALUE USB control transfer-in data port 3 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA3 23 22 21 20 IDATA3 15 14 13 12 IDATA3 7 6 5 4 IDATA3 BITS [31:6] DESCRIPTIONS IDATA3 Control transfer-in data3 USB SIE Status Register (USB_SIE) REGISTER USB_SIE 31 ADDRESS R/W 0xFFF06038 30 R 29 DESCR
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:2] Reserved [1] USB_DPS USB Bus D+ Signal Status 0: USB Bus D+ Signal is low 1: USB Bus D+ Signal is high USB_DMS USB Bus D- Signal Status 0: USB Bus D- Signal is low 1: USB Bus D- Signal is high [0] USB Engine Register (USB_ENG) REGISTER USB_ENG ADDRESS 0xFFF0603C R/W DESCRIPTION R/W RESET VALUE USB Engine Register 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 Reserved 19 18 17 16 10 9 8 3 2 1 0 SDO_RD CV_LDA CV_STL
W90P710CD/W90P710CDG Continued. BITS [1] [0] DESCRIPTIONS CV_STL USB Class and Vendor Command Stall Control 0: NO Operation 1: Return Stall for Class and Vendor Command NOTE: this bit will auto clear after 32 HCLK CV_DAT USB Class and Vendor Command return data control 0: NO Operation 1: The Data Packet for Data Input of Class and Vendor Command or Get Descriptor command is ready.
W90P710CD/W90P710CDG USB Configured Value Register (USB_CONFD) REGISTER USB_CONFD 31 ADDRESS R/W 0xFFF06044 R/W 30 29 DESCRIPTION RESET VALUE USB Configured Value register 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 CONFD BITS DESCRIPTIONS [31:8] [7:0] Reserved CONFD Software configured value USB Endpoint A Information Register (EPA_INFO) REGISTER EPA_INFO 31 Reserved 23 ADDRESS R/W 0xF
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31] Reserved [30:29] EPA_TYPE Endpoint A type 00: reserved 01: bulk 10: interrupt 11: isochronous [28] EPA_DIR Endpoint A direction 0: OUT 1: IN [27:26] Reserved [25:16] EPA_MPS Endpoint A max.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:6] Reserved [6] EPA_ZERO Send zero length packet to HOST [5] EPA_STL_CLR CLEAR the Endpoint A stall(WRITE ONLY) Endpoint A threshold (only for ISO) [4] EPA_THRE 1: once available space in FIFO over 16 bytes, DMA accesses memory 0: once available space in FIFO over 32 bytes, DMA accesses memory [3] EPA_STL Set the Endpoint A stall [2] EPA_RDY The memory is ready for Endpoint A to access [1] EPA_RST Endpoint A reset [0] EPA_EN Endpoint A enab
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:6] Reserved [5] EPA_CF_IE Endpoint A clear feature interrupt enable [4] EPA_BUS_ERR_IE Endpoint A system bus error interrupt enable [3] EPA_DMA_IE Endpoint A DMA transfer complete interrupt enable [2] EPA_ALT_IE Endpoint A alternate setting interrupt enable [1] EPA_TK_IE Endpoint A token input interrupt enable [0] EPA_STL_IE Endpoint A stall interrupt enable USB Endpoint A Interrupt Clear Register (EPA_IC) REGISTER EPA_IC ADDRESS 0xFFF0605
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG USB Endpoint A Address Register (EPA_ADDR) REGISTER EPA_ADDR ADDRESS R/W 0xFFF0605C R/W DESCRIPTION RESET VALUE USB endpoint A address register 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 EPA_ADDR 20 19 18 17 16 10 9 8 2 1 0 EPA_ADDR 15 14 13 12 11 EPA_ADDR 7 6 5 4 3 EPA_ADDR BITS [31:0] DESCRIPTIONS EPA_ADDR Endpoint A transfer address USB Endpoint A transfer length Register (EPA_LENTH) REGISTER ADDRESS R/W EPA_LENTH 0xFFF06060 R/W
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:20] [19:0] Reserved EPA_LENTH Endpoint A transfer length USB Endpoint B Information Register (EPB_INFO) REGISTER EPB_INFO 31 Reserved 23 ADDRESS R/W 0xFFF06064 R/W 30 DESCRIPTION USB endpoint B information register 29 EPB_TYPE 22 RESET VALUE 28 27 EPB_DIR 21 20 26 0x0000_0000 25 Reserved 24 EPB_MPS 19 18 17 16 11 10 9 8 1 0 EPB_MPS 15 14 13 12 EPB_ALT 7 6 EPB_INF 5 4 3 EPB_CFG BITS EPB_NUM DESCRIPTIONS [31] Reserved
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG USB Endpoint B Interrupt Clear Register (EPB_IC) REGISTER EPB_IC 31 ADDRESS 0xFFF06070 30 29 R/W DESCRIPTION W USB endpoint B interrupt clear register 28 27 RESET VALUE 0x0000_0000 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 Reserved 5 4 3 2 1 0 EPB_CF_IC EPB_BUS_ERR_IC EPB_DMA_IC EPB_ALT_IC EPB_TK_IC EPB_STL_IC BITS DESCRIPTIONS [31:6] Reserved [5] EPB_CF_IC Endpoint B clear feature interru
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 Reserved 5 4 3 2 1 0 EPB_CF_IS EPB_BUS_ERR_IS EPB_DMA_IS EPB_ALT_IS EPB_TK_IS EPB_STL_IS BITS DESCRIPTIONS [31:6] Reserved [5] EPB_CF_IS Endpoint B clear feature interrupt status [4] EPB_DMA_IS Endpoint B system bus error interrupt status [3] EPB_DMA_IS Endpoint B DMA transfer complete interrupt status [2] EPB_ALT_IS Endpoint B alter
W90P710CD/W90P710CDG BITS [31:0] DESCRIPTIONS EPB_ADDR Endpoint B transfer address USB Endpoint B transfer length Register (EPB_LENTH) REGISTER EPB_LENTH 31 ADDRESS R/W 0xFFF0607C 30 R/W 29 DESCRIPTION USB endpoint register 28 B RESET VALUE transfer length 0x0000_0000 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 EPB_LENTH 13 12 11 10 9 8 2 1 0 EPB_LENTH 7 6 5 4 3 EPB_LENTH BITS DESCRIPTIONS [31:20] [19:0] Reserved EPB_LENTH Endpoint B tra
W90P710CD/W90P710CDG 31 Reserved 23 30 29 EPC_TYPE 22 28 27 EPC_DIR 21 20 26 25 Reserved 24 EPC_MPS 19 18 17 16 11 10 9 8 1 0 EPC_MPS 15 14 13 12 EPC_ALT 7 6 EPC_INF 5 4 3 EPC_CFG 2 EPC_NUM BITS DESCRIPTIONS [31] Reserved Endpoint C type 00: reserved [30:29] EPC_TYPE 01: bulk 10: interrupt 11: isochronous Endpoint C direction [28] EPC_DIR 0: OUT 1: IN [27:26] Reserved [25:16] EPC_MPS Endpoint C max.
W90P710CD/W90P710CDG USB Endpoint C Control Register (EPC_CTL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EPC_CTL 0xFFF06084 R/W USB endpoint C control register 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 3 2 1 0 Reserved EPC_ZERO EPC_STL_CLR EPC_THRE EPC_STL EPC_RDY EPC_RST EPC_EN BITS DESCRIPTIONS [31:7] Reserved [6] EPC_ZERO Send zero length packet back to HOST [5] EPC_STL_
W90P710CD/W90P710CDG USB Endpoint C interrupt enable Register (EPC_IE) REGISTER EPC_IE 31 30 ADDRESS R/W 0xFFF06088 R/W 29 DESCRIPTION USB endpoint register 28 C Interrupt 27 RESET VALUE Enable 0x0000_0000 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 Reserved 5 4 3 2 1 0 EPC_CF_IE EPC_BUS_ERR_IE EPC_DMA_IE EPC_ALT_IE EPC_TK_IE EPC_STL_IE BITS DESCRIPTIONS [31:6] Reserved [5] EPC_CF_IE Endpoint C clear feature
W90P710CD/W90P710CDG 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EPC_ALT_IC EPC_TK_IC EPC_STL_IC Reserved Reserved 15 14 13 12 Reserved 7 6 Reserved 5 4 EPC_CF_IC EPC_BUS_ERR_IC EPC_DMA_IC BITS DESCRIPTIONS [31:6] Reserved [5] EPC_CF_IC Endpoint C clear feature interrupt clear [4] EPC_DMA_IC Endpoint C system bus error interrupt clear [3] EPC_DMA_IC Endpoint C DMA transfer complete interrupt clear [2] EPC_ALT_IC Endpoint C alternate
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 Reserved 4 EPC_CF_IS 3 EPC_BUS_ERR_IS EPC_DMA_IS BITS EPC_ALT_IS EPC_TK_IS EPC_STL_IS DESCRIPTIONS [31:6] Reserved [5] EPC_CF_IS Endpoint C clear feature interrupt status [4] EPC_BUS_ERR_IS Endpoint A system bus error interrupt status [3] EPC_DMA_IS Endpoint A DMA transfer complete interrupt status [2] EPC_ALT_IS Endpoint A al
W90P710CD/W90P710CDG BITS [31:0] DESCRIPTIONS EPC_ADDR Endpoint C transfer address USB Endpoint C transfer length Register (EPC_LENTH) REGISTER ADDRESS EPC_LENTH 31 0xFFF0_6098 30 29 R/W DESCRIPTION R/W USB endpoint C transfer length register 28 RESET VALUE 0x0000_0000 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 EPC_LENTH 13 12 11 10 9 8 2 1 0 EPC_LENTH 7 6 5 4 3 EPC_LENTH BITS DESCRIPTIONS [31:20] [19:0] Reserved EPC_LENTH Endpoint C trans
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 EPA_XFER 13 12 11 10 9 8 2 1 0 EPA_XFER 7 6 5 4 3 EPA_XFER BITS DESCRIPTIONS [31:20] [19:0] Reserved EPA_XFER Endpoint A remain transfer length USB Endpoint A Remain packet length Register (EPA_PKT) REGISTER ADDRESS EPA_PKT 0xFFF0_60A0 31 30 R/W RESET VALUE DESCRIPTION R/W USB endpoint A remain packet length register 29 28 0x0000_0000 27 26 25 24 19 18 17 16
W90P710CD/W90P710CDG USB Endpoint B Remain transfer length Register (EPB_XFER) REGISTER EPB_XFER 31 ADDRESS 0xFFF0_60A4 30 R/W DESCRIPTION R/W USB endpoint B remain transfer length register 29 28 RESET VALUE 0x0000_0000 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 EPB_XFER 13 12 11 10 9 8 2 1 0 EPB_XFER 7 6 5 4 3 EPB_XFER BITS DESCRIPTIONS [31:20] [19:0] Reserved EPB_XFER Endpoint B remain transfer length USB Endpoint B Remain packet length Regi
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:10] [9:0] Reserved EPB_PKT Endpoint B remain packet length USB Endpoint C Remain transfer length Register (EPC_XFER) REGISTER EPC_XFER 31 ADDRESS 0xFFF0_60AC 30 R/W DESCRIPTION R/W USB endpoint C remain transfer length register 29 28 RESET VALUE 0x0000_0000 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 EPC_XFER 13 12 11 10 9 8 2 1 0 EPC_XFER 7 6 5 4 3 EPC_XFER BITS DESCRIPTIONS [31:20] [19:0] Reserved
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 EPC_PKT 4 3 2 1 0 EPC_PKT BITS DESCRIPTIONS [31:10] [9:0] Reserved EPC_PKT Endpoint C remain packet length - 233 - Publication Release Date: September 19, 2006 Revision B2
W90P710CD/W90P710CDG 6.9 SD Host Controller The SD host controller of W90P710 supports Secure Digital card devices (SD, MMC). The SD hostcontroller also supports DMA function to reduce the intervention of CPU for data transfer between flash memory card and system memory. There are two 512B internal buffers embedded in the SD host controller to buffer the data temporally for DMA transfer between flash memory card and system memory.
W90P710CD/W90P710CDG SD host controller checks the associated CRC-16 bits and reports the result to SD status register. If the data-input interrupt is enabled, an interrupt will occur when the data transfer is finished. The data input status bit of SD status register will be set as 1 for this interrupt. Thus, the CPU can identify a data-input interrupt by reading this bit.
W90P710CD/W90P710CDG 6.9.
W90P710CD/W90P710CDG 6.9.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS DMA Read Enable [3] DMARd Set this bit high enables the DMA to transfer data from external SDRAM to internal buffer. This bit will be cleared automatically after DMA operation finished. Write 0 to this bit has no effect. 1’b0: No DMA operation (Default) 1’b1: Enable DMA read operation DMA Write Enable [2] DMAWr Set this bit high enables the DMA to transfer data from internal buffer into external SDRAM.
W90P710CD/W90P710CDG SD DMA Transfer Starting Address Register (SDDSA) REGISTER ADDRESS R/W SDDSA 0xFFF0_7004 R/W 31 30 29 DESCRIPTION RESET VALUE SD DMA Transfer Starting Address Register 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DMASA 23 22 21 20 DMASA 15 14 13 12 DMASA 7 6 5 4 DMASA BITS DESCRIPTIONS DMA Transfer Starting Address [31:0] DMASA This field defines the address of external SDRAM where DMA reads/writes data from/to.
W90P710CD/W90P710CDG SD DMA Byte Count Register (SDBCR) REGISTER ADDRESS R/W SDBCR 0xFFF0_7008 R/W 31 30 DESCRIPTION RESET VALUE SD DMA Byte Count Register 29 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 BCNT 6 5 4 3 2 1 0 BCNT BITS [31:12] DESCRIPTIONS Reserved DMA Transfer Byte Count [11:0] BCNT This field defines the byte count of DMA Transfer between internal flash buffer and external SDRAM.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:7] Reserved [6] ERRIEN Bus Error Interrupt Enable DMA Read Interrupt Enable [5] DRdIEN This bit controls the SD host controller interrupt generation from the interrupt of the DMA read operation.
W90P710CD/W90P710CDG SD global Interrupt Status Register (SDGISR) REGISTER ADDRESS R/W SDGISR 0xFFF0_7010 R/W 31 30 29 DESCRIPTION RESET VALUE SD Global Interrupt Status Register 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 4 3 2 1 0 Reserved ERRINT DRdINT DWrINT SDHIINT Reserved Reserved SDGINT BITS DESCRIPTIONS [31:7] Reserved - [6] ERRINT Bus Error Interrupt Status DRdINT DMA Read Interr
W90P710CD/W90P710CDG SD BIST Register (SDBIST) REGISTER ADDRESS R/W SDBIST 0xFFF0_7014 R/W 31 30 29 DESCRIPTION RESET VALUE SD BIST Register 28 0x0000_0000 27 26 25 24 18 17 16 10 9 8 2 1 0 Finish BISTEN Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 4 3 Reserved BITS [31:4] [3:2] BistFail DESCRIPTIONS Reserved BistFail BIST Fail The BistFail indicates if the BIST test fails or succeeds.
W90P710CD/W90P710CDG SD Interface Control Register (SDICR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SDICR 0xFFF0_7300 R/W SD Interface Control Register 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 SD_CS Reserved 7 6 5 4 3 2 1 0 CLK_KEEP 8CLK_OE 74CLK_OE R2_EN DO_EN DI_EN RI_EN CO_EN CMD_CODE BITS [31:16] 12 DESCRIPTIONS Reserved SD Card Select Control [15] SD_CS 0=Select SD card-0 1=Select SD
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS 74 Clock Cycle Output Enable 0=Disable [5] 74CLK_OE 1=Enable, SD host controller outputs 74 clock cycles When the operation is finished, this bit is automatically cleared to “0” by H/W circuit. Response R2 Input Enable 0=Disable [4] R2_EN 1=Enable, SD host controller will wait to receive a response R2 from DS card and store the response data into flash buffer.
W90P710CD/W90P710CDG SD Host interface Initial Register (SDHIIR) REGISTER ADDRESS R/W SDHIIR 0xFFF0_7304 R/W 31 30 DESCRIPTION RESET VALUE SD Host Interface Initial Register 29 28 27 0x0000_0018 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 SPD 4 3 2 1 0 SD_CLK BITS DESCRIPTIONS [31:9] Reserved - [8] SPD Data Bus Width Control 0=1-bit data bus 1=4-bit data bus SD_CLK SD Clock Control The frequency of SD clock will
W90P710CD/W90P710CDG BITS [31:5] DESCRIPTIONS Reserved SD Interrupt Status Enable [4] 0=Disable SD_IS interrupt generation SD_IEN 1=Enable SD_IS interrupt generation SD DAT0 Level Transition Interrupt Status Enable [3] 0=Disable DAT0_STS interrupt generation DAT0_IEN 1=Enable DAT0_STS interrupt generation CD# Interrupt Status Enable [2] 0=Disable CD_IS interrupt generation CD_IEN 1=Enable CD_IS interrupt generation Data Output Interrupt Status Enable [1] 0=Disable DO_IS interrupt generation
W90P710CD/W90P710CDG BITS [31:11] DESCRIPTIONS Reserved SD Interrupt Value Status 0 = SD interrupt at interrupt period. Write 1 to clear this status bit (set DAT1_IS_ to 1). 1 = no SD interrupt at interrupt period. [10] DAT1_IS_ If SD_IEN is set and DAT1_IS_ is 0, an interrupt request will be generated.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS CD# Interrupt Status [2] CD_IS 0=No Interrupt Generated 1=Interrupt Generated Note: Write “1” into this bit will clear the interrupt status. Data Output Interrupt Status [1] DO_IS 0=No Interrupt Generated 1=Interrupt Generated Note: Write “1” into this bit will clear the interrupt status. Data Input Interrupt Status [0] 0=No Interrupt Generated DI_IS 1=Interrupt Generated Note: Write “1” into this bit will clear the interrupt status.
W90P710CD/W90P710CDG SD Receive Response Token Register 0 (SDRSP0) REGISTER ADDRESS R/W SDRSP0 0xFFF0_7314 R 31 30 29 DESCRIPTION RESET VALUE SD Receive Response Token Register 0 28 27 0xXXXX_XXXX 26 25 24 18 17 16 10 9 8 2 1 0 SD_RSP_TK0 23 22 21 20 19 SD_RSP_TK0 15 14 13 12 11 SD_RSP_TK0 7 6 5 4 3 SD_RSP_TK0 BITS DESCRIPTIONS SD Receive Response Token 0 [31:0] SD_RDP_TK0 SD host controller will receive a response token for getting a reply from SD card.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:8] - Reserved SD Receive Response Token 1 [7:0] SD host controller will receive a response token for getting a reply from SD card. This register records the bit 15-8 of the response token.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FBuf0 23 22 21 20 15 14 13 12 7 6 5 4 FBuf0 FBuf0 FBuf0 BITS [31:0] DESCRIPTIONS Flash Buffer 0 These register ports supports the data read from embedded flash buffer 0. The embedded flash buffer size is 512 bytes, the 128 words. Consequently, the address range for flash buffer 0 is from 0xFFF0_7400 to 0xFFF0_75FC. FBuf0 Flash Buffer 1 Registers (FB1_0 ~ FB1_127) REGISTER FB1_0 …..
W90P710CD/W90P710CDG 6.10 LCD Controller 6.10.
W90P710CD/W90P710CDG 6.10.
W90P710CD/W90P710CDG LCD Register MAP, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE OSDLUTENTRY1 0xFFF0_8060 R/W OSD lookup table entry index 1 0x0000_0000 OSDLUTENTRY2 0xFFF0_8064 R/W OSD lookup table entry index 2 0x0000_0000 OSDLUTENTRY3 0xFFF0_8068 R/W OSD lookup table entry index 3 0x0000_0000 OSDLUTENTRY4 0xFFF0_806C R/W OSD lookup table entry index 4 0x0000_0000 DITHP1 0xFFF0_8070 R/W Gray level dithered data duty pattern 1 0x0101_0001 DITHP2 0xFFF0_8074 R/W
W90P710CD/W90P710CDG 6.10.3 LCD Special Register Description 6.10.3.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS [23] Monochrome LCD has an 8-bit interface LCDMON8 0 = mono LCD use 4-bit interface 1 = mono LCD use 8-bit interface [22] [21] [20] [19:18] LCDBW STN LCD is monochrome 0 = STN LCD is color 1 = STN LCD is monochrome Image stored in memory device is YUV format or RGB format 0 = RGB format YUV_nRGB 1 = YUV format If this bit is set to 1, VDBPP and OSDBPP must be set to 101 ( 16bpp ) TVEN External TV encoder Enable 0 = Normal operation 1 = Convert RGB
W90P710CD/W90P710CDG Continued BITS [9:8] DESCRIPTIONS LCDBUS LCD Data output re-map( Only used at Sync-type High Color TFT) 00 = Databus is 24bit 01 = Databus is 18bit 10 = Databus is 8bit 11 = Reserved [7] OSD Lookup Table Enable OSDLUTEN 0 = display OSD color directly from image 1 = display OSD color from lookup table [6:4] OSDBPP OSD image bits per pixel 000 = 1 bpp 2-gray level 001 = 2 bpp 4-gray level 010 = 4 bpp 16-gray level 011 = 8 bpp RGB332 100 = 12 bpp RGB444 101 = 16 bpp RGB565 110 =
W90P710CD/W90P710CDG Sync-type TFT: Fig. 6.10.3.2 Sync-type TFT output format TV-Encoder: Fig. 6.10.3.3 TV-Enocder output format Color STN: Fig. 6.10.3.
W90P710CD/W90P710CDG Monochrome STN with 4-bit data bus: Fig. 6.10.3.5 Monochrome STN output format - 1 Monochrome STN with 8-bit data bus: Fig. 6.10.3.6 Monochrome STN output format - 2 Only when LUTWREN is enabled, Lookup Table SRAM can be read / write by CPU. If LUTWREN is disabled, Lookup Table SRAM is accessed by LCD Controller. Palette function can’t be enabled for STN panel.
W90P710CD/W90P710CDG replaced with zero. Please refer to GPIO chapter to setting this register. This is only used for Synctype High Color TFT because it’s databus is large over 8bit. Databus of other panel is only 8bit so don’t need to setting this register. VD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LCDBUS = 00 R[7:0] LCDBUS = 01 9 8 7 6 5 G[7:0] 0 3 2 1 0 B[7:0] R[7:2] LCDBUS = 10 4 G[7:2] 0 B[7:2] R[7:5] G[7:5] B[7:6] 6.10.3.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:19] Reserved Reserved [18] UNDREN2 FIFO2 UNDERRUN interrupt enable [17] UNDREN1 FIFO1 UNDERRUN interrupt enable [16] AHBEREN AHB ERROR interrupt enable [15:6] Reserved Reserved [5] HSEN HSYNC interrupt enable [4] VSEN VSYNC interrupt enable [3] VLFINEN2 FIFO2 VLINE FINISH interrupt enable [2] VFFINEN2 FIFO2 VFRAME FINISH interrupt enable [1] VLFINEN1 FIFO1 VLINE FINISH interrupt enable [0] VFFINEN1 FIFO1 VFRAME FINISH interrupt en
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:20] Reserved Reserved [18] UNDRIS2 FIFO2 have no data for output to Panel [17] UNDRIS1 FIFO1 have no data for output to Panel [16] AHBERIS AHB master bus error status [15:6] Reserved Reserved [5] HSIS Timing Generator output a HSYNC pulse [4] VSIS Timing Generator output a VSYNC pulse [3] VLFINIS2 FIFO2 transfer one line stream complete [2] VFFINIS2 FIFO2 transfer one frame stream complete [1] VLFINIS1 FIFO1 transfer one line stream
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 UNDRIC2 UNDRIC1 AHBERIC 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 Reserved 5 4 3 2 1 0 HSIC VSIC VLFINIC2 VFFINIC2 VLFINIC1 VFFINIC1 BITS DESCRIPTIONS [31:20] Reserved Reserved [18] UNDRIC2 Clear FIFO2 UNDERRUN interrupt [17] UNDRIC1 Clear FIFO1 UNDERRUN interrupt [16] AHBERIC Clear MBERROR interrupt [15:6] Reserved Reserved [5] HSIC Clear HSYNC interrupt [4] VSIC C
W90P710CD/W90P710CDG 6.10.3.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 4 Reserved 3 VDHUP BITS [31:5] [4:3] [2:1] [0] VDVUP Reserved DESCRIPTIONS Reserved Reserved VDHUP Video Horizontal Up-scaling control 00=1x 01=2x 10=4x VDVUP Video Vertical Up-scaling control 00=1x 01=2x 10=4x Reserved Reserved OSD Down-Scaling Factor Register (OSDDNSCF) REGISTER OSDDNSCF 31 ADDRESS R/W 0xFFF0_8018 R/W 30
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:24] OSDVDNN An 8-bit value specifies the numerator part (N) of the vertical downscaling factor. [23:16] OSDVDNM An 8-bit value specifies the numerator part (M) of the vertical downscaling factor. [15:8] OSDHDNN An 8-bit value specifies the numerator part (N) of the Horizontal down-scaling factor. [7:0] OSDHDNM An 8-bit value specifies the numerator part (M) of the Horizontal down-scaling factor.
W90P710CD/W90P710CDG 6.10.3.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Video image 18bpp swap control bit 0=Swap Disable 1=Swap Enable [18] VDBPP18SW [17] VDHSWP Video half-word swap control bit. 0 = Swap Disable 1 = Swap Enable [16] VDBSWP Video byte swap control bit.
W90P710CD/W90P710CDG FIFO1 Parameter Register (FIFO1PRM) REGISTER ADDRESS FIFO1PRM 31 R/W 0xFFF0_8028 30 DESCRIPTION R/W 29 FIFO1 parameters 28 27 RESET VALUE 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 F1STRIDE[15:8] 23 22 21 20 19 F1STRIDE[7:0] 15 14 13 12 11 Reserved 7 6 5 4 Reserved 3 F1LOCK BITS F1BURSTY F1TRANSZ DESCRIPTIONS [31:16] F1STRIDE Video frame buffer stride 16-bit value specifies the word offset of memory address of vertically adjacent line fo
W90P710CD/W90P710CDG 31 30 29 28 23 22 21 20 27 26 25 24 18 17 16 10 9 8 2 1 0 F2STRIDE[15:8] 19 F2STRIDE[7:0] 15 14 13 12 7 6 5 4 11 Reserved Reserved 3 F2LOCK BITS F2BURSTY F2TRANSZ DESCRIPTIONS [31:16] F2STRIDE Video frame buffer stride 16-bit value specifies the word offset of memory address of vertically adjacent line for FIFO2 fetching.
W90P710CD/W90P710CDG BITS [31:0] DESCRIPTIONS These bits indicate the source address of the bank location for the LCD frame buffer in the system memory.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:16] FIFO1COLCNT These bits indicate the FIFO1 request count per-line of video [15:0] FIFO1ROWCNT These bits indicate the FIFO1 request count per-frame of video FIFO2 Request Count Register (FIFO2DREQCNT) REGISTER ADDRESS R/W FIFO2DREQCNT 0xFFF0_803C R/W 31 30 29 DESCRIPTION RESET VALUE FIFO2 data request count 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 FIFO2COLCNT[31:24] 23 22 21 20 19 FIFO2COLCNT[23:16] 15 14 13 12
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 FIFO1CURADR[31:24] 23 22 21 20 19 FIFO1CURADR[23:16] 15 14 13 12 11 FIFO1CURADR[15:8] 7 6 5 4 3 FIFO1CURADR[7:0] BITS [31:0] DESCRIPTIONS FIFO1CURADR Contains the approximate current FIFO1 access data address FIFO2 Current Access Address Register (FIFO2CURADR) REGISTER ADDRESS FIFO2CURADR 31 0xFFF0_8044 30 29 R/W R DESCRIPTION RESET VALUE FIFO2 current access address 28 27 0x0000_0000 26
W90P710CD/W90P710CDG FIFO1 Real Column Count Register (F1REALCULCNT) REGISTER ADDRESS R/W FIFO1REALCULCNT 0xFFF0_8048 R/W 31 30 29 28 DESCRIPTION RESET VALUE FIFO1 real column count 27 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 F1REALCOLCNT[15:8] 7 6 5 4 3 F1REALCOLCNT[7:0] BITS [31:16] [15:0] DESCRIPTIONS Reserved Reserved F1REALCOLCNT These bits indicate the FIFO1 real column count per-frame of video FIFO2 Re
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:16] Reserved Reserved [15:0] F2REALCOLCNT These bits indicate the FIFO2 real column count per-line of video 24bpp image format: (BSWP=0, HSWP=0, BPP24SWP=0) D[31:24] D[23:0] 0000H Dummy Bit Pixel 1 0004H Dummy Bit Pixel 2 0008H Dummy Bit Pixel 3 ………. (BSWP=0, HSWP=0, BPP24SWP=1) D[31:8] D[7:0] 0000H Pixel 1 Dummy Bit 0004H Pixel 2 Dummy Bit 0008H Pixel 3 Dummy Bit ……….
W90P710CD/W90P710CDG (BSWP=0, HSWP=0, BPP18SWP=1) D[31:18] D[17:0] 0000H Pixel 1 Dummy Bit 0004H Pixel 2 Dummy Bit 0008H Pixel 3 Dummy Bit D[31:16] D[15:0] 0000H Pixel 2 Pixel 1 0004H Pixel 4 Pixel 3 0008H Pixel 6 Pixel 5 D[31:16] D[15:0] 0000H Pixel 1 Pixel 2 0004H Pixel 3 Pixel 4 0008H Pixel 5 Pixel 6 ………. 16bpp image format: (BSWP=0, HSWP=0) ………. (BSWP=0, HSWP=1) ……….
W90P710CD/W90P710CDG 12bpp image format: (BSWP=0, HSWP=0) D[31:28] P[27:16] P[15:12] D[11:0] 0000H Dummy Bit Pixel 2 Dummy Bit Pixel 1 0004H Dummy Bit Pixel 4 Dummy Bit Pixel 3 0008H Dummy Bit Pixel 6 Dummy Bit Pixel 5 D[31:28] P[27:16] P[15:12] D[11:0] 0000H Dummy Bit Pixel 1 Dummy Bit Pixel 2 0004H Dummy Bit Pixel 3 Dummy Bit Pixel 4 0008H Dummy Bit Pixel 5 Dummy Bit Pixel 6 D[31:24] P[23:16] P[15:8] D[7:0] 0000H Pixel 4 Pixel 3 Pixel 2 Pixel 1 0004H Pixel 8
W90P710CD/W90P710CDG 4bpp image format: (BSWP=0, HSWP=0) D[31:28] P[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 0000H Pixel 7 Pixel 8 Pixel 5 Pixel 6 Pixel 3 Pixel 4 Pixel 1 Pixel 2 0004H Pixel 15 Pixel 16 Pixel 13 Pixel 14 Pixel 11 Pixel 12 Pixel 9 Pixel 10 …… (BSWP=1, HSWP=0) D[31:28] P[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 0000H Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 0004H Pixel 9 Pixel 10 Pixel 11 Pix
W90P710CD/W90P710CDG (BSWP=1, HSWP=0) 0000H 0004H D[31:30] P[29:28] D[27:26] D[25:24] D[23:22] D[21:20] D[19:18] D[17:16] Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 D[15:14] P[13:12] D[11:10] D[9:8] D[7:6] D[5:4] D[3:2] D[1:0] Pixel 9 Pixel 10 Pixel 11 Pixel 12 Pixel 13 Pixel 14 Pixel 15 Pixel 16 D[31:30] P[29:28] D[27:26] D[25:24] D[23:22] D[21:20] D[19:18] D[17:16] Pixel 17 Pixel 18 Pixel 19 Pixel 20 Pixel 21 Pixel 22 Pixel 23 Pixel 24
W90P710CD/W90P710CDG (BSWP=0, HSWP=0) 0000H D[31] P[30] D[29] D[28] D[27] D[26] D[25] D[24] Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 D[23] P[22] D[21] D[20] D[19] D[18] D[17] D[16] Pixel 9 Pixel 10 Pixel 11 Pixel 12 Pixel 13 Pixel 14 Pixel 15 Pixel 16 D[15] P[14] D[13] D[12] D[11] D[10] D[9] D[8] Pixel 17 Pixel 18 Pixel 19 Pixel 20 Pixel 21 Pixel 22 Pixel 23 Pixel 24 D[7] P[6] D[5] D[4] D[3] D[2] D[1] D[0] Pixel 25 Pixel 26 Pi
W90P710CD/W90P710CDG 480 pixels 480 pixels Fig. 6.10.5.
W90P710CD/W90P710CDG N BPP W (WORD) 1 BPP (Black / White) 2 BPP (4 gray-level) 4 BPP (16 gray-level) 8 BPP ( RGB 332) 12 BPP (RGB 444) 16 BPP (RGB 565) 18 BPP (RGB 666) 24 BPP (RGB 888) X % 32 X % 16 X%8 X%4 X%2 X%2 X%1 X%1 The first limitation is W must be a integer. The second limitation is W must be a multiple of 8 for Color STN panel. W can be a multiple of 4, 8 or 16 for other kind of panel. If W is a multiple of 4, the register value of F1BURSTY (FIFO1PRM register) must be set to 00.
W90P710CD/W90P710CDG BITS DESCRIPTIONS Theses bits define address of Lookup Table SRAM when Video pixel data is [31:0] 00 = VDLUTENTY1[7:0] VDLUTENTY1 01 = VDLUTENTY1[15:8] 10 = VDLUTENTY1[23:16] 11 = VDLUTENTY1[31:24] Video Lookup Table Entry Index 2 Register (VDLUTENTY2) REGISTER ADDRESS R/W VDLUTENTY2 0xFFF0_8054 R/W 31 30 29 DESCRIPTION RESET VALUE Video lookup table entry index 2 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 VDLUTENTY2[31:24] 23 22 21 20 19 VD
W90P710CD/W90P710CDG Video Lookup Table Entry Index 3 Register (VDLUTENTY3) REGISTER ADDRESS R/W VDLUTENTY3 0xFFF0_8058 R/W DESCRIPTION Video lookup table entry index 3 31 30 29 28 23 22 21 20 27 RESET VALUE 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 VDLUTENTY3[31:24] 19 VDLUTENTY3[23:16] 15 14 13 12 7 6 5 4 11 VDLUTENTY3[15:8] 3 VDLUTENTY3[7:0] BITS [31:0] DESCRIPTIONS Theses bits define address of Lookup Table SRAM when Video pixel data is 00 = VDLUTENTY3[7:0]
W90P710CD/W90P710CDG BITS DESCRIPTIONS Theses bits define address of Lookup Table SRAM when Video pixel data is [31:0] 00 = VDLUTENTY4[7:0] VDLUTENTY4 01 = VDLUTENTY4[15:8] 10 = VDLUTENTY4[23:16] 11 = VDLUTENTY4[31:24] OSD Lookup Table Entry Index 1 Register (OSDLUTENTRY1) REGISTER ADDRESS OSDLUTENTRY 31 30 0xFFF0_8060 29 R/W R/W 28 DESCRIPTION RESET VALUE OSD lookup table entry index 1 27 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 OSDLUTENTRY1[31:24] 23 22 21 20 19 OS
W90P710CD/W90P710CDG OSD Lookup Table Entry Index 2 Register (OSDLUTENTRY2) REGISTER ADDRESS R/W OSDLUTENTRY2 0xFFF0_8064 R/W 31 30 29 28 DESCRIPTION RESET VALUE OSD lookup table entry index 2 27 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 OSDLUTENTRY2[31:24] 23 22 21 20 19 OSDLUTENTRY2[23:16] 15 14 13 12 11 OSDLUTENTRY2[15:8] 7 6 5 4 3 OSDLUTENTRY2[7:0] BITS [31:0] DESCRIPTIONS Theses bits define address of Lookup Table SRAM when pixel OSD data is 00 = OSDLUTENT
W90P710CD/W90P710CDG BITS [31:0] DESCRIPTIONS Theses bits define address of Lookup Table SRAM when OSD pixel data is 00 = OSDLUTENTRY3[7:0] 01 = OSDLUTENTRY3[15:8] 10 = OSDLUTENTRY3[23:16] 11 = OSDLUTENTRY3[31:24] OSDLUTENTRY3 OSD Lookup Table Entry Index 4 Register (OSDLUTENTRY4) REGISTER ADDRESS R/W OSDLUTENTRY4 0xFFF0_806C R/W 31 30 29 DESCRIPTION RESET VALUE OSD lookup table entry index 4 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 OSDLUTENTRY4[31:24] 23 22 21 20
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DP2[15:8] 23 22 21 20 DP2[7:0] 15 14 13 12 DP1[15:8] 7 6 5 4 DP1[7:0] BITS DESCRIPTIONS [31:16] DP2 [15:0] DP1 Recommended pattern value for “4’b0010” gray level 0000 0001 0000 0001 Recommended pattern value for “4’b0001” gray level 0000 0000 0000 0001 Dithering Pattern 2 Register (DITHP2) REGISTER DITHP2 31 ADDRESS R/W 0xFFF0_8074 30 R/W 29 DESCRIPTION RESET VALUE Gray level dithered
W90P710CD/W90P710CDG Dithering Pattern 3 Register (DITHP3) REGISTER DITHP3 31 ADDRESS R/W 0xFFF0_8078 30 R/W 29 DESCRIPTION RESET VALUE Gray level dithered data duty pattern 3 28 0x4949_2491 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DP6[15:8] 23 22 21 20 DP6[7:0] 15 14 13 12 DP5[15:8] 7 6 5 4 DP5[7:0] BITS DESCRIPTIONS [31:16] DP6 Recommended pattern value “4’’b0110” gray level 0100 1001 0100 1001 [15:0] DP5 Recommended pattern value “4’’b0101” gray level 001
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:16] DP8 Recommended pattern value “4’’b1000” gray level 0101 0101 0101 0101 [15:0] DP7 Recommended pattern value “4’’b0111” gray level 0101 0010 1010 1001 Dithering Pattern 5 Register (DITHP5) REGISTER DITHP5 31 ADDRESS R/W 0xFFF0_8080 30 R/W 29 DESCRIPTION RESET VALUE Gray level dithered data duty pattern 5 28 27 0xB6B6_B556 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DP10[15:8] 23 22 21 20 DP10[7:0] 15 14 13 12 DP9[15:8]
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 DP12[15:8] 23 22 21 20 19 DP12[7:0] 15 14 13 12 11 DP11[15:8] 7 6 5 4 3 DP11[7:0] BITS DESCRIPTIONS [31:16] DP12 Recommended pattern value “4’’b1100” gray level 1110 1110 1110 1110 [15:0] DP11 Recommended pattern value “4’’b1011” gray level 1101 1011 0110 1110 Dithering Pattern 7 Register (DITHP7) REGISTER DITHP7 31 ADDRESS R/W DESCRIPTION RESET VALUE 0xFFF0_8088 R/W Gray level dithered data
W90P710CD/W90P710CDG THE ADDRESS VALUE WHICH WILL INPUT LOOKUP TABLE SRAM PIXEL DATA OF 4BPP IMAGE 0 (0000) 1 (0001) 2 (0010) 3 (0011) 4 (0100) 5 (0101) 6 (0110) 7 (0111) 8 (1000) 9 (1001) 10 (1010) 11 (1011) 12 (1100) 13 (1101) 14 (1110) 15 (1111) LUTENTY1[7:0] LUTENTY1[15:8] LUTENTY1[23:16] LUTENTY1[31:24] LUTENTY2[7:0] LUTENTY2[15:8] LUTENTY2[23:16] LUTENTY2[31:24] LUTENTY3[7:0] LUTENTY3[15:8] LUTENTY3[23:16] LUTENTY3[31:24] LUTENTY4[7:0] LUTENTY4[15:8] LUTENTY4[23:16] LUTENTY4[31:24] When the image
W90P710CD/W90P710CDG 6.10.3.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 VWYS[31:24] 23 22 21 20 19 VWYS[23:16] 15 14 13 12 11 VWXS[15:8] 7 6 5 4 3 VWXS[7:0] BITS DESCRIPTIONS [31:16] VWYS Video Window Y-Start A 16-bit value specifies the vertical starting pixel positions of the LCD display window. [15:0] VWXS Video Window X-Start A 16-bit value specifies the horizontal starting pixel positions of the LCD display window.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:16] VWYE Video Window Y-End A 16-bit value specifies the vertical last pixel positions of the LCD display window. [15:0] VWXE Video Window X-End A 16-bit value specifies the horizontal last pixel positions of the LCD display window.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 OSDWYE[15:8] 23 22 21 20 19 OSDWYE[7:0] 15 14 13 12 11 OSDWXE[15:8] 7 6 5 4 3 OSDWXE[7:0] BITS DESCRIPTIONS [31:16] OSDWYE OSD Window Y-End A 16-bit value specifies the vertical last pixel positions of the OSD window. [15:0] OSDWXE OSD Window X-End A 16-bit value specifies the horizontal last pixel positions of the OSD window.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:24] Reserved Reserved [23:16] BLICNT OSD Blinking Cycle Time An 8-bit value specifies the OSD blinking cycle time (unit: Vsync) [15:10] Reserved Reserved OSDBLI OSD Blinking Control 0 = Disable 1 = Enable [8] OSDCKY OSD Color Key Control 0 = Disable 1 = Enable [7] Reserved Reserved [6:4] VASYNW Video Synthesis Weighting Synthesized video= [Video x VASYNW+ OSD x (8-VASYNW)]/8 OCR1 Video/OSD overlay control 1 When display region with OSD windo
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:24] Reserved Reserved [23:16] OSDRKYP OSD data comparing of R component according to the source color format [15:8] OSDGKYP OSD data comparing of G component according to the source color format [7:0] OSDBKYP OSD data comparing of B component according to the source color format OSD Overlay Color Key Mask Register (OSDOVCKM) REGISTER OSDOVCKM 31 ADDRESS R/W 0xFFF0_80AC R/W 30 29 DESCRIPTION RESET VALUE OSD Overlay Color-Key Mask 28 0x0000
W90P710CD/W90P710CDG 6.10.3.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 PPL[15:8] 23 22 21 20 PPL[7:0] 15 14 13 12 LPP[15:8] 7 6 5 4 3 LPP[7:0] BITS DESCRIPTIONS Pixel Per-Line [31:16] PPL [15:0] LPP The PPL bit field specifies the number of pixels in each line or row of screen. Lines Per-Panel The LPP bit field specifies the number of active lines per screen.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:30] Reserved Reserved [29:20] VSPW Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines. [19:10] VBPD Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. [9:0] VFPD Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period.
W90P710CD/W90P710CDG LCD Timing Control 5 Register (LCDTCON5) REGISTER LCDTCON5 31 ADDRESS 0xFFF0_80C0 30 29 R/W R/W DESCRIPTION RESET VALUE LCD Timing Control 5 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 ACBF 13 12 11 Reserved 7 6 5 Reserved 4 3 2 1 0 MMODE INVVCLK INVHSYN INVVSYN INVVDEN BITS DESCRIPTIONS [31:21] Reserved Reserved [20:16] ACBF Determine the toggle rate of the VDEN AC bias pin).
W90P710CD/W90P710CDG LCD Timing Control 6 Register (LCDTCON6) REGISTER LCDTCON6 31 ADDRESS R/W 0xFFF0_80C4 30 R 29 DESCRIPTION RESET VALUE LCD Timing Control 6 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 PPLCURENT[15:8] 23 22 21 20 19 PPLCURENT[7:0] 15 14 13 12 11 LPPCURENT[15:8] 7 6 5 4 3 LPPCURENT[7;0] BITS DESCRIPTIONS [31:16] PPLCURENT Pixel number which LCD Controller is outputting to LCD Panel [15:0] LPPCURENT Line number which LCD Controller is o
W90P710CD/W90P710CDG Fig. 6.10.3.7.2 TFT Vertical display timing diagram Fig. 6.10.3.7.3 STN Horizontal display timing diagram Fig. 6.10.3.7.
W90P710CD/W90P710CDG 6.10.3.
W90P710CD/W90P710CDG 6.11 Audio Controller The audio controller consists of IIS/AC-link protocol to interface with external audio CODEC. One 8-level deep FIFO for read path and write path and each level has 32-bit width (16 bits for right channel and 16 bits for left channel). One DMA controller handles the data movement between FIFO and memory. The following are the property of the DMA.
W90P710CD/W90P710CDG LRC LK L e ft 1 2 R ig h t 3 1 2 BCK DATA B2 M SB LSB M SB I2S b u s LRC LK L e ft 1 2 R ig h t 3 1 2 BCK DATA M SB B2 B3 LSB M SB B2 M S B – J u s tif ie d f o r m a t Figure 6.11.2.2 The format of IIS The sampling rate, bit shift clock frequency could be set by the control register ACTL_IISCON. 6.11.2 AC97 Interface The AC97 interface, called AC-link is supported. For input and output direction, each frame contains a Tag slot and 12 data slots.
W90P710CD/W90P710CDG The signal format is shown as Figure 6.11.2.2 Frame (48 KHz) Data phase Tag phase SYNC 12.288 MHz BCLK . . . . . . DIN . . . . . . . DOUT B255 B0 MS B1 . . B15 B16 Slot 0 B35 B36 Slot 1 LS . B55 B56 Slot 2 . B75 B76 Slot 3 . B95 B96 Slot 4 B255 Slot 5 –12 Figure 6.11.2.
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG 6.11.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Reserved Reserved Reserved 7 6 5 FIFO_TH Reserved 4 IIS_AC_PIN_ SEL Reserved 3 Reserved BITS 2 1 BLOCK_EN[1:0] 0 Reserved DESCRIPTIONS [15] Reserved - [14] Reserved - [13] Reserved - [12] R_DMA_IRQ T_DMA_IRQ R_DMA_IRQ When recording, when the DMA destination current address reach the DMA destination end address or middle address, the R_DMA_IRQ bit will be set to 1
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 AUDIO_RDSTB[31:24] 23 22 21 20 19 AUDIO_RDSTB[23:16] 15 14 13 12 11 AUDIO_RDSTB[15:8] 7 6 5 4 3 AUDIO_RDSTB[7:0] BITS [31:0] DESCRIPTIONS 32-bit record destination base address AUDIO_RDSTB[31:0] The AUDIO_RDSTB[31:0] bits is read/write.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:0] 32-bit record destination address length AUDIO_RDST_L[31:0] The AUDIO_RDST_L[31:0] bits is read/write. DMA destination current address (ACTL_RDSTC) REGISTER ACTL_RDSTC ADDRESS R/W 0xFFF0_9010 RO DESCRIPTION RESET VALUE DMA record destination current address 0x0000_0000 The value in ACTL_RDSTC is the DMA record destination current address, this register could only be read by CPU.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 17 16 9 8 1 0 Reserved 23 22 21 20 19 18 Reserved 15 14 13 12 11 10 Reserved 7 6 5 4 3 Reserved 2 R_FIFO_FULL BITS R_DMA_END_IRQ R_DMA_MIDDLE_IRQ DESCRIPTIONS [31:3] Reserved Record FIFO full indicator bit [2] R_FIFO_FULL R_FIFO_FULL=0, the record FIFO not full R_FIFO_FULL=1, the record FIFO is full The R_FIFO_READY bit is read only DMA end address interrupt request bit for record [1] R_DMA_END_IRQ R_DMA_END_IRQ=0, mean
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 AUDIO_PDSTB[31:24] 23 22 21 20 19 AUDIO_PDSTB[23:16] 15 14 13 12 11 AUDIO_PDSTB[15:8] 7 6 5 4 3 AUDIO_PDSTB[7:0] BITS [31:0] DESCRIPTIONS AUDIO_PDSTB[31:0] 32-bit play destination base address The AUDIO_PDSTB[31:0] bits is read/write.
W90P710CD/W90P710CDG BITS [31:0] DESCRIPTIONS 32-bit play destination address length AUDIO_PDST_L[31:0] The AUDIO_PDST_L[31:0] bits is read/write. DMA destination current address (ACTL_PDSTC) REGISTER ADDRESS R/W 0xFFF0_9020 RO ACTL_PDSTC DESCRIPTION RESET VALUE DMA play destination current address 0x0000_0000 The value in ACTL_PDSTC is the DMA play destination current address, this register could only be read by CPU.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 17 16 9 8 2 1 0 P_FIFO_EMPTY P_DMA_END_IRQ P_DMA_MIDDLE _IRQ Reserved 23 22 21 20 19 18 Reserved 15 14 13 12 11 10 Reserved 7 6 5 4 3 Reserved BITS DESCRIPTIONS [31:3] Reserved Playback FIFO empty indicator bit [2] P_FIFO_EMPTY P_FIFO_EMPTY=0, the playback FIFO is not empty P_FIFO_EMPTY=1, the playback FIFO is empty The P_FIFO_EMPTY bit is read only DMA end address interrupt request bit for playback [1] P_DMA_END_IRQ
W90P710CD/W90P710CDG The ACTL_IISCON is the IIS basic operation control register. 31 30 29 28 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 PRS[3:0] 13 12 11 10 9 8 2 1 0 Reserved 7 6 BCLK_SEL[1:0] 5 4 3 FS_SEL MCLK_SEL FORMAT BITS [31:20] Reserved DESCRIPTIONS Reserved IIS frequency pre-scaler selection bits.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS IIS serial data clock frequency selection bit [7:6] BCLK_SEL [1:0] BCLK_SEL[1:0]=00, 32fs is selected (fs is sampling rate), when FS_SEL=0, the frequency of bit clock is MCLK/8, when FS_SEL=1, the frequency of bit clock is MCLK/12. BCLK_SEL[1:0]=01, 48fs is selected (only when FS_SEL=1, this term could be selection), when FS_SEL=1, the frequency of bit clock is MCLK/8.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 Reserved 5 4 3 2 1 0 AC_BCLK_ PU_EN AC_R_FINI SH AC_W_FINI SH AC_W_RE S AC_C_RES Reserved BITS [6] DESCRIPTIONS Reserved This bit controls the AC_BCLK pin pull-high resister.
W90P710CD/W90P710CDG Continued. BITS [2] DESCRIPTIONS AC-link warm reset control bit, when this bit is set to 1, (AC-link begin warn reset procedure, after warn reset procedure finished, this bit will be cleared automatically) the interface signal AC_SYNC is high, when this bit is set to 0, the interface signal AC_SYNC is controlled by AC_BCLK input when this bit is set to 1. Note the AC-link spec. shows it need at least 10 us high duration of AC_SYNC to warn reset AC97.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:5] Reserved Frame valid indicated bits [4] VALID_FRAME=1, any one of slot is valid VALID_FRAME=0, no any slot is valid The VALID_FRAME bits are read/write VALID_FRAME Slot valid indicated bits [3:0] SLOT_VALID[0]= 1/0, indicate Slot 1 valid/invalid SLOT_VALID[1]= 1/0, indicate Slot 2 valid/invalid SLOT_VALID[2]= 1/0, indicate Slot 3 valid/invalid SLOT_VALID[3]= 1/0, indicate Slot 4 valid/invalid The SLOT_VALID[3:0] bits are read/write SLOT_VALID [3:0] T
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:8] Reserved Read/Write select bit [7] R_WB R_WB=1, a read specified by R_INDEX[6:0] will occur, and the data will appear in next frame R_WB=0, a write specified by R_INDEX[6:0] will occur, and the write data is put at out slot 2 The R_WB bit is read/write [6:0] R_INDEX[6:0] External AC97 CODEC control register index (address) bits The R_INDEX[6:0] bits are read/write AC-link output slot 2 (ACTL_ACOS2) REGISTER ACTL_ACOS2 ADDRESS R/W 0xFFF0_9038 R/W
W90P710CD/W90P710CDG AC-link input slot 0 (ACTL_ACIS0) REGISTER ACTL_ACIS0 ADDRESS R/W 0xFFF0_903C R DESCRIPTION RESET VALUE AC-link in slot 0 0x0000_0000 The ACTL_ACIS0 store the shift in slot 0 data of AC-link.
W90P710CD/W90P710CDG AC-link input slot 1 (ACTL_ACIS1) REGISTER ACTL_ACIS1 ADDRESS R/W 0xFFF0_9040 R DESCRIPTION RESET VALUE AC-link in slot 1 0x0000_0000 The ACTL_ACIS1 stores the shift in slot 1 data of AC-link. 31 30 29 28 27 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 4 R_INDEX[6] 3 2 R_INDEX[5:0] BITS [31:9] [8:2] 1 0 SLOT_REQ[1:0] DESCRIPTIONS Reserved - R_INDEX[6:0] Register index.
W90P710CD/W90P710CDG AC-link input slot 2 (ACTL_ACIS2) REGISTER ACTL_ACIS2 ADDRESS R/W 0xFFF0_9044 R DESCRIPTION RESET VALUE AC-link in slot 2 0x0000_0000 The ACTL_ACIS2 stores the shift in slot 2 data of AC-link. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 RD[15:8] 7 6 5 4 RD[7:0] BITS DESCRIPTIONS [31:16] Reserved [15:0] RD[15:0] AC-link read data.
W90P710CD/W90P710CDG 6.12 Universal Asynchronous Receiver/Transmitter Controller Asynchronous serial communication block include 4 UART blocks and accessory logic. They can be described as follow: • UART0 It is merely a general purpose UART. It does not include any accessory function.
W90P710CD/W90P710CDG • Accessory Function : IrDA SIR (optional) I/O Pin : TXD2, RXD2. I/O Pin Share with : UART1 (Bluetooth function) UART3 It is also merely a general purpose UART. It does not include any accessory function. It share four I/O pins with AC97/I2S.
W90P710CD/W90P710CDG 6.12.1 UART0 UART0 is a general UART block. It has not Modem I/O signals. More detail function description, please refer to section 7.12.5 General UARTcontroller description Table 6.12.1.
W90P710CD/W90P710CDG Table 6.12.2.
W90P710CD/W90P710CDG BITS [31:3] DESCRIPTIONS Reserved UBCR is a 3 bits register which is used to select clock source to generate suitable baud rate: 000: 15Mhz from external crystal [2:0] UBCR 100: 30Mhz divided from PLL 480Mhz 101: 43.6Mhz divided from PLL 480Mhz 110: 48Mhz divided from PLL 480Mhz 111: 60Mhz divided from PLL 480Mhz 6.12.3 UART2 UART2 contains 2 features: general UART and IrDA SIR decoder/encoder. UART has not modem function. Please read the spec of section 7.12.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 3 2 Reserved INV_RX INV_TX Reserved Reserved LB BITS TX_SELECT IrDA_EN DESCRIPTIONS [31:7] Reserved [6] INV_RX [5] INV_TX [4:3] Reserved Reserved 1: Inverse RX input signal 0: No inversion 1: Inverse TX output signal 0: No inversion Reserved IrDA loop back mode for self test.
W90P710CD/W90P710CDG 6.12.4 UART3 UART3 is a general UART block. It has not Modem I/O signals. More detail general UART function description, please refer to next section 7.12.5 General UART controller. Table 6.12.4.
W90P710CD/W90P710CDG UART3 Modem Status Register (UART3_MSR) REGISTER ADDRESS R/W UART3_MSR 0xFFF8_0318 31 30 R DESCRIPTION RESET VALUE UART 3 Modem Status Register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 3 2 1 0 Reserved Reserved DSR# Reserved Reserved Reserved DDSR Reserved 6.12.
W90P710CD/W90P710CDG y Line break generation and detection y False start bit detection y Full prioritized interrupt system controls y Loop back mode for internal diagnostic testing 6.12.5.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 8-bit Received Data BITS DESCRIPTIONS By reading this register, the UART will return an 8-bit data received from SIN pin (LSB first).
W90P710CD/W90P710CDG UART Interrupt Enable Register (UART_IER) REGISTER OFFSET R/W UART_IER 0x04 R/W 31 30 DESCRIPTION RESET VALUE Interrupt Enable Register (DLAB = 0) 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 4 3 2 1 0 nDBGACK_EN MSIE RLSIE THREIE RDAIE Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 RESERVED BITS [31:5] DESCRIPTIONS Reserved ICE debug mode acknowledge enable 0 = When DBGACK is high, the UART receiver time-out clock wil
W90P710CD/W90P710CDG UART Divider Latch (Low Byte) Register (UART_DLL) REGISTER OFFSET R/W UART_DLL 0x00 R/W 31 30 DESCRIPTION RESET VALUE Divisor Latch Register (LS) (DLAB = 1) 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Baud Rate Divider (Low Byte) BITS [7:0] DESCRIPTIONS Baud Rate Divider (Low Byte) The low byte of the baud rate divider UART Divisor Latch (High Byte) Register (UART_DL
W90P710CD/W90P710CDG This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows Baud Rate = Crystal Clock / {16 * [Divisor + 2]} Note: This definition is different from 16550 UART Interrupt Identification Register (UART_IIR) REGISTER OFFSET R/W UART_IIR 0x08 R 31 30 DESCRIPTION RESET VALUE Interrupt Identification Register 29 28 0x8181_8181 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 FMES 5 RFTL
W90P710CD/W90P710CDG Table 6.12.5.
W90P710CD/W90P710CDG BITS DESCRIPTIONS RX FIFO Interrupt (Irpt_RDA) Trigger Level [7:6] RFITL [7:6] Irpt_RDA Trigger Level (Bytes) 00 01 01 04 10 08 11 14 RFITL [3] [2] [1] [0] DMS DMA Mode Select The DMA function is not implemented in this version. TFR TX FIFO Reset Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO. The TX FIFO becomes empty (TX pointer is reset to 0) after such reset. This bit is returned to 0 automatically after the reset pulse is generated.
W90P710CD/W90P710CDG BITS DESCRIPTIONS Divider Latch Access Bit [7] DLAB 0 = It is used to access RBR, THR or IER. 1 = It is used to access Divisor Latch Registers {DLL, DLM} Break Control Bit [6] BCB When this bit is set to logic 1, the serial data output (SOUT) is forced to the Spacing State (logic 0). This bit acts only on SOUT and has no effect on the transmitter logic.
W90P710CD/W90P710CDG UART Modem Control Register (UART_MCR) REGISTER OFFSET R/W UART_MCR 0x10 R/W 31 30 29 DESCRIPTION RESET VALUE 0x0000_0000 Modem Control Register (Optional) 28 27 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 Reserved BITS [31:5] 4 3 2 1 0 LBME Reserve Reserve Reserved DTR# DESCRIPTIONS Reserved - Loop-back Mode Enable 0 = Disable [4] LBME 1 = When the loop-back mode is enabled, the following
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 3 2 1 0 ERR_RX TE THRE BII FEI PEI OEI RFDR BITS [31:8] DESCRIPTIONS Reserved - RX FIFO Error 0 = RX FIFO works normally [7] ERR_RX 1 = There is at least one parity error (PE), framing error (FE), or break indication (BI) in the FIFO. ERR_RX is cleared when CPU reads the LSR and if there are no subsequent errors in the RX FIFO.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS Parity Error Indicator [2] This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU reads the contents of the LSR. PEI Overrun Error Indicator [1] An overrun error will occur only after the RX FIFO is full and the next character has been completely received in the shift register. The character in the shift register is overwritten, but it is not transferred to the RX FIFO.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:6] Reserved [5] DSR# [4:2] Reserved [1] DDSR [0] Reserved - Complement version of data set ready (DSR#) input (This bit is selected by IP) DSR# State Change (This bit is selected by IP) This bit is set whenever DSR# input has changed state, and it will be reset if the CPU reads the MSR. - Whenever any of MSR [3:0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing MSR is a null operation (not suggested).
W90P710CD/W90P710CDG 6.12.6 High speed UART Controller The High Speed Universal Asynchronous Receiver/Transmitter (HS_UART) performs a serial-toparallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from the CPU.
W90P710CD/W90P710CDG Continued.
W90P710CD/W90P710CDG HSUART Transmit Holding Register (HSUART_THR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_THR 0x00 W Transmit Holding Register (DLAB = 0) Undefined 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 8-bit Transmitted Data BITS DESCRIPTIONS [7:0] By writing to this register, the UART will send out an 8-bit data through the SOUT pin (LSB first).
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:5] Reserved ICE debug mode acknowledge enable 0 = When DBGACK is high, the UART receiver time-out clock will be held 1 = No matter what DBGACK is high or not, the UART receiver timerout clock will not be held [4] nDBGACK_EN [3] MSIE MODEM Status Interrupt (Irpt_MOS) Enable 0 = Mask off Irpt_MOS 1 = Enable Irpt_MOS [2] RLSIE Receive Line Status Interrupt (Irpt_RLS) Enable 0 = Mask off Irpt_RLS 1 = Enable Irpt_RLS [1] THREIE Transmit Holding Register
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:8] Reserved - [7:0] Baud Rate Divisor (Low Byte) The low byte of the baud rate divider HSUART Divisor Latch (High Byte) Register (HSUART_DLM) REGISTER OFFSET HSUART_DLM 0x04 31 30 R/W DESCRIPTION RESET VALUE R/W Divisor Latch Register (MS) (DLAB = 1) 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Baud Rate Divider (High Byte) BITS DESCRIPTIONS
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 FMES 5 RFTLS 4 DMS BITS [31:8] IID NIP DESCRIPTIONS Reserved FIFO Mode Enable Status [7] FMES This bit indicates whether the FIFO mode is enabled or not. Since the FIFO mode is always enable, this bit always shows the logical 1 when CPU is reading this register.
W90P710CD/W90P710CDG Interrupt Control Functions PRIORITY INTERRUPT TYPE ---1 -- None 0110 Highest Receiver Line Status (Irpt_RLS) 0100 Second Received Data Available (Irpt_RDA) Receiver FIFO threshold level is reached Receiver FIFO drops below the threshold level Receiver FIFO Timeout (Irpt_TOUT) Receiver FIFO is nonempty and no activities are occurred in the receiver FIFO during the TOR defined time duration Reading the RBR Transmitter Holing Register Empty (Irpt_THRE) Transmitter holding
W90P710CD/W90P710CDG BITS [31:8] DESCRIPTIONS Reserved RX FIFO Interrupt (Irpt_RDA) Trigger Level [7:4] [3] RFITL DMS RFITL Irpt_RDA Trigger Level (Bytes) 0000 01 0001 04 0010 08 0011 14 0100 30 0101 46 0110 62 others 62 DMA Mode Select The DMA function is not implemented in this version. TX FIFO Reset [2] TFR Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO. The TX FIFO becomes empty (TX pointer is reset to 0) after such reset.
W90P710CD/W90P710CDG HSUART Line Control Register (HSUART_LCR) REGISTER OFFSET HSUART_LCR 0x0C R/W DESCRIPTION RESET VALUE R/W Line Control Register BITS 0x0000_0000 DESCRIPTIONS [31:8] Reserved [7] DLAB [6] BCB [5] SPE [4] EPE [3] PBE [2] NSB Divider Latch Access Bit 0 = It is used to access RBR, THR or IER. 1 = It is used to access Divisor Latch Registers {DLL, DLM}.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 3 2 DLAB BCB SPE EPE PBE NSB WLS HSUART Modem Control Register (HSUART_MCR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_MCR 0x10 R/W Modem Control Register (Optional) 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RTS Reserved Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved
W90P710CD/W90P710CDG Continued. BITS [3:2] DESCRIPTIONS Reserved Complement version of RTS# (Request-To-Send) signal [1] Writing 0x00 to MCR, RTS# bit are set to logic 1’s; RTS# Writing 0x0f to MCR, RTS# bit are reset to logic 0’s.
W90P710CD/W90P710CDG Continued. BITS DESCRIPTIONS Transmitter Holding Register Empty 0 = THR is not empty. [5] THRE 1 = THR is empty. THRE is set when the last data word of TX FIFO is transferred to Transmitter Shift Register (TSR). The CPU resets this bit when the THR (or TX FIFO) is loaded. This bit also causes the UART to issue an interrupt (Irpt_THRE) to the CPU when IER [1]=1.
W90P710CD/W90P710CDG HSUART Modem Status Register (HSUART_MSR) REGISTER OFFSET R/W DESCRIPTION RESET VALUE HSUART_MSR 0x18 R MODEM Status Register (Optional) 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 CTS# Reserved BITS Reserved DCTS DESCRIPTIONS [31:5] Reserved [4] CTS# [3:1] Reserved [0] DCTS Complement version of clear to send (CTS#) input (This bit is selected by IP) C
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 TOIE TOIC BITS [31:8] DESCRIPTIONS Reserved Time Out Interrupt Enable [7] TOIE The feature of receiver time out interrupt is enabled only when TOR [7] = IER[0] = 1. Time Out Interrupt Comparator [6:0] TOIC The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word.
W90P710CD/W90P710CDG 6.13 Timer/Watchdog Controller 6.13.1 General Timer Controller The timer module includes two channels, TIMER0 and TIMER1, which allow you to easily implement a counting scheme for use. The timer can perform functions like frequency measurement, event counting, interval measurement, clock generation, delay timing, and so on. The timer possesses features such as adjustable resolution, programmable counting period, and detailed information.
W90P710CD/W90P710CDG 31 30 29 nDBGACK_EN CEN IE 23 22 21 28 27 26 25 24 CRST CACT Reserved 19 18 17 16 11 10 9 8 3 2 1 0 MODE[1:0] 20 Reserved 15 14 13 12 Reserved 7 6 5 4 PRESCALE[7:0] BITS DESCRIPTIONS [31] nDBGACK_EN [30] CEN [29] IE ICE debug mode acknowledge enable 0 = When DBGACK is high, the TIMER counter will be held 1 = No matter DBGACK is high or not, the TIMER counter will not be held Counter Enable 0 = Stops/Suspends counting 1 = Starts counting Int
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Counter Reset Set this bit will reset the TIMER counter, and also force CEN to 0. [26] CRST 0 = No effect. 1 = Reset Timer’s prescale counter, internal 24-bit counter and CEN. Timer is in Active [25] CACT This bit indicates the counter status of timer. 0 = Timer is not active. 1 = Timer is in active. [24:8] Reserved Reserved Prescale [7:0] PRESCALE Clock input is divided by PRESCALE+1 before it is fed to the counter.
W90P710CD/W90P710CDG BITS [31:24] [23:0] DESCRIPTIONS Reserved TIC Reserved Timer Initial Count This is a 24-bit value representing the initial count. Timer will reload this value whenever the counter is decremented to zero. NOTE1: Never write 0x0 in TIC, or the core will run into unknown state. NOTE2: No matter CEN is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.
W90P710CD/W90P710CDG Timer Interrupt Status Register (TISR) REGISTER TISR 31 ADDRESS R/W 0xFFF8_1018 R/W 30 DESCRIPTION RESET VALUE Timer Interrupt Status Register 29 28 27 0x0000_0000 26 25 24 18 17 16 10 9 8 2 1 0 TIF1 TIF0 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 5 4 3 Reserved BITS DESCRIPTIONS Timer Interrupt Flag 1 This bit indicates the interrupt status of Timer channel 1.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 Reserved 23 22 21 20 19 Reserved 15 14 13 12 11 Reserved 7 6 WTE WTIE 5 4 WTIS BITS [31:11] WTCLK nDBGACK_EN WTTME 3 2 1 0 WTIF WTRF WTRE WTR DESCRIPTIONS Reserved Reserved Watchdog Timer Clock [10] WTCLK This bit is used for deciding whether the Watchdog timer clock input is divided by 256 or not. Clock source of Watchdog timer is Crystal input.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Watchdog Timer Interrupt Enable [6] WTIE 0 = Disable the Watchdog timer interrupt 1 = Enable the Watchdog timer interrupt Watchdog Timer Interval Select These two bits select the interval for the Watchdog timer. No matter which interval is chosen, the reset timeout is always occurred 512 WDT clock cycles later than the interrupt timeout.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Watchdog Timer Reset Enable [1] WTRE Setting this bit will enable the Watchdog timer reset function. 0 = Disable Watchdog timer reset function 1 = Enable Watchdog timer reset function Watchdog Timer Reset [0] WTR This bit brings the Watchdog timer into a known state. It helps reset the Watchdog timer before a timeout situation occurring. Failing to set WTR before timeout will initiates an interrupt if WTIE is set.
W90P710CD/W90P710CDG 6.14 Advanced Interrupt Controller An interrupt temporarily changes the sequence of program execution to react to a particular event such as power failure, watchdog timer timeout, transmit/receive request from Ethernet MAC Controller, and so on. The ARM7TDMI processor provides two modes of interrupt, the Fast Interrupt (FIQ) mode for critical session and the Interrupt (IRQ) mode for general purpose. The IRQ exception is occurred when the nIRQ input is asserted.
W90P710CD/W90P710CDG 6.14.1 Interrupt Sources Table 6.14.
W90P710CD/W90P710CDG AIC Functional Description Hardware Interrupt Vectoring The hardware interrupt vectoring can be used to shorten the interrupt latency. If not used, priority determination must be carried out by software. When the Interrupt Priority Encoding Register (AIC_IPER) is read, it will return an integer representing the channel that is active and having the highest priority.
W90P710CD/W90P710CDG Interrupt Masking Each interrupt source, including FIQ, can be enabled or disabled individually by using the command registers AIC_MECR and AIC_MDCR. The status of interrupt mask can be read in the read only register AIC_IMR. A disabled interrupt doesn’t affect the servicing of other interrupts.
W90P710CD/W90P710CDG ACTION NORMAL MODE Calculate active interrupt ICE/DEBUG MODE Read AIC_IPER Read AIC_IPER Determine and return the vector of the active interrupt Read AIC_IPER Read AIC_IPER Push on internal stack the current priority level Read AIC_IPER Write AIC_IPER Acknowledge the interrupt (Note 1) Read AIC_IPER Write AIC_IPER No effect (Note 2) Read AIC_IPER Notes: y NIRQ de-assertion and automatic interrupt clearing if the source is programmed as level sensitive.
W90P710CD/W90P710CDG AIC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR16 0xFFF8_2040 R/W Source Control Register 16 0x0000_0047 AIC_SCR17 0xFFF8_2044 R/W Source Control Register 17 0x0000_0047 AIC_SCR18 0xFFF8_2048 R/W Source Control Register 18 0x0000_0047 AIC_SCR19 0xFFF8_204C R/W Source Control Register 19 0x0000_0047 AIC_SCR20 0xFFF8_2050 R/W Source Control Register 20 0x0000_0047 AIC_SCR21 0xFFF8_2054 R/W Source Control Register 21 0x0000_0047 AIC
W90P710CD/W90P710CDG AIC Source Control Registers (AIC_SCR1 ~ AIC_SCR31) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR1 0xFFF8_2004 R/W Source Control Register 1 0x0000_0047 AIC_SCR2 0xFFF8_2008 R/W Source Control Register 2 0x0000_0047 yyy yyy yyy yyy yyy AIC_SCR28 0xFFF8_2070 R/W Source Control Register 28 0x0000_0047 AIC_SCR29 0xFFF8_2074 R/W Source Control Register 29 0x0000_0047 AIC_SCR30 0xFFF8_2078 R/W Source Control Register 30 0x0000_0047 AIC_SCR31 0xFFF8_207C R/W S
W90P710CD/W90P710CDG Continued BITS [5:3] DESCRIPTIONS Reserved Reserved Priority Level [2:0] Every interrupt source must be assigned a priority level during initiation. Among them, priority level 0 has the highest priority and priority level 7 the lowest. Interrupt sources with priority level 0 are promoted to FIQ. Interrupt sources with priority level other than 0 belong to IRQ. For interrupt sources of the same priority level that located in the lower channel number has higher priority.
W90P710CD/W90P710CDG AIC Interrupt Active Status Register (AIC_IASR) REGISTER ADDRESS R/W AIC_IASR 0xFFF8_2104 R DESCRIPTION RESET VALUE 0x0000_0000 Interrupt Active Status Register 31 30 29 28 27 26 25 24 IAS31 IAS30 IAS29 IAS28 IAS27 IAS26 IAS25 IAS24 23 22 21 20 19 18 17 16 IAS23 IAS22 IAS21 IAS20 IAS19 IAS18 IAS17 IAS16 15 14 13 12 11 10 9 8 IAS15 IAS14 IAS13 IAS12 IAS11 IAS10 IAS9 IAS8 7 6 5 4 3 2 1 0 IAS7 IAS6 IAS5 IAS4 IAS3 IAS2
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 IS31 IS30 IS29 IS28 IS27 IS26 IS25 IS24 23 22 21 20 19 18 17 16 IS23 IS22 IS21 IS20 IS19 IS18 IS17 IS16 15 14 13 12 11 10 9 8 IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8 7 6 5 4 3 2 1 0 IS7 IS6 IS5 IS4 IS3 IS2 IS1 RESERVED BITS DESCRIPTIONS This register identifies those interrupt channels whose are both active and enabled.
W90P710CD/W90P710CDG BITS [6:2] DESCRIPTIONS Vector When the AIC generates the interrupt, VECTOR represents the interrupt channel number that is active, enabled, and has the highest priority. If the representing interrupt channel possesses a priority level 0, then the interrupt asserted is FIQ; otherwise, it is IRQ. The value of VECTOR is copied to the register AIC_ISNR thereafter by the AIC. This register was restored a value 0 after it was read by the interrupt handler.
W90P710CD/W90P710CDG AIC Interrupt Mask Register (AIC_IMR) REGISTER ADDRESS R/W AIC_IMR 0xFFF8_2114 R DESCRIPTION RESET VALUE 0x0000_0000 Interrupt Mask Register 31 30 29 28 27 26 25 24 IM31 IM30 IM29 IM28 IM27 IM26 IM25 IM24 23 22 21 20 19 18 17 16 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16 15 14 13 12 11 10 9 8 IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 7 6 5 4 3 2 1 0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 RESERVED BITS DESCRIPTIONS [31:1] IM x [
W90P710CD/W90P710CDG The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted interrupt is FIQ or IRQ. If both IRQ and FIQ are equal to 0, it means there is no interrupt occurred. BITS [31:2] DESCRIPTIONS Reserved Reserved IRQ [1]: Interrupt Request [1] IRQ 0 = nIRQ line is inactive. 1 = nIRQ line is active. FIQ [0]: Fast Interrupt Request [0] FIQ 0 = nFIQ line is inactive.
W90P710CD/W90P710CDG AIC Mask Disable Command Register (AIC_MDCR) REGISTER ADDRESS R/W AIC_MDCR 0xFFF8_2124 W DESCRIPTION RESET VALUE Mask Disable Command Register Undefined 31 30 29 28 27 26 25 24 MDC31 MDC30 MDC29 MDC28 MDC27 MDC26 MDC25 MDC24 23 22 21 20 19 18 17 16 MDC23 MDC22 MDC21 MDC20 MDC19 MDC18 MDC17 MDC16 15 14 13 12 11 10 9 8 MDC15 MDC14 MDC13 MDC12 MDC11 MDC10 MDC9 MDC8 7 6 5 4 3 2 1 0 MDC7 MDC6 MDC5 MDC4 MDC3 MDC2 MDC1 RE
W90P710CD/W90P710CDG BITS [31:1] DESCRIPTIONS When the W90P710 is under debugging or verification, software can activate any interrupt channel by setting the corresponding bit in this register. This feature is useful in hardware verification or software debugging. SSCx SSCx: Source Set Command 0 = No effect.
W90P710CD/W90P710CDG AIC End of Service Command Register (AIC_EOSCR) REGISTER ADDRESS R/W W AIC_EOSCR 0xFFF8_2130 DESCRIPTION RESET VALUE End of Service Command Register Undefined 31 30 29 28 27 26 25 24 --- --- --- --- --- --- --- --- 23 22 21 20 19 18 17 16 --- --- --- --- --- --- --- --- 15 14 13 12 11 10 9 8 --- --- --- --- --- --- --- --- 7 6 5 4 3 2 1 0 --- --- --- --- --- --- --- --- BITS [31:0] DESCRIPTIONS EOSCR This regis
W90P710CD/W90P710CDG BITS [31:1] [0] DESCRIPTIONS Reserved TEST Reserved This register indicates whether AIC_IPER will be cleared or not after been read. If bit0 of AIC_TEST has been set, ICE or debug monitor can read AIC_IPER for verification and the AIC_IPER will not be cleared automatically. Write access to the AIC_IPER will perform the interrupt stacking in this mode. TEST: ICE/Debug mode 0 = normal mode. 1 = ICE/Debug mode.
W90P710CD/W90P710CDG 6.15 General-Purpose Input/Output The General-Purpose Input/Output (GPIO) module possesses 71 pins and serves multiple function purposes. Each port can be configured by software to meet various system configurations and design requirements. Software must configure each pin before starting the main program.
W90P710CD/W90P710CDG Table 6.16.
W90P710CD/W90P710CDG Table 6.16.
W90P710CD/W90P710CDG 6.15.
W90P710CD/W90P710CDG GPIO Control Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG5 0xFFF8_3050 R/W GPIO port5 configuration register 0x0000_0000 GPIO_DIR5 0xFFF8_3054 R/W GPIO port5 direction control register 0x0000_0000 GPIO_DATAOUT5 0xFFF8_3058 R/W GPIO port5 data output register 0x0000_0000 GPIO_DATAIN5 0xFFF8_305C R GPIO_CFG6 0xFFF8_3060 R/W GPIO port6 configuration register 0x0000_0000 GPIO_DIR6 0xFFF8_3064 R/W GPIO port6 direction control
W90P710CD/W90P710CDG PT0CFG0 11 Name 10 Type Name 00 01 Type Name Type Name Type O GPIO0 I/O AC97RESET PORT00 USB_PWREN O nIRQ4 or I2SMCLK PT0CFG1 11 Name 10 Type Name 00 01 Type Name Type Name Type O GPIO1 I/O AC97DATAI PORT0_1 DTR3 O PWM0 O or I2SDATAI PT0CFG2 11 Name 10 Type Name 00 01 Type Name Type Name Type O GPIO2 I/O AC97DATAO PORT0_2 DSR3 I PWM1 O or I2SDATAO PT0CFG3 11 10 00 01 Name Type Name Type TXD3 O PWM2 O Name Type Name
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 RESERVED 23 22 21 20 19 RESERVED 15 14 PUPEN0[3:0] 13 12 11 10 9 8 2 1 0 RESERVED 7 6 5 4 3 RESERVED OMDEN0[4:0] Bits [31:20] Description RESERVED GPIO3 -GPIO0 port pin internal pull-up resister enable There are 4 bits for this register, the corresponding bit is set to “1” will enable pull-up resister on IO pin. 1 = enable [19:16] 0 = disable PUPEN0 After power on the pull-up resisters are disabled.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 RESERVED DATAOUT0 BITS [31:5] [4:0] DESCRIPTION RESERVED - DATAOUT0 PORT0 data output value Writing data to this register will reflect the data value on the corresponding pin when it is configured as general output pin. And writing data to reserved bits is not effective.
W90P710CD/W90P710CDG GPIO Port1 Configuration Register (GPIO_CFG1) REGISTER ADDRESS GPIO_CFG1 31 0xFFF8_3010 30 R/W DESCRIPTION R/W 29 RESET VALUE GPIO port1 configuration register 28 27 0x0000_0000 26 25 24 18 17 16 RESERVED 23 22 21 20 19 RESERVED 15 14 13 PT1CFG7 7 PT1CFG9 12 11 PT1CFG6 6 5 PT1CFG3 PT1CFG8 10 9 PT1CFG5 4 3 PT1CFG2 8 PT1CFG4 2 1 PT1CFG1 0 PT1CFG0 *In the following pin definition, mark with shading is default function.
W90P710CD/W90P710CDG 11 PT1CFG5 Name PORT1_5 10 Type VD13 Name Type Name Type Name Type SC0_PWR O SD_DAT2 I/O GPIO25 I/O PORT1_6 10 Type VD14 Name PORT1_7 Type Name Type Name Type SC0_PRES O SD_DAT1 I/O GPIO26 I/O PORT1_8 Type Name Type Name Type SC0_RST O SD_DAT0 I/O GPIO27 I/O PORT1_9 01 Type Name Type Name Type SC0_CLK O SD_CLK O GPIO28 I/O 10 Type VD17 00 Name 11 Name 00 Type 10 VD16 PT1CFG9 01 Name 11 Name 00 Type 10 VD15 PT1CF
W90P710CD/W90P710CDG BITS [31:26] DESCRIPTION RESERVED - [25:16] PUPEN1 GPIO51 ~ GPIO42 port pins internal pull-up resister enable This is a 10-bit registers, set corresponding bit to “1” will enable pull up resister in IO pin. 1 = enable 0 = disable After power on the resisters are disabled. [15:10] RESERVED - OMDEN1 PIO51 ~ GPIO42 output mode enable 1 = enable 0 = disable NOTE: Output mode enable bits are valid only when bit PT1CFG9-0 is configured as general purpose I/O mode.
W90P710CD/W90P710CDG GPIO Port1 Data Input Register (GPIO_DATAIN1) REGISTER GPIO_DATAIN1 31 ADDRESS R/W 0xFFF8_301C R/W 30 29 DESCRIPTION RESET VALUE GPIO port1 data input register 28 27 0xXXXX_XXXX 26 25 24 18 17 16 10 9 8 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 DATAIN1[9:8] 4 3 2 1 0 DATAIN1[7:0] BITS DESCRIPTION [31:10] RESERVED [9:0] DATAIN1 Port1 input data register The DATAIN1 indicates the status of each GPIO29~GPIO20 pin regardle
W90P710CD/W90P710CDG *In the following pin definition, mark with shading is default function.
W90P710CD/W90P710CDG 11 PT2CFG9 PORT2_9 10 00 01 Name Type Name Type Name Type Name Type VD17 O KPROW1 O PHY_MDC O GPIO51 I/O GPIO Port2 Direction Register (GPIO_DIR2) REGISTER ADDRESS GPIO_DIR2 31 R/W 0xFFF8_3024 30 R/W 29 DESCRIPTION GPIO port2 in/out direction control and pull-up enable register 28 27 26 RESERVED 23 22 21 RESET VALUE 25 0x0000_0000 24 PUPEN2[9:8] 20 19 18 17 16 10 9 8 PUPEN2[7:0] 15 14 13 12 11 RESERVED 7 6 5 OMDEN2[9:8] 4 3 2
W90P710CD/W90P710CDG PGPIO Port2 Data Output Register (GPIO_DATAOUT2) REGISTER GPIO_DATAOUT2 31 ADDRESS R/W 0xFFF8_3028 R/W 30 29 28 DESCRIPTION RESET VALUE GPIO port2 data output register 27 0x0000_0000 26 25 24 18 17 16 10 9 8 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 DATAOUT2[9:8] 4 3 2 1 0 DATAOUT2[7:0] BITS [31:10] DESCRIPTION RESERVED PORT2 data output value [9:0] Writing data to this register will reflect the data value on the corres
W90P710CD/W90P710CDG BITS [31:10] DESCRIPTION RESERVED Port2 input data register [9:0] The DATAIN2 indicates the status of each GPIO42~GPIO51 pin regardless of its operation mode. The reserved bits will be read as 0s.
W90P710CD/W90P710CDG 11 PT3CFG3 Name PORT3_3 Type RESERVED Name Type Name Type Name Type VD19 O D27 I/O GPIO63 I/O PORT3_4 RESERVED Name Type Name Type Name Type VD20 O D28 I/O GPIO64 I/O PORT3_5 RESERVED Name Type Name Type Name Type VD21 O D29 I/O GPIO65 I/O PORT3_6 RESERVED Name Type Name Type Name Type VD22 O D30 I/O GPIO66 I/O PORT3_7 01 10 Type RESERVED 00 Name 11 PT3CFG7 01 10 Type 00 Name 11 PT3CFG6 01 10 Type 00 Name 11
W90P710CD/W90P710CDG BITS DESCRIPTION [31:24] RESERVED - [23:16] PUPEN2 After power on, the registers are disabled. RESERVED GPIO67 ~ GPIO60 port pin internal pull-up resister enable 1 = enable 0 = disable After power on the pull-up registers are disabled OMDEN2 GPIO67 ~ GPIO60 output mode enable 1 = enable 0 = disable NOTE: Output mode enable bits are valid only when bit PT3CFG7-0 is configured as general purpose I/O mode.
W90P710CD/W90P710CDG GPIO Port3 Data Input Register (GPIO_DATAIN3) REGISTER GPIO_DATAIN3 31 ADDRESS R/W 0xFFF8_303C R/W 30 29 DESCRIPTION RESET VALUE GPIO port3 data input register 28 27 0xXXXX_XXXX 26 25 24 18 17 16 10 9 8 2 1 0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 DATAIN3[7:0] BITS [31:8] DESCRIPTION RESERVED Port3 input data register [7:0] The DATAIN3 indicates the status of each GPIO67~GPIO60 pin regardless of its operation mod
W90P710CD/W90P710CDG *In the following pin definition, mark with shading is default function.
W90P710CD/W90P710CDG 11 PT4CFG8 Name PORT4_8 PT4CFG9 Type PT4CFG10 Name Type RESERVED 11 10 Type Name Type RESERVED 11 10 Type Name Type Name Type nWBE2/SDQM2 I/O GPIO68 I/O 00 Name Type Name Type nWBE3/SDQM3 I/O GPIO69 I/O 01 Name RESERVED 00 01 RESERVED Name PORT4_10 01 RESERVED Name PORT4_9 10 Type nIRQ5 00 Name Type Name Type nWAIT I GPIO70 I/O GPIO Port4 Direction Register (GPIO_DIR4) REGISTER ADDRESS GPIO_DIR4 31 R/W 0xFFF8_3044 30 R/W
W90P710CD/W90P710CDG Continued BITS DESCRIPTION GPIO70~GPIO68 and GPIO59~GPIO52 output mode enable 1 = enable 0 = disable [10:0] OMDEN4 NOTE: Output mode enable bits are valid only when bit PT4CFG10-0 is configured as general purpose I/O mode. Each port pin can be enabled individually by setting the corresponding control bit.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 DATAIN4[10:8] 5 4 3 2 1 0 DATAIN3[7:0] BITS [31:11] DESCRIPTION RESERVED Port4 input data register [10:0] The DATAIN4 indicates the status of each GPIO52~GPIO59, GPIO68 and GPIO69 pin regardless of its operation mode.
W90P710CD/W90P710CDG PT5CFG1 PORT5_1 PT5CFG2 PORT5_2 PT5CFG3 PORT5_3 PT5CFG4 PORT5_4 PT5CFG5 PORT5_5 PT5CFG6 PORT5_6 PT5CFG7 PORT5_7 PT5CFG8 PORT5_8 11 Name 10 Type Name Type RESERVED RESERVED 11 10 Name Type Name Type RESERVED 11 10 Type Name Name Type Name Type RXD0 I GPIO6 I/O 00 01 RESERVED Name 00 01 Name Type Name Type TXD1 O GPIO7 I/O 00 01 Type RESERVED RESERVED 11 10 Name Type Name Type RXD1 I GPIO8 I/O 00 01 Name Type Name Type Nam
W90P710CD/W90P710CDG PT5CFG9 PORT5_9 PT5CFG10 PORT5_10 PT5CFG11 PORT5_11 PT5CFG12 PORT5_12 PT5CFG13 PORT5_13 PT5CFG14 PORT5_14 11 10 00 01 Name Type Name Type Name Type Name Type KPROW2 O SSPRXD I/O SDA1 I/O GPIO14 I/O 11 Name 10 Type RESERVED Name Type Name Type Name Type USBPWREN O nWDOG O GPIO15 I/O 11 Name 10 Type Name RESERVED Type RESERVED Type Name Type nIRQ0 I GPIO16 I/O Name 00 01 Name Type Name Type Name Type USBOVCUR I nIRQ1 I GP
W90P710CD/W90P710CDG 31 30 29 28 RESERVED 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 PUPEN5[14:8] 23 22 21 20 PUPEN5[7:0] 15 14 13 12 RESERVED OMDEN5[14:8] 7 6 5 4 3 OMDEN5[7:0] BITS DESCRIPTION [31] RESERVED [30:16] PUPEN5 [15] RESERVED [14:0] GPIO19 ~ GPIO5 port pin internal pull-up resister enable 1 = enable 0 = disable GPIO19 ~ GPIO5 output mode enable 1 = output mode 0 = input mode NOTE: Output mode enable bits are valid only when bit PT5CFG9-0 is configured a
W90P710CD/W90P710CDG BITS [31:15] DESCRIPTION RESERVED PORT5 data output value [14:0] Writing data to this register will reflect the data value on the corresponding port5 pin when it is configured as general purpose output pin. And writing data to reserved bits is not effective.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 RESERVED 23 22 21 PT6CFG11 15 19 PT6CFG10 14 13 PT6CFG7 7 20 PT6CFG9 12 11 PT6CFG6 6 5 PT6CFG3 PT6CFG8 10 9 PT6CFG5 4 3 PT6CFG2 8 PT6CFG4 2 1 PT6CFG1 0 PT6CFG0 *In the following pin definition, mark with shading is default function.
W90P710CD/W90P710CDG PT6CFG5 PORT6_5 PT6CFG6 PORT6_6 PT6CFG7 PORT6_7 PT6CFG8 PORT6_8 PT6CFG9 PORT6_9 PT6CFG10 PORT6_10 PT6CFG11 PORT6_11 11 Name 10 Type RESERVED Name Type Name Type Name Type KPCOL1 I VD1 O GPIO35 I/O 11 Name 10 Type RESERVED Type Name Type Name Type KPCOL2 I VD2 O GPIO36 I/O 10 Type RESERVED Type Name Type Name Type KPCOL3 I VD3 O GPIO37 I/O 10 Type RESERVED Type Name Type Name Type KPCOL4 I VD4 O GPIO38 I/O 10 Type RESERVED
W90P710CD/W90P710CDG 31 30 29 28 27 26 RESERVED 23 22 25 24 PUPEN6[11:8] 21 20 19 18 17 16 10 9 8 PUPEN6[7:0] 15 14 13 12 11 RESERVED 7 6 OMDEN6[11:8] 5 4 3 2 1 0 OMDEN6[7:0] BITS [31:27] DESCRIPTION RESERVED - [26:16] PUPEN6 GPIO30 ~GPIO41 port pin internal pull-up resister enable 1 = enable 0 = disable [15:13] RESERVED [12:0] GPIO41 ~ GPIO30 output mode enable 1 = output mode 0 = input mode NOTE: Output mode enable bits are valid only when bit PT6CFG11-0 is co
W90P710CD/W90P710CDG BITS [31:12] DESCRIPTION RESERVED PORT6 data output value [11:0] Writing data to this register will reflect the data value on the corresponding port6 pin when it is configured as general purpose output pin.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 3 2 1 0 DBEN3 DBEN2 DBEN1 DBEN0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 RESERVED 4 DBCLKSEL BITS [31:7] DESCRIPTION RESERVED Debounce Clock Selection [6:4] DBCLKSEL These 3 bits are used to select the clock rate for de-bouncer circuit.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 3 2 1 0 EnINT4 DBE4 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 EnINT5 DBE5 5 4 ISTYPE5 BITS [31:8] ISTYPE4 DESCRIPTION RESERVED Enable INT5 Setting this bit 1 to enable extend interrupt 5.
W90P710CD/W90P710CDG Continued BITS [3] [2] DESCRIPTION EnINT4 Enable INT4 Setting this bit 1 to enable extend interrupt 4 1 = Enable interrupt 4 0 = Disable interrupt 4 The AIC interrupt channel 31 is reserved for interrupt 5 and 4 (wire-OR), if this bit is set and interrupt 4 occur, then it will send an interrupt request signal into AIC module.
W90P710CD/W90P710CDG BITS [31:2] DESCRIPTION RESERVED Interrupt 5 status [1] INT5 When interrupt input is detected with ISTYPE5 triggered condition, this flag will be set. It must be cleared by software. 1 = interrupt detected. 0 = No interrupt Interrupt 4 status [0] INT4 When interrupt input is detected with ISTYPE4 triggered condition, this flag will be set. It must be cleared by software. 1 = interrupt 4 is detected.
W90P710CD/W90P710CDG 6.16 Real Time Clock Real Time Clock (RTC) block can be operated by independent power supply while the system power is off. The RTC block utilizes an external crystal to generate 32.768 KHz clock. The RTC can transmit data to CPU as BCD values. The data include the time by second, minute, hour and the date by day, month, and year. In addition, to reach better frequency accuracy, the RTC counter can be adjusted by software.
W90P710CD/W90P710CDG Tick Time interrupt: RTC block use a counter to calibrate the tick time count value. When the value in counter reaches zero, RTC will issue an interrupt. RTC register property: When system power is off but RTC power is on, data stored in RTC registers will not be lost except RTC_TSSR, RTC_RIER and RTC_RIIR. Because of difference between RTC clock and system clock, every time user write new data to any one register, the register will be updated until 2 RTC clock later (60us).
W90P710CD/W90P710CDG 6.16.
W90P710CD/W90P710CDG BITS DESCRIPTIONS INIR [31:0]: [31:0] INIR The INIR register is used to replace hardware reset circuit. User must write INIR as “0xa5eb_1357” after RTC is power on. INIR [0]: R/W. Once RTC INIR has been written, user can access this bit to find out whether RTC reset signal is pulled high.
W90P710CD/W90P710CDG RTC Frequency Compensation Register (RTC_FCR) REGISTER RTC_FCR ADDRESS R/W DESCRIPTION RESET VALUE 0xFFF8_4008 R/W RTC Frequency Compensation Register 31 30 29 28 0X0000_0700 27 26 25 24 19 18 17 16 11 10 9 8 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 FCR_int 5 4 3 Reserved FCR_fra BITS [31:12] 2 DESCRIPTIONS Reserved FCR [11:8]: Integer part [11:8] FCR_int Integer part of detected value FCR[11:8] Integer part of detecte
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Frequency counter measurement: 32773.65Hz Example 1 Integer part: 32773 => FCR [11:8] = 0xc Fraction part: 0.65 X 60 = 39(0x27) => FCR[5:0]=0x27 FCR Calibration Frequency counter measurement: 32765.27Hz Example 2 Integer part: 32765=> FCR [11:8] = 0x4 Fraction part: 0.27 X 60 = 16.
W90P710CD/W90P710CDG RTC Calendar Loading Register (RTC_CLR) REGISTER RTC_CLR ADDRESS R/W DESCRIPTION RESET VALUE 0xFFF8_4010 R/W RTC Calendar Loading Register 31 30 29 28 0X0005_0101 27 26 25 24 19 18 17 16 9 8 1 0 Reserved 23 22 21 20 Hi_year 15 14 Lo_year 13 12 Reserved 7 6 11 10 Hi_mon 5 Reserved Lo_mon 4 3 Hi_day 2 Lo_day Note: CLR is a BCD digit counter and RTC will not check loaded data.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved BITS [31:1] 24Hr/12Hr DESCRIPTIONS Reserved 24Hr/12Hr : 24hour / 12 hour mode selection It indicate that TLR and TAR are in 24-hour mode or 12-hour mode 1 = select 24-hour time scale 0 = select 12-hour time scale with am and pm indication [0] 24Hr/12Hr 24-hour time scale 12-hour time scale 24-hour time scale 12-hour time sc
W90P710CD/W90P710CDG RTC Day of the Week Register (RTC_DWR) REGISTER RTC_DWR 31 ADDRESS R/W DESCRIPTION RESET VALUE 0xFFF8_4018 R/W Day of the Week Register 30 29 28 0X0000_0006 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved DWR[2:0] BITS [31:3] DESCRIPTIONS Reserved DWR[2:0] : Day of the Week Register [2:0] DWR 0 Sunday 1 Monday 2 Tuesday 3 Wednesday 4 Thursday 5 Friday 6 Saturday R
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 Reserved 23 22 21 Reserved 15 Hi_hr_alarm 14 Reserved 7 13 Hi_hr_alarm 12 11 10 Hi_min_alarm 6 Reserved 20 5 9 8 Lo_min_alarm 4 3 2 Hi_sec_alarm 1 0 Lo_sec_alarm TAR is a BCD digit register and RTC will not check loaded data.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Hi_year_alarm 15 14 Lo_year_alarm 13 12 Hi_mon_ Reserved 7 6 11 Reserved 9 8 Lo_mon_alarm alarm 5 10 4 3 Hi_day_alarm 2 1 0 Lo_day_alarm CAR is a BCD digit register and RTC will not check loaded data.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved BITS LIR[0] DESCRIPTIONS [31:1] Reserved LIR [0]: Real only.
W90P710CD/W90P710CDG BITS DESCRIPTIONS [31:2] Reserved [1] Tick_int_en [0] Alarm_int_en 1 = RTC Time Tick Interrupt and counter enable 0 = RTC Time Tick Interrupt and counter disable 1 = RTC Alarm Interrupt enable 0 = RTC Alarm Interrupt disable RTC Interrupt Indication Register (RTC_RIIR) REGISTER ADDRESS RTC_RIIR 0xFFF8_402C 31 30 R/W DESCRIPTION RESET VALUE R/C RTC Interrupt Indication Register 29 28 0X0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Tick_int_st
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS RTC Alarm Interrupt Indication REGISTER 1 = It indicates that time counter and calendar counter have counted [0] to a specified time recorded in TAR and CAR. RTC alarm interrupt Alarm_int_st has been activated. 0 = It indicates that alarm interrupt has never occurred. Software can Also clear this bit after RTC interrupt has occurred.
W90P710CD/W90P710CDG BITS [31:3] DESCRIPTIONS Reserved RTC Tick Time Interrupt request Interval The TTR [2:0] is used to select tick time interrupt request interval.
W90P710CD/W90P710CDG 6.16.2 RTC Application Note Detect RTC frequency Step1. Configure GPIO register GPIOCFG5[21:20] as “2’b11” Step2. Making use of frequency counter (for example: Agilent 53131A) to detect W90P710 IO Pin “GPIO15/nWDOG/USBPWREN”. Note: Because the parasitic capacitance would slow crystal oscillation, do not connect the probe with 32K crystal directly. RTC application circuit 1. The recommended RTC appliction circuit is ad following: RTCVDD1.8V C1 EXTAL32 C2 XTAL32 2.
W90P710CD/W90P710CDG 6.17 Smart Card Host Interface The Smart Card resides in APB bus. The whole chip of W90P710 operates at voltage level of 3.3 V except Smart Card Interface port's I/O pins that are at 5 V to be compatible with mainstream Smart Card implementations. Advanced power management feature further optimizes power consumption whether in operation or in power down mode.
W90P710CD/W90P710CDG Table 6.12.2.
W90P710CD/W90P710CDG 6.17.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESERVED 23 22 21 20 RESERVED 15 14 13 12 RESERVED 7 6 5 4 TxBDATA[7:0] BITS [31:8] DESCRIPTIONS RESERVED 8-bit Transmit Buffer Data [7:0] TxBDATA By writing to this register, the SCHI will send out an 8-bit data through the SCx_DAT pin. This register is the access port for transmitter FIFO. transmitter FIFO is 16 bytes.
W90P710CD/W90P710CDG BITS [31:11] DESCRIPTIONS RESERVED - ETOR2 TOR2 interrupt enable bit When 24 bit time-out counter decrease to zero, it will set TO2 flag to high. If we set ETOR2 to high, then the 24 bit time-out counters will interrupt CPU to indicate that the time-out count is reached. ETOR1 TOR1 interrupt enable bit When 16 bit time-out counter decrease to zero, it will set TO1 flag to high.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Enable Transmit Buffer Empty interrupt bit [1] ETBREI An ETBREI means interrupt enable bit for TBR (Transmitter Buffer Register) empty condition. An interrupt is issued when TBR is empty and this bit is set to "1". 0 = TBR empty interrupt is disabled. 1 = TBR empty interrupt is enabled.
W90P710CD/W90P710CDG BITS [31:6] [5] [4] DESCRIPTIONS RESERVED - SCPSNT Smart card present line status. User may poll this bit to see SCPSNT pin's voltage level 0 = Smart card has been remove from the reader 1 = Smart card IC is contact with the reader SCPTI SCPSNT toggle interrupt status. A rising/falling edge of SCPSNT signal triggers an interrupt and set this status bit if ESCPTI (IER bit 3) is set to "1" to enable SCPSNT toggle interrupt. 0= No SCPSNT toggle interrupt.
W90P710CD/W90P710CDG Smart Card FIFO control Register (SCHI_SCFR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_SCFR0 0xFFF8_5008 (DLAB = 0) W Interrupt Status Register 0 0x0000_0000 SCHI_SCFR1 0xFFF8_5808 (DLAB = 0) W Interrupt Status Register 1 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 RESERVED 23 22 21 20 RESERVED 15 14 13 12 RESERVED 7 6 5 4 3 2 1 0 RxTL1 RxTL0 PEC2 PEC1 PEC0 TxFRST RxFRST Reserved BITS [31:8] DESCRIPTIONS RESE
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS PEC2, PEC1, PEC0 Parity Error Count. Bits PEC2, PEC1 and PEC0 determine the number of allowed repetitions in reception or in transmission before setting bit PBER in SCSR. The value 000 indicates that, if only one parity error has occurred, bit PE is set; the value 111 indicate that bit PE will be set after 8 parity errors.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 2 1 0 BDLAB DIR NSBE EPE PROT CDP Reserved Reserved BITS [31:8] DESCRIPTIONS RESERVED - BDLAB Baud rate Divisor Latch Access Bit. When this bit is set to a logical "1", users may access baud rate divisor (in 16-bit binary format) through divisor latches (BLH and BLL) of baudrate generator during a read/write operation.
W90P710CD/W90P710CDG Contiuned BITS DESCRIPTIONS [2] CDP Card Detect Polarity. We can use the CDP bit to choose the card present input polarity for different socket application. 0 : the input high means card is present. 1 : the input low means card is present.
W90P710CD/W90P710CDG Smart Card Host Status Register (SCHI_SCSR) REGISTER ADDRESS R/W SCHI_SCSR0 0xFFF8_5014 R Smart card Status Register 0 0x0000_0060 SCHI_SCSR1 0xFFF8_5814 R Smart card Status Register 1 0x0000_0060 31 30 29 DESCRIPTION 28 RESET VALUE 27 26 25 24 19 18 17 16 11 10 9 8 RESERVED 23 22 21 20 RESERVED 15 14 13 12 TOF2 RESERVED 7 SC_RESET 5 4 3 2 1 0 TSRE TBRE SBD NSER PBER OER RDR DESCRIPTIONS RESERVED TOF2, [10:8] TOF0 6 BITS [31:
W90P710CD/W90P710CDG Contiuned BITS [5] [4] [3] [2] [1] [0] DESCRIPTIONS TBRE Transmitter Buffer Register Empty In non-FIFO mode, this bit will be set to a logical 1 when a data byte is transferred from TBR to TSR. If ETBREI of IER is a logical 1, an interrupt is generated to notify host to write the following data bytes. In FIFO mode, this bit is set to "1" when the transmitter FIFO is empty. It is cleared to "0" when host writes data bytes into TBR or FIFO.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 RESERVED 23 22 21 20 19 RESERVED 15 14 13 12 11 RESERVED 7 6 5 4 3 GTR[7:0] BITS [31:8] [7:0] DESCRIPTIONS RESERVED - GTR Guard Time Register value. This register specifies number of stop bits appended in the end of data byte. Bit 7 ~ 0: Guard time values. Default to be 01h.
W90P710CD/W90P710CDG BITS [31:11] DESCRIPTIONS RESERVED PSCK Frequency Selection bit 2, 1 and 0. This selection can adjust power-on /power-offf sequence interval. They select working clock frequency as following table. Default values are 05h. [10:8] PSCKFS2, PSCKFS1, PSCKFS0 SCKFS0, SCKFS1, SCKFS2 SCCLK frequency 000 001 010 011 100 101 110 80MHz 40 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz [6:4] SCKFS2, SCKFS1, SCKFS0 SCCLK Frequency Selection bit 2, 1 and 0.
W90P710CD/W90P710CDG Smart Card Host Test Mode Register (SCHI_TMR) REGISTER SCHI_TMR0 SCHI_TMR1 ADDRESS R/W 0xFFF8_5020 0XFFF8_5820 R/W R/W DESCRIPTION RESET VALUE Test mode Register 0 Test mode Register 1 0x0000_0000 0x0000_0000 This 8 bit register is added in order to allow better testability of the Smart Card host. Currently only bit 1 is utilized. In the future, other bits can be used to program the host to improve testability on the testing platform.
W90P710CD/W90P710CDG BITS [31:2] DESCRIPTIONS RESERVED - [1] SCRST_L Smart card Reset pin control bit Software driver controls this bit directly which in turn determines the SCRST_L signal to the Smart Card. ‘0’ or ‘1’ in this bit drives ‘0’ or ‘1’ respectively on the SCRST_L signal. This feature was first added to allow the SCRST_L to be pulled high at a quicker rate during the reset phase to improve testability.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 nDBGACK_EN2 TOC8 3 2 RESERVED 23 22 21 20 RESERVED 15 14 13 12 RESERVED 7 6 nDBGACK_EN1 TOC5 5 TOC4 BITS [31:12] 4 TOC3 nDBGACK_EN0 TOC2 TOC7 TOC6 1 TOC1 0 TOC0 DESCRIPTIONS RESERVED ICE Debug mode Acknowledge enable for time-out counter 2 [11] nDBGACK_EN2 0 = When DBGACK is high, the timer clock will be held 1 = No matter what DBGACK is high or not, the timer clock will not be held.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS TOC8, TOC7, TOC6 (Time Out Configuration) control 24 bit timeout counter 2 configuration. TOC8, TOC7, TOC6 value 000 001 010 TOC8, [10:8] TOC7, TOC6 011 100 OPERATION MODE 24 bit counter 2 is stopped Counting the value stored in register TOIR 2 is started after 001b is written in register in register TOC. An interrupt is given if enabled, and bit TO2 is set within register SCSR when the terminal count is reached.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS TOC5, TOC4, TOC3 (Time Out Configuration) control 16 bit timeout counter 1 configuration. TOC5, [6:4] TOC5, TOC4, TOC3 value OPERATION MODE 000 001 16 bit counter 1 is stopped Counting the value stored in register TOIR 1 is started after 001b is written in register in register TOC. An interrupt is given if enabled, and bit TO1 is set within register SCSR when the terminal count is reached.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS TOC5, TOC4, TOC3 (Time Out Configuration) control 8 bit time-out counter 0 configuration. TOC2, TOC1, TOC0 value 000 001 TOC2, [2:0] 010 TOC1, TOC0 011 100 OPERATION MODE 8 bit counter 0 is stopped Counting the value stored in register TOIR 0 is started after 001b is written in register in register TOC. An interrupt is given if enabled, and bit TO0 is set within register SCSR when the terminal count is reached.
W90P710CD/W90P710CDG Smart Card Host Time-out Initial Register 0 (SCHI_TOIR 0) REGISTER ADDRESS R/W SCHI_TOIR0_0 0xFFF8_502C R/W 8 bit Time out initial Register 0 0x0000_0000 SCHI_TOIR0_1 0xFFF8_582C R/W 8 bit Time out initial Register 1 0x0000_0000 31 30 29 DESCRIPTION 28 RESET VALUE 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESERVED 23 22 21 20 RESERVED 15 14 13 12 RESERVED 7 6 5 4 TOIR0[7:0] BITS [31:8] [7:0] DESCRIPTIONS RESERVED - TOIR0 8 bit Time
W90P710CD/W90P710CDG 31 30 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESERVED 20 RESERVED 15 14 13 12 TOIR1[15:8] 7 6 5 4 TOIR1[7:0] BITS DESCRIPTIONS [31:16] [15:0] RESERVED - TOIR1 16 bit Time Out Initial Register 1 The value to load in register TOIR 1 is the number of ETU to count. The time-out counters may only be used when a card is active with a running clock.
W90P710CD/W90P710CDG Smart Card Host Time-Out Data Register 0 (SCHI_TODR0) REGISTER ADDRESS R/W SCHI_TOD0_0 0xFFF8_5038 R 8 bit Time out data Register 0 0x0000_00FF SCHI_TOD0_1 0xFFF8_5838 R 8 bit Time out data Register 1 0x0000_00FF 31 30 DESCRIPTION 29 28 RESET VALUE 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESERVED 23 22 21 15 14 13 20 RESERVED 12 RESERVED 7 6 5 4 TOD0[7:0] BITS [31:8] [7:0] DESCRIPTIONS RESERVED - TOD0 8 bit Time Out Data count Reg
W90P710CD/W90P710CDG BITS [31:16] [15:0] DESCRIPTIONS RESERVED - TOD1 16 bit Time Out Data count Register 1 The value showing in register TOD 1 is the number of ETU to count. The time-out data counters may only be used when a card is active with a running clock. This is 16 bit time-out data register used to show the current counting value.
W90P710CD/W90P710CDG Smart Card Host Buffer Time-Out Data Register (SCHI_BTOR) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE SCHI_BTOR0 0XFFF8_5044 R/W Buffer Time out Data Register 0 0x0000_0000 SCHI_BTOR1 0XFFF8_5844 R/W Buffer Time out Data Register 1 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 RESERVED 23 22 21 20 RESERVED 15 14 13 12 RESERVED 7 BTOIE 6 BTOIC_6 5 BTOIC_5 BITS [31:8] [7] [6:0] 4 BTOIC_4 3 BTOIC_3 2 BTOIC_2 1 0 BTOIC_1 BTOIC_0
W90P710CD/W90P710CDG 31 30 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESERVED 20 RESERVED 15 14 13 12 RESERVED 7 6 5 4 BLL[7:0] BITS [31:8] DESCRIPTIONS RESERVED 8 bit Baud rate divider Latch Low byte register [7:0] This register combining with BLH and CBR determine internal sampling clock frequency. Bit 7 ~ 0: Baud rate divisor latch lower byte values. Default to be 1Fh.
W90P710CD/W90P710CDG BITS [31:8] DESCRIPTIONS RESERVED 8 bit Baud rate divider Latch High byte register [7:0] This register combining with BLL and CBR determine internal sampling clock frequency. Bit 7 ~ 0: Baud rate divisor latch higher byte values. Default to be 00h.
W90P710CD/W90P710CDG 6.17.3 Functional description The following description uses abbreviations to refer to control/status registers and their contents of Smart Card interface as seen in section 7.12.2 z Initialization User needs to program control registers so that ATR (Answer To Reset) data streams can be properly decoded after card insertion. Initialization settings include the following steps where sequential order is irrelevant. 1.
W90P710CD/W90P710CDG convention is for inserted card and chooses a conversion procedure for it. Subsequent incoming data bytes must be passed through a conversion procedure before actually transfers these data bytes to host. Similar conversion procedure must be applied to outgoing data byte before writing to TBR too. For example, the raw data byte for initial character of inverse-convention ATR would be 3Fh.
W90P710CD/W90P710CDG These I/O conditions also apply to socket in power down state (SCPWD = 1) or deselected socket in idle state. Designers of application circuits must take extra care so that no contention occurs when Smart Card interface is in those power-saving states.
W90P710CD/W90P710CDG 6.18 I2C Interface I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Serial, 8-bit oriented bi-directional data transfers can be made up to 100 kbit/s in Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.
W90P710CD/W90P710CDG 6.18.1 I2C Protocol Normally, a standard communication consists of four parts: 1) START or Repeated START signal generation 2) Slave address transfer 3) Data transfer 4) STOP signal generation SCL 1 2 SDA A6 A5 7 8 9 1 2 3-7 8 9 A0 R/W ACK D7 D6 D5 - D1 D0 NACK ACK P S or Sr A4 - A1 MSB LSB MSB P or Sr LSB Fig. 6.18.1.
W90P710CD/W90P710CDG START or Repeated START signal When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal, usually referred to as the S-bit, is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH. The START signal denotes the beginning of a new data transfer. A Repeated START (Sr) is a START signal without first generating a STOP signal.
W90P710CD/W90P710CDG Data Transfer Once successful slave addressing has been achieved, the data transfer can proceed on a byte-bybyte basis in the direction specified by the RW bit sent by the master. Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a Not Acknowledge (NACK), the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle.
W90P710CD/W90P710CDG 6.18.2 I2C Serial Interface Control Registers Map R: read only, W: write only, R/W: both read and write NOTE1: The reset value of I2C_WR0/1 is 0x3F only when SCR, SDR and SER are connected to pull high resistor.
W90P710CD/W90P710CDG BITS [31:12] [11] [10] DESCRIPTIONS Reserved I2C_RxACK I2C_BUSY Reserved Received Acknowledge From Slave (Read only) This flag represents acknowledge from the addressed slave. 0 = Acknowledge received (ACK). 1 = Not acknowledge received (NACK). I2C Bus Busy (Read only) 0 = After STOP signal detected. 1 = After START signal detected. I2C_AL Arbitration Lost (Read only) This bit is set when the I2C core lost arbitration.
W90P710CD/W90P710CDG I2C Prescale Register 0/1 (I2C_DIVIDER 0 /1) REGISTER ADDRESS R/W I2C_DIVIDER0 0xFFF8_6004 R/W I2C Clock Prescale Register 0 0x0000_0000 I2C_DIVIDER1 0xFFF8_6104 R/W I2C Clock Prescale Register 1 0x0000_0000 31 30 29 DESCRIPTION 28 RESET VALUE 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 DIVIDER[15:8] 7 6 5 4 3 DIVIDER[7:0] BITS DESCRIPTIONS Clock Prescale Register [15:0] DIVIDER It is used to pres
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 4 3 2 1 0 START STOP READ WRITE ACK Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 Reserved NOTE: Software can write this register only when I2C_EN = 1. BITS DESCRIPTIONS [31:5] Reserved [4] START [3] STOP Generate Stop Condition Generate stop condition on I2C bus. [2] READ Read Data From Slave Retrieve data from slave. [1] WRITE Write Data To Slave Transmit data to slave.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 Reserved 5 4 3 2 1 0 Reserved SDR SCR Reserved SDW SCW Note: This register is used as software mode of I2C. Software can read/write this register no matter I2C_EN is 0 or 1. But SCL and SDA are controlled by software only when I2C_EN = 0.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Rx [7:0] BITS DESCRIPTIONS [31:8] Reserved [7:0] Rx Reserved Data Receive Register The last byte received via I2C bus will put on this register. The I2C core only used 8-bit receive buffer.
W90P710CD/W90P710CDG BITS DESCRIPTIONS Data Transmit Register The I2C core used 32-bit transmit buffer and provide multi-byte transmit function. Set CSR[Tx_NUM] to a value that you want to transmit. I2C core will always issue a transfer from the highest byte first. For example, if CSR[Tx_NUM] = 0x3, Tx[31:24] will be transmitted first, then Tx[23:16], and so on. [31:0] Tx In case of a data transfer, all bits will be treated as data.
W90P710CD/W90P710CDG 6.19 Universal Serial Interface The USI is a synchronous serial interface performs a serial-to-parallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from CPU. This interface can drive one external peripherals and is seen as the master. It can generate an interrupt signal when data transfer is finished and can be cleared by writing 1 to the interrupt flag.
W90P710CD/W90P710CDG mw_ss_o mw_sclk_o mw_so_o LSB (Tx[0]) Tx[1] Tx[2] Tx[3] Tx[4] Tx[5] Tx[6] MSB (Tx[7]) mw_si_i LSB (Rx[0]) Rx[1] Rx[2] Rx[3] Rx[4] Rx[5] Rx[6] MSB (Rx[7]) CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08, CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1, SSR[SS_LVL]=0 Fig. 6.19.1.2 Alternate Phase SCLK Clock Timing 6.19.
W90P710CD/W90P710CDG USI_Control and Status Register (USI_CNTRL) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_CNTRL 0xFFF8_6200 R/W USI Control and Status Register 31 30 29 28 0x0000_0004 27 26 25 24 19 18 17 16 IE IF 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 SLEEP 7 6 5 11 10 Reserved LSB 3 2 1 0 Tx_NEG Rx_NEG GO_BUSY 4 Tx_BIT_LEN BITS Tx_NUM DESCRIPTIONS [31:18] Reserved [17] IE Interrupt Enable 0 = Disable USI Interrupt.
W90P710CD/W90P710CDG Continued BITS [11] DESCRIPTIONS Reserved Reserved LSB Send LSB First 0 = The MSB is transmitted/received first (which bit in TxX/RxX register that is depends on the Tx_BIT_LEN field in the CNTRL register). 1 = The LSB is sent first on the line (bit TxX[0]), and the first bit received from the line will be put in the LSB position in the Rx register (bit RxX[0]).
W90P710CD/W90P710CDG USI Divider Register (USI_DIVIDER) REGISTER ADDRESS R/W DESCRIPTION RESET VALUE USI_Divider 0xFFF8_6204 R/W USI Clock Divider Register 31 30 29 28 0x0000_0000 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 DIVIDER[15:8] 7 6 5 4 3 DIVIDER[7:0] BITS DESCRIPTIONS Clock Divider Register The value in this field is the frequency divider of the system clock pclk to generate the serial clock on the output usi_sclk_o.
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ASS SS_LVL Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved BITS [3] [2] SSR[1:0] DESCRIPTIONS ASS SS_LVL Automatic Slave Select 0 = If this bit is cleared, slave select signals are asserted and deasserted by setting and clearing related bits in SSR register. 1 = If this bit is set, usi_ss_o signals are generated automatically.
W90P710CD/W90P710CDG USI Data Receive Register 0/1/2/3 (USI_Rx0/1/2/3) REGISTER ADDRESS R/W USI_RX0 0xFFF8_6210 R USI Data Receive Register 0 0x0000_0000 USI_RX1 0xFFF8_6214 R USI Data Receive Register 1 0x0000_0000 USI_RX2 0xFFF8_6218 R USI Data Receive Register 2 0x0000_0000 USI_RX3 0xFFF8_621C R USI Data Receive Register 3 0x0000_0000 31 30 29 DESCRIPTION 28 RESET VALUE 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Rx [31:24] 23 22 21 20 Rx [23:16] 15 14 13
W90P710CD/W90P710CDG 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Tx [31:24] 23 22 21 20 Tx [23:16] 15 14 13 12 Tx [15:8] 7 6 5 4 Tx [7:0] BITS DESCRIPTIONS Data Transmit Register [31:0] Tx The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.
W90P710CD/W90P710CDG 6.20 PWM The W90P710 have 4 channels PWM timers. They can be divided into two groups. Each group has 1 Prescaler, 1 clock divider, 2 clock selectors, 2 16-bit counters, 2 16-bit comparators, 1 Dead-Zone generator. They are all driven by PCLK (80 MHz). Each channel can be used as a timer and issue interrupt independently. Two channels PWM timers in one group share the same prescaler. Clock divider provides each channel with 5 clock sources (1, 1/2, 1/4, 1/8, 1/16).
W90P710CD/W90P710CDG The auto-reload operation copies from PWM_CNR0, PWM_CNR1, PWM_CNR2, PWM_CNR3 to down-counter when down-counter reaches zero. If PWM_CNR0~3 are set as zero, counter will be halt when counter count to zero. If auto-reload bit is set as zero, counter will be stopped immediately. 6.20.2 Modulate Duty Ratio The double buffering function allows PWM_CMR written at any point in current cycle. The loaded value will take effect from next cycle. 6.20.
W90P710CD/W90P710CDG Dead zone generator operation PWM_out1 PWM_out1_n PWM_out1_DZ PWM_out1_n_DZ Dead zone interval 6.20.4 PWM Timer Start procedure 1. Setup clock selector (PWM_CSR) 2. Setup prescaler & dead zone interval (PWM_PPR) 3. Setup inverter on/off, dead zone generator on/off, toggle mode /one-shot mode, and PWM timer off. (PWM_PCR) 4. Setup comparator register (PWM_CMR) 5. Setup counter register (PWM_CNR) 6. Setup interrupt enable register (PWM_PIER) 7. Enable PWM timer (PWM_PCR) 6.20.
W90P710CD/W90P710CDG 6.20.
W90P710CD/W90P710CDG BITS [31:24] DESCRIPTIONS DZI1 DZI1: Dead zone interval register 1, these 8-bit determine dead zone length. The 1 unit time of dead zone length is received from clock selector 2. [23:16] DZI0 DZI0: Dead zone interval register 0, these 8-bit determine dead zone length. The 1 unit time of dead zone length is received from clock selector 0. CP1 : Clock prescaler 1 for PWM Timer channel 2 & 3 [15:8] CP1 Clock input is divided by (CP1 + 1) before it is fed to the counter.
W90P710CD/W90P710CDG CSR3 INPUT CLOCK DIVIDED BY 000 2 001 4 010 8 011 16 100 1 PWM Control Register (PWM_PCR) REGISTER ADDRESS PWM_PCR 0xFFF8_7008 31 30 R/W DESCRIPTION RESET VALUE R/W PWM Control Register 29 28 0x0000_0000 27 26 25 24 19 18 17 16 PCR19 PCR18 PCR17 PCR16 Reserved 23 22 21 20 Reserved 15 14 13 12 11 10 9 8 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 PCR09 PCR08 7 6 5 4 3 2 1 0 PCR07 PCR06 PCR05 PCR04 PCR03 PCR02 PCR01 PCR00 B
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Channel 2 toggle/one shot mode [15] PCR 15 1 = toggle mode 0 = one shot mode Channel 2 Inverter on/off [14] PCR 14 1 = inverter on 0 = inverter off [13] PCR 13 Reserved Channel 2 enable/disable [12] PCR 12 1 = enable 0 = disable Channel 1 toggle/one shot mode [11] PCR 11 1 = toggle mode 0 = one shot mode Channel 1 Inverter on/off [10] PCR 10 1 = inverter on 0 = inverter off [09] PCR 09 Reserved Channel 1 enable/disable [08] PCR 08 1
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Channel 0 toggle/one shot mode [03] PCR 03 1 = toggle mode 0 = one shot mode Channel 0 Inverter on/off [02] PCR 02 1 = inverter on 0 = inverter off [01] PCR 01 Reserved Channel 0 enable/disable [00] PCR 00 1 = enable 0 = disable PWM Counter Register 0/1/2/3 (PWM_CNR0/1/2/3) REGISTER ADDRESS PWM_CNR0 0xFFF8_700C R/W PWM Counter Register 0 0x0000_0000 PWM_CNR1 0xFFF8_7018 R/W PWM Counter Register 1 0x0000_0000 PWM_CNR2 0xFFF8_7024 R/W
W90P710CD/W90P710CDG BITS [31:16] [15:0] DESCRIPTIONS Reserved CNRx CNR: PWM counter/timer buffer. Inserted data range: 65535~0. Unit: 1 PWM clock cycle Note 1: One PWM counter countdown interval = CNR + 1.If CNR is loaded as zero, PWM counter will be stopped. Note 2: Programmer can feel free to write data to CNR at any time, and it will be reloaded when PWM counter reaches zero.
W90P710CD/W90P710CDG PWM Data Register 0/1/2/3 (PWM_PDR 0/1/2/3) REGISTER ADDRESS R/W PWM_PDR0 0xFFF8_7014 R PWM Data Register 0 0x0000_0000 PWM_PDR1 0xFFF8_7020 R PWM Data Register 1 0x0000_0000 PWM_PDR2 0xFFF8_702C R PWM Data Register 2 0x0000_0000 PWM_PDR3 0xFFF8_7038 R PWM Data Register 3 0x0000_0000 31 30 29 DESCRIPTION 28 RESET VALUE 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 PDRx[15:8] 7 6 5 4 3 PDRx[7:0]
W90P710CD/W90P710CDG BITS [31:4] DESCRIPTIONS Reserved - [3] PIER3 Enable/Disable PWM counter channel 3 interrupt request 1 = enable 0 = disable [2] PIER2 Enable/Disable PWM counter channel 2 interrupt request 1 = enable 0 = disable [1] PIER1 Enable/Disable PWM counter channel 1 interrupt request 1 = enable 0 = disable PIER0 Enable/Disable PWM counter channel 0 interrupt request 1 = enable 0 = disable [0] PWM Interrupt Indication Register (PWM_PIIR) REGISTER ADDRESS R/W/C PWM_PIIR 0xFFF
W90P710CD/W90P710CDG 6.21 Keypad Interface W90P710 Keypad Interface (KPI) is an APB slave with 4-row scan output and 8-column scan input. KPI scans an array up to 16x8 with an external 4 to 16 decoder. It can also be programmed to scan 8x8 or 4x8 key array. If the 4x8 array is selected then external decoder is not necessary because the scan signals are dived by W90P710 itself.
W90P710CD/W90P710CDG KPIR[3:0] 4 :16 DECODER W90P710 ROW[[16:0] KPIC[7:0] 16x8 key pad matrix COL[7:0] Fig. 6.21.1 W90P710 Keypad Interface 6.21.
W90P710CD/W90P710CDG 6.21.
W90P710CD/W90P710CDG Continued BITS DESCRIPTION Key pad scan enable [18] ENKP Setting this bit high enable the key scan function. 1 = enable key pad scan 0 = disable key pad scan Key array size [17:16] KSIZE KSIZE Key array size 2’b00 4x8, 3x8, 2x8, 1x8 2’b01 8x8, 7x8, 6x8, 5x8 2’b1x 16x8, 15x8, 14x8, 13x8, 12x8, 11x8, 10x8, 9x8 Debounce terminal count [15:8] DBTC Debounce counter counts the number of consecutive scans that decoded the same keys.
W90P710CD/W90P710CDG 16x8 keys matrix 74138 ROW[15:0] ROW[3:0] COL[7:0] ENCODER W90P710 COL[0] COL[1] COL[2] COL[3] A0 A1 A2 GS IN[7:0] 74148 keypad I/F with 8:3 encoder Fig. 6.21.
W90P710CD/W90P710CDG BITS DESCRIPTION [31:26] RESERVED [25] EN3KY Enable three-keys detection Setting this bit enables hardware to detect 3 keys specified by software Enable three-key reset Setting this bit enable hardware reset when three-key is detected.
W90P710CD/W90P710CDG KeyPad Interface Low Power Mode Configuration Register (KPILPCONF) REGISTER ADDRESS R/W KPILPCOF 0xFFF8_8008 W/R 31 30 29 DESCRIPTION RESET VALUE Low power configuration register 28 27 0x0000_0000 26 25 24 18 17 16 RESERVED 23 22 21 20 19 WAKE 15 14 13 12 11 10 9 8 3 2 1 0 LPWCEN 7 6 5 4 RESERVED LPWR BITS [31:17] DESCRIPTION RESERVED Lower power wakeup enable [16] WAKE Setting this bit enables low power wakeup 1 = wakeup enable 0 = not
W90P710CD/W90P710CDG Key Pad Interface Status Register (KPISTATUS) REGISTER ADDRESS R/W KPISTATUS 0xFFF8_800C R/O 31 30 29 DESCRIPTION key pad status register 28 RESET VALUE 0x0000_0000 27 26 25 24 RESERVED 23 22 21 20 19 18 17 16 RESERVED INT 3 K R S T PDWAKE 3KEY 2KEY 1KEY 15 13 12 11 10 9 8 14 RESERVED 7 KEY1R 6 5 RESERVED 4 3 2 KEY0R BITS [31:22] KEY1C 1 0 KEY0C DESCRIPTION RESERVED Key interrupt [21] INT This bit indicates the key scan interrupt
W90P710CD/W90P710CDG Continued BITS DESCRIPTION Double-key press [17] 2KEY [16] 1KEY [15] RESERVED This bit indicates that 2 keys have been detected. Software can read {KEY1R, KEY1C} and {KEY0R, KEY0C} to know which two keys are pressed. Single-key press This bit indicates that 1 key has been detected. Software can read {KEY0R, KEY0C} to know which key is pressed. KEY1 row address [14:11] KEY1R [10:8] KEY1C [7] RESERVED This value indicates key1 row address.
W90P710CD/W90P710CDG 6.22 PS2 Host Interface Controller W90P710 PS2 host controller interface is an APB slave consisted of PS2 protocol. It is used to connect to your IBM keyboard or other device through PS2 interface. For example, the IBM keyboard will sends scan codes to the host controller, and the scan codes will tell your Keyboard Bios what keys you have pressed or released. Besides Scan codes, commands can also be sent to the keyboard from host.
W90P710CD/W90P710CDG 6.22.1 PS2 Host Controller Interface Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PS2CMD 0xFFF8_9000 R/W PS2 Host Controller Command Register 0x0000_0000 PS2STS 0xFFF8_9004 R/W PS2 Host Controller Status Register 0x0000_0000 PS2SCANCODE 0xFFF8_9008 RO PS2 Host Controller RX Scan Code 0x0000_0000 Register PS2ASCII RO PS2 Host Controller RX ASCII Code 0x0000_0000 Register 0xFFF8_900C 6.22.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Enable write PS2 Host Controller Commands [8] This bit enables the write function of Host controller command to device. Set this bit will start the write process of PS2CMD content and hardware will automatically clear this bit while write process is finished. EnCMD PS2 Host Controller Commands [7:0] This command filed is sent by the Host to the Keyboard. The most common command would be the setting/resetting of the Status Indicators (i.e.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS [3:1] Reserved [0] This Receive Interrupt bit indicates software that Host controller receives one byte data from device. This data is stored at PS2_SCANCODE register. Software needs to write one to this bit to clear this interrupt after reading receiving data in RX_SCAN_CODE register. Note that the reception of the Extend (0xE0) and Release (0xF0) scan code will not cause an interrupt by host.
W90P710CD/W90P710CDG Continued BITS DESCRIPTIONS Receive Extend Byte [8] A handful of the keys on keyboard are extended keys and thus require two more scan code. These keys are preceded by an E0 (hex). This bit indicates software that Host controller receives extended byte (E0). This bit is read only and will update when host has received next data byte. RX_extend PS2 Host Controller Received Data Field [7:0] This field stores the original data content transmitted from device.
W90P710CD/W90P710CDG 7. ELECTRICAL SPECIFICATIONS 7.1 Absolute Maximum Ratings Ambient temperature .................................……………............................. TBD Storage temperature ..................................................…….................... -40 °C ~ +125°C Voltage on any pin ...............................................................…….......... -0.5V ~ 6V Power supply voltage (Core logic) ..............................…...........………..….. -0.5V ~ 1.
W90P710CD/W90P710CDG Table 7.2.1TSMC IO DC Characteristics PARAMETER MIN. TYP. MAX. VIL Input Low Voltage -0.3V 0.8V VIH Input High Voltage 2V 5.5V VT Threshold point 1.46V 1.59V 1.75V VT+ Schmitt trig low to high threshold point 1.47V 1.50V 1.50V VT- Schmitt trig, high to low threshold point 0.90V 0.94V 0.96V II Input leakage current @VI= 3.3V or 0V +/- 10uA Ioz Tri-state output leakage current @Vo =3.
W90P710CD/W90P710CDG 7.2.2 USB Transceiver DC Characteristics SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDI Differential Input Sensitivity DP − DM 0.2 VCM Differential Common Mode Range Includes VDI range 0.8 2.5 V VSE Single Ended Receiver Threshold 0.8 2.0 V VOL Static Output Low Voltage RL of 1.5 KΩ to 3.6 V 0.3 V VOH Static Output High Voltage RL of 15 KΩ to VSS 2.8 3.6 V VCRS Output Signal Crossover Voltage 1.3 2.
W90P710CD/W90P710CDG 7.3.
W90P710CD/W90P710CDG 7.3.3 USB Transceiver AC Characteristics Rise Time CL Differential Data Lines CL Fall Time 90% 90% 10% 10% tR Full Speed: 4 to 20ns at CL = 50pF tF Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF Data Signal Rise and Fall Time USB Transceiver AC Characteristics SYMBOL DESCRIPTION CONDITIONS MIN MAX UNIT TR Rise Time CL = 50 pF 4 20 ns TF Fall Time CL = 50 pF 4 20 ns TRFM Rise/Fall Time Matching 90 110 % TDRATE Full Speed Data Rate 11.97 12.
W90P710CD/W90P710CDG 7.3.4 EMC RMII AC Characteristics The signal timing characteristics conforms to the guidelines specified in IEEE Std. 802.3.
W90P710CD/W90P710CDG PHY_MDC TMDO TMDH PHY_MDIO (Write) valid data TMDS PHY_MDIO (Read) SYMBOL TMDH valid data DESCRIPTION MIN MAX UNIT 15 ns TMDO MDIO Output Delay Time 0 TMDSU MDIO Setup Time 5 ns TMDH MDIO Hold Time 5 ns - 522 -
W90P710CD/W90P710CDG 7.3.
W90P710CD/W90P710CDG 7.3.6 SD Interface AC Characteristics Twl Twh SD_CLK Tpp SD_CMD SD_DAT (Input) Toh Tisu Tih SD_CMD SD_DAT (Output) Tod(max) SYMBOLS DESCRIPTION MIN. TYP. MAX.
W90P710CD/W90P710CDG 7.3.7 AC97/I2S Interface AC Characteristics TCLK_PERIOD AC97_BCLK TOD AC97_DATAO AC97_SYNC TISU TIHD TOH AC97_DATAI SYMBOLS DESCRIPTION MIN TYP. MAX UNIT TCLK_PERIOD AC97 Bit Clock Frequency -- 12.
W90P710CD/W90P710CDG TBCLK_PERIOD I2S_BCLK Tout_delay I2S_DATAO I2S_RLCLK TDOH TDIS TDIH I2S_DATAI SYMBOLS DESCRIPTION MIN MAX UNIT TBCLK_PERIOD IIS Bit Clock Frequency Note:depend on codec spec.
W90P710CD/W90P710CDG 7.3.
W90P710CD/W90P710CDG 7.3.
W90P710CD/W90P710CDG SYMBOL DESCRIPTION MIN MAX UNIT THIGH I2C Clock high time 1 - us TLOW I2C clock low time 1 - us Thd:STA Start condition hold time 1 - us Receive data setup time 0.1 - us Transmit data output delay - 0.5 us Receive data hold time 1 - us Transmit data hold time 0 0.9 us 0.5 - us 1 - us 1.5 - us TSU:DAT THD:DAT TSU:DAT2 SDA setup time (before STOP condition) TSU:STO Stop condition setup time TSU:STA Restart condition setup time 7.3.
W90P710CD/W90P710CDG Tlag FUSI SFRM Tlead SCLK TIH TCLKH TCLKL SSPRXD (RX_NEG =1) TIH TISU SSPRXD (RX_NEG =0) TISU SYMBOL DESCRIPTION MIN MAX UNIT FUSI USI clock frequency - 20 MHz TCLKH USI clock high time 12.5 - ns TCLKL USI clock low time - - ns TISU Data input setup time - 14 ns TIH Data input hold time 0 - ns Tlead USI enable lead time 12.5 - ns Tlag USI enable lag time 12.
W90P710CD/W90P710CDG 7.3.11 PS2 Interface AC Characteristics T4 T3 1st CLK PS2_CLK 2nd CLK 10th CLK 11th CLK T5 T1 PS2_DATA T2 Start Bit Bit 0 Parity Bit Timing for data received from the auxiliary device T7 PS2_CLK T8 1st CLK 2nd CLK 9th CLK 10th CLK 11th CLK T9 Bit 0 PS2_DATA Parity Bit STOP Bit Timing for data send to the auxiliary device SYMBOL DESCRIPTION MIN. MAX.
W90P710CD/W90P710CDG 8. ORDERING INFORMATION PART NUMBER NAME PACKAGE DESCRIPTION W90P710CD LQFP176 176 Leads, body 22 x 22 x 1.4 mm W90P710CDG LQFP176 176 Leads, body 22 x 22 x 1.
W90P710CD/W90P710CDG 9. PACKAGE SPECIFICATIONS 176L LQFP (20X20X1.4 mm footprint 2.
W90P710CD/W90P710CDG 10.
W90P710CD/W90P710CDG Cache Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAHCNF 0xFFF0_2000 R/W Cache configuration register 0x0000_0000 CAHCON 0xFFF0_2004 R/W Cache control register 0x0000_0000 CAHADR 0xFFF0_2008 R/W Cache address register 0x0000_0000 EMC Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAMCMR 0xFFF0_3000 R/W CAM Command Register 0x0000_0000 CAMEN 0xFFF0_3004 R/W CAM Enable Register 0x0000_0000 CAM0M 0xFFF0_3008 R/W CAM0 Mos
W90P710CD/W90P710CDG EMC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM12M 0xFFF0_3068 R/W CAM12 Most Significant Word Register 0x0000_0000 CAM12L 0xFFF0_306C R/W CAM12 Least Significant Word Register 0x0000_0000 CAM13M 0xFFF0_3070 R/W CAM13 Most Significant Word Register 0x0000_0000 CAM13L 0xFFF0_3074 R/W CAM13 Least Significant Word Register 0x0000_0000 CAM14M 0xFFF0_3078 R/W CAM14 Most Significant Word Register 0x0000_0000 CAM14L 0xFFF0_307C R/W CAM1
W90P710CD/W90P710CDG EMC Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RXFSM 0xFFF0_3200 R Receive Finite State Machine Register 0x0081_1101 TXFSM 0xFFF0_3204 R Transmit Finite State Machine Register 0x0101_1101 FSM0 0xFFF0_3208 R Finite State Machine Register 0 0x0001_0101 FSM1 0xFFF0_320C R Finite State Machine Register 1 0x1100_0100 DCR 0xFFF0_3210 DMMIR 0xFFF0_3214 BISTR 0xFFF0_3300 R/W Debug Configuration Register R Debug Mode MAC Information Register R/W BI
W90P710CD/W90P710CDG USB Host Controller Registers Map REGISTER ADDRESS R/W HcRevision 0xFFF0_5000 R HcControl 0xFFF0_5004 HcCommandStatus DESCRIPTION RESET VALUE OpenHCI Registers Host Controller Revision Register 0x0000_0010 R/W Host Controller Control Register 0x0000_0000 0xFFF0_5008 R/W Host Controller Command Status Register 0x0000_0000 HcInterruptStatus 0xFFF0_500C R/W Host Controller Interrupt Status Register 0x0000_0000 HcInterruptEnbale 0xFFF0_5010 R/W Host Controller In
W90P710CD/W90P710CDG USB Device Register Map REGISTER OFFSET R/W DESCRIPTION RESET VALUE USB_CTL 0xFFF0_6000 R/W USB control register 0x0000_0000 VCMD 0xFFF0_6004 R/W USB class or vendor command register 0x0000_0000 USB_IE 0xFFF0_6008 R/W USB interrupt enable register 0x0000_0000 USB_IS 0xFFF0_600C R USB interrupt status register 0x0000_0000 USB_IC 0xFFF0_6010 R/W USB interrupt status clear register 0x0000_0000 USB_IFSTR 0xFFF0_6014 R/W USB interface and string register 0x0
W90P710CD/W90P710CDG USB Device Register Map, continued REGISTER OFFSET R/W RESET VALUE DESCRIPTION EPC_INFO 0xFFF0_6080 R/W USB endpoint C information register 0x0000_0000 EPC_CTL 0xFFF0_6084 R/W USB endpoint C control register 0x0000_0000 EPC_IE 0xFFF0_6 088 R/W USB endpoint C Interrupt Enable register 0x0000_0000 EPC_IC 0xFFF0_608C W USB endpoint C interrupt clear register 0x0000_0000 EPC_IS 0xFFF0_6090 R USB endpoint C interrupt status register 0x0000_0000 EPC_ADDR 0xFFF0
W90P710CD/W90P710CDG SD Control Register Map, continued REGISTER FB0_0 ….. FB0_127 FB1_0 ….. FB1_127 OFFSET R/W DESCRIPTION RESET VALUE 0xFFF0_7400 ….. 0xFFF0_75FC R/W Flash Buffer 0 Undefined 0xFFF0_7800 ...
W90P710CD/W90P710CDG LCDC Control Register Map, continued.
W90P710CD/W90P710CDG LCDC Control Register Map, continued.
W90P710CD/W90P710CDG UART0 Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART0_RBR 0xFFF8_0000 R Receive Buffer Register (DLAB = 0) Undefined UART0_THR 0xFFF8_0000 W Transmit Holding Register (DLAB = 0) Undefined UART0_IER 0xFFF8_0004 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000 UART0_DLL 0xFFF8_0000 R/W UART0_DLM 0xFFF8_0004 R/W UART0_IIR 0xFFF8_0008 R Interrupt Identification Register 0x8181_8181 UART0_FCR 0xFFF8_0008 W FIFO Control Register
W90P710CD/W90P710CDG UART2 Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE UART2_RBR 0xFFF8_0200 R Receive Buffer Register (DLAB = 0) Undefined UART2_THR 0xFFF8_0200 W Transmit Holding Register (DLAB = 0) Undefined Interrupt Enable Register (DLAB = 0) 0x0000_0000 UART2_IER 0xFFF8_0204 R/W UART2_DLL 0xFFF8_0200 R/W UART2_DLM 0xFFF8_0204 R/W UART2_IIR Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) 0x0000_0000 0x0000_0000 0xFFF8_0208 R Inte
W90P710CD/W90P710CDG Timer Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TCR0 0xFFF8_1000 R/W Timer Control Register 0 0x0000_0005 TCR1 0xFFF8_1004 R/W Timer Control Register 1 0x0000_0005 TICR0 0xFFF8_1008 R/W Timer Initial Control Register 0 0x0000_00FF TICR1 0xFFF8_100C R/W Timer Initial Control Register 1 0x0000_00FF TDR0 0xFFF8_1010 R Timer Data Register 0 0x0000_0000 TDR1 0xFFF8_1014 R Timer Data Register 1 0x0000_0000 TISR 0xFFF8_1018 R/C Tim
W90P710CD/W90P710CDG AIC Control Registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR21 0xFFF8_2054 R/W Source Control Register 21 0x0000_0047 AIC_SCR22 0xFFF8_2058 R/W Source Control Register 22 0x0000_0047 AIC_SCR23 0xFFF8_205C R/W Source Control Register 23 0x0000_0047 AIC_SCR24 0xFFF8_2060 R/W Source Control Register 24 0x0000_0047 AIC_SCR25 0xFFF8_2064 R/W Source Control Register 25 0x0000_0047 AIC_SCR26 0xFFF8_2068 R/W Source Control Register 26 0x0000_0
W90P710CD/W90P710CDG GPIO Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG0 0xFFF8_3000 R/W GPIO port0 configuration register 0x0000_0000 GPIO_DIR0 0xFFF8_3004 R/W GPIO port0 direction control register 0x0000_0000 GPIO_DATAOUT0 0xFFF8_3008 R/W GPIO port0 data output register 0x0000_0000 GPIO_DATAIN0 0xFFF8_300C R GPIO port0 data input register 0xXXXX_XXXX GPIO_CFG1 0xFFF8_3010 R/W GPIO port1 configuration register 0x0000_0000 GPIO_DIR1 0xFFF8_3014 R/W GPIO
W90P710CD/W90P710CDG RTC Control Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RTC_INIR 0xFFF8_4000 R/W RTC Initiation Register RTC_AER 0xFFF8_4004 R/W RTC Access Enable Register 0x0000_0000 RTC_FCR 0xFFF8_4008 R/W RTC Frequency Compensation Register 0x0000_0700 RTC_TLR 0xFFF8_400C R/W Time Loading Register 0x0000_0000 RTC_CLR 0xFFF8_4010 R/W Calendar Loading Register 0x0005_0101 RTC_TSSR 0xFFF8_4014 R/W Time Scale Selection Register 0x0000_0001 RTC_DWR 0xFFF8_4018 R/W Day
W90P710CD/W90P710CDG Smart card Host Control Register Map, continued.
W90P710CD/W90P710CDG I2C Register Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE I2C Interface 0 I2C_CSR0 0xFFF8_6000 R/W I2C0 Control and Status Register 0x0000_0000 I2C_DIVIDER0 0xFFF8_6004 R/W I2C0 Clock Prescale Register 0x0000_0000 I2C_CMDR0 0xFFF8_6008 R/W I2C0 Command Register 0x0000_0000 I2C_SWR0 0xFFF8_600C R/W I2C0 Software Mode Control Register 0x0000_003F I2C_RxR0 0xFFF8_6010 R I2C0 Data Receive Register 0x0000_0000 I2C_TxR0 0xFFF8_6014 R/W I2C0 Data Transmit R
W90P710CD/W90P710CDG PWM Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PWM_PPR 0xFFF8_7000 R/W PWM Prescaler Register 0x0000_0000 PWM_CSR 0xFFF8_7004 R/W PWM Clock Select Register 0x0000_0000 PWM_PCR 0xFFF8_7008 R/W PWM Control Register 0x0000_0000 PWM_CNR0 0xFFF8_700C R/W PWM Counter Register 0 0x0000_0000 PWM_CMR0 0xFFF8_7010 R/W PWM Comparator Register 0 0x0000_0000 PWM_PDR0 0xFFF8_7014 R PWM Data Register 0 0x0000_0000 PWM_CNR1 0xFFF8_7018 R/W P
W90P710CD/W90P710CDG Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life.
