Instruction Manual

W90P710CD/W90P710CDG

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Finite State Machine Register 1 (FSM1)

The FSM1 shows the current value of the FSM (Finite State Machine) of the function module in EMC.

The FSM1 is read only and write to it has no effect. The FSM1 is used only for debug.

FSM1 0xFFF0_320C R Finite State Machine Register 1 0x1100_0100

31 30 29 28 27 26 25 24

Reserved

ARB_FSM TxPause_FSM

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

Reserved AHB_FSM

7 6 5 4 3 2 1 0

Reserved

BITS DESCRIPTIONS

[31] Reserved

[30:28] ARB_FSM Internal Arbiter FSM

[27:24] TxPause_FSM Transmit PAUSE Control Frame FSM

[23:14] Reserved -

[13:8] AHB_FSM [13:8]: AHB Master FSM

[7:0]

RESERVED

Debug Configuration Register (DCR)

The DCR is for debug only to multiplex different signal group out. In FPGA emulation, the signals are

outputted to probe pins in emulation board. In real chip, the signals are outputted through the GPIO

pins.

DCR 0xFFF0_3210 R/W Debug Configuration Register 0x0000_003f