Instruction Manual

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 157 - Revision B2
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Enable Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Out Config
BITS DESCRIPTIONS
[31:24] Reserved
-
[23:22] Enable
The Function Enable outputs two function enable signals to
external stimulus circuit.
At this stage, only the bit 22 is used for external random collision
generator. The random collision generator used only in FPGA
emulation.
[21:8] Reserved -
[7:6] Out
The Flag Out provides two output flags to trigger Logic Analyzer for
debug. These two bits can be written at any time.
[5:0] Config
The Configuration controls which group of internal signals can be
multiplexed out for debug. Each group includes 16 signals.
CONFIG SIGNALS CONFIG SIGNALS
6’h00
OUT [6], TransDone, GrantLost,
Trans_CTR [4:0], LAST,
TransCtrExpire,
DMode_AHB_CS [5:0]
6’h01
OUT [6], DMode_TxBuf_CS [6:0]
DMode_TXFSM_CS [7:0]
6’h02
OUT [6], DMode_RXBuf_CS [5:0],
DMode_RXFSM_CS [8:0]
6’h03
OUT [6], TXFIFO_HT, TXFIFO_LT,
DMode_TFF_CS [4:0],
DMode_RFF_CS [7:0]
6’h04
TxBuf_DRDY, TFF_WPTR [5:0],
TX_START,
TXSTART, READ, TFF_RPTR [5:0]
6’h05
WRITE, RFF_WPTR [5:0],
RXFIFO_HT,
RXFIFO_LT, RxBuf_ACK, RFF_RPTR
[5:0]