Instruction Manual

W90P710CD/W90P710CDG
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Continued.
BITS DESCRIPTIONS
[2] EPB_RDY The memory is ready for Endpoint B to access
[1] EPB_RST Endpoint B reset
[0] EPB_EN Endpoint B enable
USB Endpoint B interrupt enable Register (EPB_IE)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
EPB_IE 0xFFF0606C R/W USB endpoint B Interrupt Enable register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved
EPB_CF_IE
EPB_BUS_ERR_IE
EPB_DMA_IE EPB_ALT_IE EPB_TK_IE EPB_STL_IE
BITS DESCRIPTIONS
[31:6] Reserved
[5] EPB_CF_IE Endpoint B clear feature interrupt enable
[4] EPB_BUS_ERR_IE Endpoint B system bus error interrupt enable
[3] EPB_DMA_IE Endpoint B DMA transfer complete interrupt enable
[2] EPB_ALT_IE Endpoint B alternate setting interrupt enable
[1] EPB_TK_IE Endpoint B token input interrupt enable
[0] EPB_STL_IE Endpoint B stall interrupt enable