Instruction Manual

W90P710CD/W90P710CDG

Publication Release Date: September 19, 2006

- 225 - Revision B2

USB Endpoint C Control Register (EPC_CTL)

EPC_CTL 0xFFF06084 R/W USB endpoint C control register 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1 0

Reserved EPC_ZERO EPC_STL_CLR EPC_THRE EPC_STL EPC_RDY EPC_RST EPC_EN

BITS DESCRIPTIONS

[31:7] Reserved

[6] EPC_ZERO Send zero length packet back to HOST

[5] EPC_STL_CLR Clear the Endpoint C stall(WRITE ONLY)

[4] EPC_THRE

Endpoint C threshold (only for ISO)

1: once available space in FIFO over 16 bytes, DMA accesses

memory

0: once available space in FIFO over 32 bytes, DMA accesses

memory

[3] EPC_STL Set the Endpoint C stall

[2] EPC_RDY The memory is ready for Endpoint C to access

[1] EPC_RST Endpoint C reset

[0] EPC_EN Endpoint C enable