Instruction Manual

W90P710CD/W90P710CDG
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6.9.2 Register Mapping
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
SD Registers (6)
SDGCR 0xFFF0_0000 R/W SD Global Control Register 0x0000_0000
SDDSA 0xFFF0_0004 R/W
SD DMA Transfer Starting Address
Register
0x0000_0000
SDBCR 0xFFF0_7008 R/W SD DMA Byte Count Register 0x0000_0000
SDGIER 0xFFF0_700C R/W SD Global Interrupt Enable Register 0x0000_0000
SDGISR 0xFFF0_7010 R/W SD Global Interrupt Status Register 0x0000_0000
SDBIST 0xFFF0_7014 R/W SD BIST Register 0x0000_0000
Secure Digital Registers (8)
SDICR 0xFFF0_7300 R/W SD Interface Control Register 0x0000_0000
SDHIIR 0xFFF0_7304 R/W SD Host Interface Initial Register 0x0000_0018
SDIIER 0xFFF0_7308 R/W SD Interface Interrupt Enable Register 0x0000_0000
SDIISR 0xFFF0_730C R/W
SD Interface Interrupt Status Register
0x0000_00XX
SDAUG 0xFFF0_7310 R/W SD Command Argument Register 0x0000_0000
SDRSP0 0xFFF0_7314 R
SD Receive Response Token Register
0
0xXXXX_XXXX
SDRSP1 0x0000_0318 R
SD Receive Response Token Register
1
0x0000_XXXX
SDBLEN 0xFFF0_731C R/W SD Block Length Register 0x0000_0000
Internal Buffer Access Register (256)
FB0_0
…..
FB0_127
0xFFF0_7400
…..
0xFFF0_75FC
R/W Flash Buffer 0
Undefined
FB1_0
…..
FB1_127
0xFFF0_7800
…..
0xFFF0_79FC
R/W Flash Buffer 1 Undefined