Instruction Manual

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 237 - Revision B2
6.9.3 SD Register Description
SD Gloal Control Register (SDGCR)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
SDGCR
0xFFF0_7000
R/W
SD Global Control Register
0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
RdSel
7 6 5 4 3 2 1 0
Reserved
WrSel DMARd
DMAWr SWRST SDEN
BITS DESCRIPTIONS
[31:11]
Reserved
-
[10:8]
RdSel
Read Select
This field indicates which of DMA or SD host controller can read data
from buffer 0 or buffer 1.
3’b000: DMA can read buffer 0 (Default)
3’b011: SD host controller can read buffer 0
3’b100: DMA can read buffer 1
3’b111: SD host controller can read buffer 1
[6:4]
WrSel
Write Select
This field indicates which of DMA, SD host controller can write data into
buffer 0 or buffer 1.
3’b000: DMA can write buffer 0 (Default)
3’b011: SD host controller can write buffer 0
3’b100: DMA can write buffer 1
3’b111: SD host controller can write buffer 1