Instruction Manual

W90P710CD/W90P710CDG
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6.10.3.7 LCD Timing Generation
LCD Timing Control 1 Register (LCDTCON1)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
LCDTCON1 0xFFF0_80B0 R/W LCD Timing Control 1 0x0000_0000
31 30 29 28 27 26 25 24
Reserved HSPW[9:4]
23 22 21 20 19 18 17 16
HSPW[3:0] HBPD[9:6]
15 14 13 12 11 10 9 8
HBPD[5:0] HFPD[9:8]
7 6 5 4 3 2 1 0
HFPD[7:0]
BITS DESCRIPTIONS
[31:30] Reserved Reserved
[29:20] HSPW
Horizontal sync pulse width determines the HSYNC pulse's high
level width by counting the number of the VCLK.
[19:10] HBPD
Horizontal back porch is the number of VCLK periods between the
falling edge of HSYNC and the start of active data.
[9:0] HFPD
Horizontal front porch is the number of VCLK periods between
the end of active data and the rising edge of HSYNC.
LCD Timing Control 2 Register (LCDTCON2)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
LCDTCON2 0xFFF0_80B4 R/W LCD Timing Control 2 0x0000_0000