Instruction Manual

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 309 - Revision B2
The signal format is shown as Figure 6.11.2.2
Figure 6.11.2.2 The signal format of AC-link
The structure of output frame is shown as below:
SLOT #
0 1 2 3 4 5 6 7 8 9 10 11 12
CONTENT
Tag
CMD
ADDR
CMD
DATA
PCM
LEFT
PCM
RIGHT
Unused
BITS
15-0 19-0 19-0 19-0 19-0 159 - 0
PHASE
Tag phase
Data phase
The output frame data format is shown as following:
SLOT # BIT DESCRIPTION
15 Frame validity bit, 1 is valid, 0 is invalid.
14 - 3
Slot validity, but in W90P710, only bits 6-3 are used, bits 14-7 are
unused. Bit 3 is corresponding to slot 1, bit 4 is corresponding to slot
2, etc.. 1 is valid, 0 is invalid. The unused bits 14-7 should be cleared
to 0.
Tag
(slot 0)
2 - 0 This field should be cleared to 0.
19 - 4
Control register write data. It should be cleared to 0 if current
operation is read.
CMD DATA
(slot 2)
3 - 0 This field should be cleared to 0
. .
. . .
...
...
.
...
.
.
.
SYNC
BCLK
DIN
DOUT
Tag phase
Data phase
S
lot
0
Slot 1 Slot 2
Slot 3
Slot 4 Slot 5 –12
Frame (48 KHz)
12.2
88
MHz
B255
B0 B1 B15 B16 B35
MS LS
B36 B55 B56 B75 B76 B95 B96 B255