Instruction Manual

W90P710CD/W90P710CDG
- 320 -
BITS DESCRIPTIONS
[31:3] Reserved -
[2] P_FIFO_EMPTY
Playback FIFO empty indicator bit
P_FIFO_EMPTY=0, the playback FIFO is not empty
P_FIFO_EMPTY=1, the playback FIFO is empty
The P_FIFO_EMPTY bit is read only
[1] P_DMA_END_IRQ
DMA end address interrupt request bit for playback
P_DMA_END_IRQ=0, means playback DMA address does not
reach the end address
P_DMA_END_IRQ=1, means playback DMA address reach the
end address
The P_DMA_END_IRQ bit is readable, and only can be clear
by write “1” to this bit
[0]
P_DMA_MIDDLE
_IRQ
DMA address interrupt request bit for playback
P_DMA_MIDDLE_IRQ=0, means playback DMA address does
not reach the middle address
P_DMA_MIDDLE_IRQ=1, means playback DMA address reach
the middle address
The P_DMA_MIDDLE_IRQ bit is readable, and only can be
clear by write “1” to this bit
IIS control register (ACTL_IISCON)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
ACTL_IISCON
0xFFF0_9028 R/W IIS control register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved
P_FIFO_EMPTY P_DMA_END_IRQ
P_DMA_MIDDLE
_IRQ