Instruction Manual

W90P710CD/W90P710CDG
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This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows
Baud Rate = Crystal Clock / {16 * [Divisor + 2]}
Note: This definition is different from 16550
UART Interrupt Identification Register (UART_IIR)
REGISTER OFFSET R/W DESCRIPTION RESET VALUE
UART_IIR
0x08
R
Interrupt Identification Register 0x8181_8181
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
FMES RFTLS DMS IID NIP
BITS DESCRIPTIONS
[7]
FMES
FIFO Mode Enable Status
This bit indicates whether the FIFO mode is enabled or not. Since the FIFO
mode is always enabling, this bit always shows the logical 1 when CPU is
reading this register.
[6:5]
RFTLS
RX FIFO Threshold Level Status
These bits show the current setting of receiver FIFO threshold level (RTHO).
The meaning of RTHO is defined in the following FCR description.
[4]
DMS
DMA Mode Select
The DMA function is not implemented in this version. When reading IIR, the
DMS is always returned 0.
[3:1]
IID
Interrupt Identification
The IID together with NIP indicates the current interrupt request from UART
[0]
NIP
No Interrupt Pending
There is no pending interrupt.