Instruction Manual

W90P710CD/W90P710CDG

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UART Modem Control Register (UART_MCR)

UART_MCR

0x10 R/W

Modem Control Register (Optional)

0x0000_0000

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1 0

Reserved LBME Reserve Reserve Reserved DTR#

BITS DESCRIPTIONS

[31:5] Reserved

[4] LBME

Loop-back Mode Enable

0 = Disable

1 = When the loop-back mode is enabled, the following signals are connected

internally

SOUT connected to SIN and SOUT pin fixed at logic 1

DTR# connected to DSR# and DTR# pin fixed at logic 1

[3:1] Reserved -

[0] DTR

Complement version of DTR# (Data-Terminal-Ready) signal

Writing 0x00 to MCR, the DTR# bit are set to logic 1’s;

Writing 0x0f to MCR, the DTR# bit are reset to logic 0’s.

UART Line Status Control Register (UART_LSR)

UART_LSR

0x14 R Line Status Register 0x6060_6060