Instruction Manual

W90P710CD/W90P710CDG
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HSUART Modem Status Register (HSUART_MSR)
REGISTER OFFSET R/W DESCRIPTION RESET VALUE
HSUART_MSR
0x18 R
MODEM Status Register (Optional)
0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved
CTS#
Reserved
DCTS
BITS DESCRIPTIONS
[31:5]
Reserved -
[4]
CTS#
Complement version of clear to send (CTS#) input
(This bit is selected by IP)
[3:1]
Reserved -
[0]
DCTS
CTS# State Change
(This bit is selected by IP)
This bit is set whenever CTS# input has changed state, and it will be reset if
the CPU reads the MSR.
Whenever any of MSR [0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing
MSR is a null operation (not suggested).
HSUART Time Out Register (HSUART_TOR)
REGISTER OFFSET R/W DESCRIPTION RESET VALUE
HSUART_TOR
0x1C
R/W Time Out Register
0x0000_0000