Instruction Manual

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 365 - Revision B2
31 30 29 28 27 26 25 24
nDBGACK_EN CEN IE MODE[1:0] CRST CACT Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
PRESCALE[7:0]
BITS DESCRIPTIONS
[31]
nDBGACK_EN
ICE debug mode acknowledge enable
0 = When DBGACK is high, the TIMER counter will be held
1 = No matter DBGACK is high or not, the TIMER counter will not
be held
[30]
CEN
Counter Enable
0 = Stops/Suspends counting
1 = Starts counting
[29]
IE
Interrupt Enable
0 = Disable TIMER Interrupt.
1 = Enable TIMER Interrupt. If timer interrupt is enabled, the timer
asserts its interrupt signal when the associated counter
decrements to zero.
[28:27]
MODE
Timer Operating Mode
MODE Timer Operating Mode
00 The timer is operating in the one-shot mode. The
associated interrupt signal is generated once (if IE is
enabled) and CEN is automatically cleared then.
01 The timer is operating in the periodic mode. The
associated interrupt signal is generated periodically
(if IE is enabled).
10 The timer is operating in the toggle mode. The
interrupt signal is generated periodically (if IE is
enabled). And the associated signal (tout) is
changing back and forth with 50% duty cycle.
11 Reserved.