Instruction Manual

W90P710CD/W90P710CDG
- 366 -
Continued
BITS DESCRIPTIONS
[26]
CRST
Counter Reset
Set this bit will reset the TIMER counter, and also force CEN to 0.
0 = No effect.
1 = Reset Timer’s prescale counter, internal 24-bit counter and
CEN.
[25]
CACT
Timer is in Active
This bit indicates the counter status of timer.
0 = Timer is not active.
1 = Timer is in active.
[24:8]
Reserved Reserved
[7:0]
PRESCALE
Prescale
Clock input is divided by PRESCALE+1 before it is fed to the
counter. If PRESCALE=0, then there is no scaling.
Timer Initial Count Register 0/1 (TICR0/1)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
TICR0
0xFFF8_1008 R/W Timer Initial Control Register 0 0x0000_0000
TICR1
0xFFF8_100C R/W Timer Initial Control Register 1 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
TIC [23:16]
15 14 13 12 11 10 9 8
TIC [15:8]
7 6 5 4 3 2 1 0
TIC [7:0]