Instruction Manual

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 421 - Revision B2
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED
7 6 5 4 3 2 1 0
EnINT5 DBE5 ISTYPE5 EnINT4 DBE4 ISTYPE4
BITS DESCRIPTION
[31:8] RESERVED
-
[7]
EnINT5
Enable INT5
Setting this bit 1 to enable extend interrupt 5.
1 = Enable interrupt 5
0 = Disable interrupt 5
The AIC interrupt channel 31 is reserved for interrupt 5 and 4 (wired-OR), if
this bit is set and interrupt 5 occur, then it will send an interrupt request
signal into AIC module.
[6]
DBE5
Debounce circuit enable for INT5
(alternative function of nWAIT pin)
Extend interrupt 5 shares the same debounce circuit with nIRQ[3:0],
software can configure debounce sampling time in GPIO_DEBNCE control
register. DBE5 function is the same as DBE0 in GPIO_DBENCE register.
1 = Enable debounce
0 = Disable debounce
[5:4]
STYPE5
Interrupt 5 source type
ISTYPE5 Interrupt Source Type
2’b00 LOW level sensitive
2’b01 HIGH level sensitive
2’b10 Negative edge triggered
2’b11 Positive edge triggered