Instruction Manual

W90P710CD/W90P710CDG
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6.17.2 Register Description
Receive Buffer Register (SCHI_RBR)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
SCHI_RBR0 0XFFF8_5000 (DLAB = 0) R Receiver Buffer Register 0 Undefined
SCHI_RBR1 0xFFF8_5800 (DLAB = 0) R Receiver Buffer Register 1 Undefined
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED
7 6 5 4 3 2 1 0
RxBDATA[7:0]
BITS DESCRIPTIONS
[31:8]
RESERVED -
[7:0]
RxBDATA
8-bit Received Data
By reading this register, the SCHI will return an 8-bit data received
from SCx_DAT pin.
This register is the access port for receiver FIFO. The depth of
receiver FIFO is 16 bytes.
Transmit Buffer Register (SCHI_TBR)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
SCHI_TBR0
0xFFF8_5000(DLAB = 0) W Transmit Buffer Register 0 Undefined
SCHI_TBR1
0xFFF8_5800(DLAB = 0) W Transmit Buffer Register 1 Undefined