Instruction Manual

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 443 - Revision B2
BITS DESCRIPTIONS
[31:8]
RESERVED -
[7:0]
TxBDATA
8-bit Transmit Buffer Data
By writing to this register, the SCHI will send out an 8-bit data through the
SCx_DAT pin.
This register is the access port for transmitter FIFO. The depth of
transmitter FIFO is 16 bytes.
Interrupt Enable register (SCHI_IER)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
SCHI_IER0
0xFFF8_5004 (DLAB = 0) R/W Interrupt Enable Register 0 0x0000_0080
SCHI_IER1
0xFFF8_5804 (DLAB = 0) R/W Interrupt Enable Register 1 0x0000_0080
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED
7 6 5 4 3 2 1 0
TxBDATA[7:0]
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED ETOR2 ETOR1 ETOR0
7 6 5 4 3 2 1 0
PWRDN Interface RESERVED ESCPTI ESCSRI ETBREI ERDRI