Instruction Manual

W90P710CD/W90P710CDG

Publication Release Date: September 19, 2006

- 447 - Revision B2

Smart Card FIFO control Register (SCHI_SCFR)

SCHI_SCFR0 0xFFF8_5008 (DLAB = 0) W Interrupt Status Register 0 0x0000_0000

SCHI_SCFR1 0xFFF8_5808 (DLAB = 0) W Interrupt Status Register 1 0x0000_0000

BITS DESCRIPTIONS

[31:8]

RESERVED -

[7:6]

RxTL1,

RxTL0

Receiver FIFO active Threshold Level control bits. These two bits are

used to set the active level for the receiver FIFO interrupt. For example,

if the interrupt active level is set as 4 bytes, once there are at least 4

data characters in the receiver FIFO, an interrupt is activated to notify

host to read data from FIFO. Default to be 00b.

RxTL1 RxTL0 Rx FIFO Interrupt Active Level (Bytes)

0 0 01

0 1 04

1 0 08

1 1 14

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED

7 6 5 4 3 2 1 0

RxTL1 RxTL0 PEC2 PEC1 PEC0 TxFRST RxFRST Reserved