Instruction Manual

W90P710CD/W90P710CDG

Publication Release Date: September 19, 2006

- 455 - Revision B2

Smart Card Host Test Mode Register (SCHI_TMR)

SCHI_TMR0 0xFFF8_5020

R/W

Test mode Register 0 0x0000_0000

SCHI_TMR1 0XFFF8_5820

R/W

Test mode Register 1 0x0000_0000

This 8 bit register is added in order to allow better testability of the Smart Card host. Currently only bit 1 is

utilized. In the future, other bits can be used to program the host to improve testability on the testing

platform.

31 30 29 28 27 26 25 24

RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED

7 6 5 4 3 2 1 0

RESERVED SCRST_L

POWER_SEQ

_SKIP