Instruction Manual

W90P710CD/W90P710CDG
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Input Divider
(NR)
PFD
Feedback
Divider
(NF)
Charge
Pump
VCO
Output
Divider
(NO)
EXTAL
OTDV1[1:0]
PLL1
INDV1[4:0]
FBDV1[8:0]
480MHz
FIN
FOUT
to LCD controller
to Audio Controller
Fig 6.2.8.2 LCD PLL block diagram
The formula of output clock of PLL is:
FOUT = FIN
NONR
NF 1
∗∗
FOUT：Output clock of Output Divider
FIN：External clock into the Input Divider
NR：Input divider value (NR = INDV1 + 2)
NF：Feedback divider value (NF = FBDV1 + 2)
NO：Output divider value (NO = OTDV1)