Instruction Manual

W90P710CD/W90P710CDG
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Continued.
BITS DESCRIPTION
[2:0] tRAS
SDRAM bank 0/1, Row active time
tRAS [2:0] MCLK
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8
Fig 6.3.4 Access timing 1 of SDRAM
Fig 6.3.5 Access timing 2 of SDRAM