W982516CH GENERAL DESCRIPTION 4M × 4 BANKS × 16 BIT SDRAM W982516CH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 4M words × 4 banks × 16 bits. Using pipelined architecture and 0.13 µm process technology, W982516CH delivers a data bandwidth of up to 166M words per second (-6). To fully comply with the personal computer industrial standard, W982516CH is sorted into two speed grades: -6, -7 and -75.
W982516CH PIN CONFIGURATION V CC 1 54 V SS DQ0 2 53 DQ15 V CC Q 3 52 V SS Q DQ1 4 51 DQ14 DQ2 5 50 DQ13 V SS Q 6 49 V CCQ DQ3 7 48 DQ12 DQ4 8 47 DQ11 V CC Q 9 46 V SS Q DQ5 10 45 DQ10 DQ6 11 44 DQ9 V SS Q 12 43 V CCQ DQ7 13 42 DQ8 V CC 14 41 V SS LDQM 15 40 NC WE 16 39 UDQM CAS 17 38 CLK RAS 18 37 CKE CS 19 36 A12 BS0 20 35 A11 BS1 21 34 A9 A10/AP 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4
W982516CH PIN DESCRIPTION PIN NO. PIN NAME FUNCTION 23−26, 22, 29−36 A0−A12 Address 20, 21 BS0, BS1 Bank Select Select bank to activate during row address latch time, or bank to read/write during address latch time. Data Input/Output Multiplexed pins for data output and input. Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues.
W982516CH BLOCK DIAGRAM CLK CLOCK BUFFER CKE CS CONTROL SIGNAL GENERATOR RAS COMMAND CAS DECODER COLUMN DECODER COLUMN DECODER A10 BANK #0 MODE REGISTER A0 CELL ARRAY BANK #1 SENSE AMPLIFIER SENSE AMPLIFIER ADDRESS BUFFER DATA CONTROL DQ BUFFER CIRCUIT DQ0 DQ15 COLUMN COUNTER LDQM UDQM COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER Note: The cell array configuration is 8192 * 512 * 16.
W982516CH ABSOLUTE MAXIMUM RAT INGS PARAMETER SYMBOL RATING UNIT NOTES Input, Output Voltage V IN, V OUT -0.3 − V CC + 0.3 V 1 Supply Voltage V CC, V CCQ -0.3 − 4.
W982516CH AC CHARACTERISTICS AND OPERATING CONDITION (Vcc = 3.3V ± 0.3V, Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I ; Notes: 5, 6, 7, 8) PARAMETER SYM. -7 -75/75L/75I (PC133, CL2) (PC133, CL3) MIN. Ref/Active to Ref/Active Command Period MAX. MIN. UNIT MAX.
W982516CH PARAMETER -6 SYM. MIN. Ref/Active to Ref/Active Command Period UNIT MAX. t RC 60 Active to precharge Command Period t RAS 42 Active to Read/Write Command Delay Time t RCD 18 nS Read/Write(a) to Read/Write(b) Command Period t CCD 1 tCK Precharge to Active Command Period tR P 18 nS Active(a) to Active(b) Command Period t RRD 12 nS Write Recovery Time t WR 2 tCK tC K 7.
W982516CH DC CHARACTERISTICS (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C for –6/-7/-75/75L, Ta=-40 to 85°C for 75I) PARAMETER SYM. -6 -7 -75/75L/75I MAX. MAX. UNIT NOTES 1 Bank Operation ICC1 90 80 75 3 CKE = VIH ICC2 50 40 35 3 CKE = VIL (Power ICC2P 2 2 2 3 CKE = VIH ICC2S 10 10 10 V IH /L = V IH (min.)/VIL (max.
W982516CH Notes: 1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices. 2. All voltages are referenced to VSS 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t C K and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up sequence is further described in the "Functional Description" section. 6.
W982516CH OPERATION MODE Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands.
W982516CH FUNCTIONAL DESCRIPTION Power Up and Initialization The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all Vcc and VccQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed Vcc +0.3V on any of the input pins or Vcc supplies.
W982516CH Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode.
W982516CH Addressing Sequence of Sequential Mode A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2.
W982516CH Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency.
W982516CH The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to t CKS (min) + tCK (min). No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations.
W982516CH TIMING WAVEFORMS Command Input Timing Command Input Timing t CL tCK tCH V IH CLK V IL tT tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH tAS t AH tCMH CS RAS CAS WE A0-A12 BS0, 1 tCKS tCKH tCKS tCKH tCKS CKE - 16 - t CKH tT tCMS
W982516CH Timing Waveforms, continued Read Timing Read CAS Latency CLK CS RAS CAS WE A0 - A12 BS0, 1 tAC t LZ tAC t HZ tOH tOH Valid Data-Out DQ Read Command Valid Data-Out Burst Length - 17 - Publication Release Date: Mar 2003 Revision A1
W982516CH Timing Waveforms, continued Control Timing of Input/Output Data Input Data (Word Mask) CLK tCMS tCMH tCMH tCMS DQM tDS t DH t DS Valid Data-in DQ0 -15 tDH tDS Valid Data-in tDH tDS Valid Data-in tDH Valid Data-in (Clock Mask) CLK tCKH tCKS tDH tDS tCKH tCKS CKE tDS DQ0 -15 Valid Data-in tDH tDS Valid Data-in tDH tDS Valid Data-in tDH Valid Data-in Output Data (Output Enable) CLK tCMH tCMS tCMH tCMS DQM tAC tOH tOH Valid Data-Out DQ0 -15 tAC tLZ tHZ tAC t
W982516CH Timing Waveforms, continued Mode Register Set Cycle tRSC CLK tCMS tCMH tCMS tCMH tCMS tCMH tCMS t CMH CS RAS CAS WE t AS A0-A12 BS0,1 tAH Register set data next command A0 A1 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency A2 0 0 0 0 1 1 1 1 A6 A7 A0 "0" (Test Mode) A8 "0" Reserved A9 A0 WriteA0 Mode A10 "0" A11 A0 "0" A12 "0" BS0 A0 "0" BS1 A0 "0" A0 Reserved A6 0 0 0 0 1 A0 A0 A1 A0 0 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 A0 1 A0 A3 A0 0 A0 1 A0 A5 A0 0 A
W982516CH OPERATING TIMING EXAMPLE Interleaved Bank Re ad (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS t RAS t RP tRAS t RAS t RP t RP tRAS CAS WE BS0 BS1 t RCD A10 A0-A9, A11,12 tRCD RAa tRCD RBb RAa RBb CAw tRCD RAc CBx RBd RAc CAy RAe RBd CBz RAe DQM CKE t AC t AC DQ aw0 aw1 tRRD Bank #0 Active Bank #1 aw2 aw3 tAC bx0 Precharge Active bx2 bx3
W982516CH Operating Timing Example, continued Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC t RC RAS tRAS tRP tRAS tRAS tRP tRP t RAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11,12 RAa t RCD tRCD RBb CAw tRCD RBb CBx RAe RBd RAc CAy RAc CBz RBd RAe DQM CKE tAC DQ tRRD Active Bank #0 Bank #1 aw1 aw2 aw3 bx0 tRRD Read tAC tAC aw
W982516CH Operating Timing Example, continued Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK CS tRC tRC tRC RAS tRAS tRP tRAS t RP tRAS tRP CAS WE BS0 BS1 tRCD A10 A0-A9, A11,12 t RCD RAa RAa tRCD RBb CAx RAc RBb CBy RAc CAz DQM CKE tAC DQ t AC ax0 ax1 tRRD Bank #0 Active Bank #1 ax2 ax3 ax4 ax5 by0 by1 by4 by5 by6 by7 tRRD Read Precharge ax6 tAC Precharg
W982516CH Operating Timing Example, continued Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRC CS tRC RAS t RAS t RP tRAS tRAS t RP CAS WE BS0 BS1 tRCD tRCD tRCD A10 RAa A0-A9, A11,12 RAa RBb CAx RAc RBb RAc CBy CAz DQM CKE tCAC tCAC DQ ax0 ax1 ax2 tRRD Bank #0 Active ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 CZ0 tRRD AP* Read Active
W982516CH Operating Timing Example, continued Interleaved Bank Write (Burst Length = 8) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRAS tRP tRAS tRP CAS tRCD t RCD t RCD WE BS0 BS1 A10 RAa A0-A9, A11,12 RAa RBb CAx RAc RBb CBy RAc CAz DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 t RRD Bank #0 Active Write by3 Precharge Write Bank #2 Bank #3 by2 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD Active Ban
W982516CH Operating Timing Example, continued Interleaved Bank Write (Burst Length = 8, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP t RAS tRAS t RP CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11,12 RAa tRCD tRCD RBb CAx RAb CBy RBb CAz RAc DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 tRRD Bank #0 Active by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD AP* Write Active Bank #1 by2 Write
W982516CH Operating Timing Example, continued Page Mode Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK tCCD tCCD tCCD CS tRAS tRP tRAS tRP RAS CAS WE BS0 BS1 t RCD A10 A0-A9, A11,12 tRCD RAa RBb RAa CAI RBb CBx CAy CAm CBz DQM CKE tAC DQ t AC tAC a0 a1 a2 a3 bx0 bx1 Ay0 t AC Ay1 Ay2 tAC am0 am1 am2 bz0 bz1 tRRD Bank #0 Active Bank #1 Read Read Active Read Read Pre
W982516CH Operating Timing Example, continued Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRAS t RP RAS CAS WE BS0 BS1 tRCD A10 A0-A9, A11,12 RAa RAa CAx CAy DQM CKE tAC DQ tWR ax0 Q Q Bank #0 Active ax1 ax3 ax2 Q Q ax5 ax4 Q Q Read ay0 D ay1 D Write ay2 D ay4 ay3 D D Precharge Bank #1 Bank #2 Bank #3 Idle - 27 - Publication Release Date: Mar
W982516CH Operating Timing Example, continued Auto Precharge Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK CS tRC tRC RAS t RAS t RP t RAS t RP CAS WE BS0 BS1 tRCD A10 A0-A9, A11,12 tRCD RAa RAa RAb CAw RAb CAx DQM CKE tAC DQ Bank #0 t AC aw0 Active Read aw1 AP* aw2 aw3 bx0 Active Read Bank #1 Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 28 - bx1 AP* bx
W982516CH Operating Timing Example, continued Auto Precharge Write (Burst Length = 4) (CLK = 100 MHz) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 t RCD tRCD A10 A0-A9, A11,12 RAa RAa RAb CAw RAb RAc CAx RAc DQM CKE DQ Bank #0 aw0 Active aw1 Write aw2 bx0 aw3 AP* Active bx1 Write bx2 bx3 AP* Active Bank #1 Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 29
W982516CH Operating Timing Example, continued Auto Refresh Cycle (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK tRP tRC t RC CS RAS CAS WE BS0,1 A10 A0-A9, A11,12 DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) - 30 - 21 22 23
W982516CH Operating Timing Example, continued Self Refresh Cycle (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRP RAS CAS WE BS0,1 A10 A0-A9, A11,12 DQM tCKS t CKS tSB CKE tCKS DQ t RC Self Refresh Cycle All Banks Precharge No Operation Cycle Self Refresh Entry Arbitrary Cycle - 31 - Publication Release Date: Mar 2003 Revision A1
W982516CH Operating Timing Example, continued Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK CS RAS CAS tRCD WE BS0 BS1 A10 RBa A0-A9, A11,12 RBa CBv CBw CBx CBy CBz DQM CKE tAC DQ tAC av0 Q Bank #0 Active Bank #1 Bank #2 Bank #3 av1 Q av2 av3 aw0 ax0 ay0 Q Q D D D Read Single Write Idle - 32 - az0 Q Read az1 az2 az3 Q Q Q 22 23
W982516CH Operating Timing Example, continued PowerDown Mode (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BS A10 RAa A0-A9 A11,12 RAa RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS tCKS DQ ax0 Active ax1 ax2 NOP Read tCKS ax3 Precharge NOPActive Precharge Standby Power Down mode Active Standby Power Down mode Note: The PowerDown Mode is entered by asserting CKE "low".
W982516CH Operating Timing Example, continued Autoprecharge Timing (Read Cycle) 0 1 Read AP 2 3 4 5 6 7 8 9 10 11 (1) CAS Latency=2 ( a ) burst length = 1 Command DQ Act t RP Q0 ( b ) burst length = 2 Command Read AP DQ Act tRP Q0 Q1 ( c ) burst length = 4 Command Read AP Act tRP DQ Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 ( d ) burst length = 8 Command Read AP DQ Q4 Q5 Q6 Act tRP Q7 (2) CAS Latency=3 ( a ) burst length = 1 Command Read AP Act tRP Q0 DQ ( b ) burst l
W982516CH Operating Timing Example, continued Autoprecharge Timing (Write Cycle) 0 1 2 3 4 5 6 7 8 9 10 11 12 (1) CAS Latency = 2 (a) burst length = 1 Command Write AP tWR DQ Act tRP D0 (b) burst length = 2 Command Write AP Act tWR DQ D0 tRP D1 (c) burst length = 4 Command AP Write tWR DQ D0 D1 D2 Act tRP D3 (d) burst length = 8 Command Write AP tWR DQ D0 D1 D2 D3 D4 D5 D6 Act tRP D7 (2) CAS Latency = 3 (a) burst length = 1 Command Write AP Act tWR DQ
W982516CH Operating Timing Example, continued Timing Chart of Read to Write Cycle In the case of Burst Length = 4 (1) CAS Latency=2 0 1 2 3 4 5 D1 D2 D3 D0 D1 D2 D1 D2 D3 D1 D2 6 7 8 9 10 11 9 10 11 Read Write ( a ) Command DQM D0 DQ Read ( b ) Command Write DQM DQ D3 (2) CAS Latency=3 Read Write ( a ) Command DQM D0 DQ Read ( b ) Command Write DQM D0 DQ D3 Note: The Output data must be masked by DQM to avoid I/O conflict Timing Chart of Write to Read Cyc
W982516CH Timing Chart of Burst Stop Cycle (Burst Stop Command) 0 1 2 3 4 5 6 7 8 9 10 11 (1) Read cycle ( a ) CAS latency =2 Command Read BST Q0 DQ Q1 Q2 Q3 Q4 ( b )CAS latency = 3 Command Read BST Q0 DQ Q1 Q2 Q3 Q4 (2) Write cycle Command Write BST DQ Q0 Q1 Q2 Note: Q3 BST Q4 represents the Burst stop command Timing Chart of Burst Stop Cycle (Precharge Command) - 37 - Publication Release Date: Mar 2003 Revision A1
W982516CH 0 1 2 3 4 5 6 7 (1) Read cycle (a) CAS latency =2 Command Read PRCG DQ (b) CAS latency =3 Command Q0 Q1 Q2 Read Q3 Q4 PRCG DQ Q0 Q1 Q2 Q3 (2) Write cycle (a) CAS latency =2 PRCG Write Command tWR DQM DQ (b) CAS latency =3 Command Q0 Q1 Q2 Q3 Q4 PRCG Write tWR DQM DQ Q0 Q1 Q2 Q3 Q4 - 38 - Q4 8 9 10 11
W982516CH Operating Timing Example, continued CKE/DQM Input Timing (Write Cycle) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D5 DQM MASK D6 CKE MASK (1) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D5 DQM MASK D6 CKE MASK (2) CLK cycle No.
W982516CH Operating Timing Example, continued CKE/DQM Input Timing (Read Cycle) CLK cycle No. 1 2 3 4 Q 1 Q 2 Q 3 Q 4 5 6 7 External CLK Internal CKE DQM DQ Open Open Q 6 (1) CLK cycle No. 1 2 3 Q 1 Q 2 Q 3 4 5 6 7 External CLK Internal CKE DQM DQ Q 4 Open Q 6 (2) CLK cycle No.
W982516CH Operating Timing Example, continued Self Refresh/Power Down Mode Exit Timing Asynchronous Control Input Buffer turn on time ( Power down mode exit time ) is specified by tCKS(min) + tCK(min) A ) tCK < tCKS(min)+tCK (min) t CK CLK CKE tCKS(min)+tC K(min) NOP Command Command Input Buffer Enable B) tCK >= tCKS(min) + tCK (min) tCK CLK tCKS(min)+tC K(min) CKE Command Command Input Buffer Enable Note ) All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode and Self R
W982516CH PACKAGE DIMENSION 54L TSOP (II)-400 mil 54 28 HE E 1 27 e b C D L A2 A1 ZD Y SEATING PLANE Controlling Dimension: Millimeters DIMENSION (MM) SYM. MIN. NOM. A A1 0.05 0.10 DIMENSION (INCH) MAX. 1.20 0.15 MIN. 0.002 1.00 NOM. 0.004 MAX. 0.047 0.006 0.039 A2 b c 0.24 0.32 0.15 0.40 0.009 0.012 0.006 0.016 D E 22.12 10.06 22.22 10.16 22.62 10.26 0.871 0.396 0.875 0.400 0.905 0.404 HE e 11.56 11.76 11.96 0.455 0.463 0.471 L 0.40 L1 0.80 0.50 0.60 0.
W982516CH 11. REVERSION HISTORY REVERSION A1 DATE PAGE March, 2003 - Oct, 2003 Headquarters DESCRIPTION Preliminary datasheet Add –6 speed grade Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Hsinchu, Taiwan Kowloon, Hong Kong TEL: 886-3-5770066 TEL: 852-27513100 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.
