W9864G2GH Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. AVAILABLE OPTIONS................................................................................................................ 4 4. PIN ASSIGNMENT .................................................
W9864G2GH 12. AC CHARACTERISTICS .......................................................................................................... 16 13. TIMING WAVEFORMS ............................................................................................................. 19 14. 15. 13.1 Command Input Timing ................................................................................................ 19 13.2 Read Timing............................................................................
W9864G2GH 1. GENERAL DESCRIPTION W9864G2GH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words × 4 banks × 32 bits. Using pipelined architecture and 0.11 µm process technology, W9864G2GH delivers a data bandwidth of up to 800M bytes per second. For different application, W9864G2GH is sorted into the following speed grades:-5,-6,-7.The -5 parts can run up to 200MHz/CL3.The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3.
W9864G2GH 3. AVAILABLE OPTIONS PART NUMBER SPEED (CL = 3) SELF REFRESH CURRENT (MAX.) OPERATING TEMPERATURE W9864G2GH-5 200 MHz 2mA 0°C ~ 70°C W9864G2GH-6 166 MHz 2mA 0°C ~ 70°C W9864G2GH-7 143 MHz 2mA 0°C ~ 70°C 4.
W9864G2GH 5. PIN DESCRIPTION PIN NUMBER PIN NAME FUNCTION DESCRIPTION 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 A0−A10 Address Multiplexed pins for row and column address. Row address: A0−A10. Column address: A0−A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. 22, 23 BS0, BS1 Bank Select Select bank to activate during row address latch time, or bank to read/write during address latch time.
W9864G2GH 6.
W9864G2GH 7. FUNCTIONAL DESCRIPTION 7.1 Power Up and Initialization The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power up voltage must not exceed VCC +0.
W9864G2GH 7.5 Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. 7.
W9864G2GH 7.11 Burst Stop Command A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock.
W9864G2GH 7.14 Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency.
W9864G2GH 7.17 Power Down Mode The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK.
W9864G2GH 8. TABLE OF OPERATING MODES Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands.
W9864G2GH SIMPLIFIED STATE DIAGRAM Self Refresh LF SE Mode Register Set MRS it ex LF E S REF IDLE CBR Refresh CK E CK E ACT Power Down READ Precharge PRE ) tion ina term ge har rec E(p CKE PR WRITEA POWER ON Read Write PR E( p rec har ge term ina tion ) CKE Writ ew Aut o pr ith ech arg e BS T W WRITEA SUSPEND Read WRITE CKE T BS CKE Active Power Down CKE d ea R WRITE SUSPEND CKE ith dw Rea arge ch pre Write o Aut rit e ROW ACTIVE CKE CKE READA CKE CKE READ SUSPEND
W9864G2GH 9. DC CHARACTERISTICS 9.1 Absolute Maximum Rating PARAMETER SYM. RATING UNIT NOTES Input, Column Output Voltage VIN, VOUT -0.3~VCC+0.3V V 1 Power Supply Voltage VCC, VCCQ -0.3~4.
W9864G2GH 11. CAPACITANCE (VCC =3.3V±0.3V, TA = 25 °C, f = 1 MHz) PARAMETER Input Capacitance (A0 to A10, BS0, BS1, CS , RAS , CAS , WE , DQM, CKE) Input Capacitance (CLK) Input/Output capacitance (DQ0−DQ31) SYM. MIN. MAX. UNIT Ci 2.5 4 pf CCLK 2.5 4 pf Co 4 6.5 pf Note: These parameters are periodically sampled and not 100% tested 11.1 DC CHARACTERISTICS (VCC = 3.3V±0.3V, TA = 0°~70°C for -5/-6/-7) PARAMETER SYM. -5 -6 -7 MAX. MAX. MAX.
W9864G2GH 12. AC CHARACTERISTICS (VCC = 3.3V±0.3V, VSS = 0V, Ta = 0 to 70 °C for -5/-6/-7) (Notes: 5, 6.) PARAMETER Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/ Write(b) Command Period Precharge to Active(b) Command Period Active(a) to Active(b) Command Period Write Recovery Time CL* = 2 CL* = 3 CLK Cycle Time CL* = 2 SYM. -5 MIN. -6 MAX. MIN. -7 MAX. MAX.
W9864G2GH Notes: 1.Operation exceeds “ABSOLUTE MAXIMUM RATING” may cause permanent damage to the devices. 2. All voltages are referenced to VSS 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up Sequence (1)Power up must be performed in the following sequence.
W9864G2GH tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.). (2) A.
W9864G2GH 13. TIMING WAVEFORMS 13.
W9864G2GH Timing Waveforms, continued 13.
W9864G2GH Timing Waveforms, continued 13.
W9864G2GH Timing Waveforms, continued 13.
W9864G2GH Timing Waveforms, continued 13.
W9864G2GH 14. OPERATING TIMING EXAMPLE 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.14 Power-down Mode (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BS A10 RAa A0-A9 RAa RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS DQ ax0 Active tCKS tCKS NOP ax1 ax2 ax3 Precharge Read NOPActive Precharge Standby Power Down mode Active Standby Power Down mode Note: The PowerDown Mode is entered by asserting CKE "low".
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.17 Timing Chart of Read to Write Cycle In the case of Burst Length = 4 0 1 2 Read Write 3 4 5 D1 D2 D3 D0 D1 D2 D1 D2 D3 D1 D2 6 (1) CAS Latency=2 ( a ) Command DQM DQ ( b ) Command D0 Read Write DQM DQ (2) CAS Latency=3 ( a ) Command Read D3 Write DQM D0 DQ ( b ) Command Read Write DQM DQ D0 D3 Note: The Output data must be masked by DQM to avoid I/O conflict.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH Operating Timing Example, continued 14.
W9864G2GH 14.
W9864G2GH Operating Timing Example, continued 14.21 CKE/DQM Input Timing (Write Cycle) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D5 DQM MASK D6 CKE MASK (1) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ DQM MASK D5 D6 5 6 7 D4 D5 D6 CKE MASK (2) CLK cycle No.
W9864G2GH Operating Timing Example, continued 14.22 CKE/DQM Input Timing (Read Cycle) CLK cycle No. 1 2 3 4 Q1 Q2 Q3 Q4 5 6 7 External CLK Internal CKE DQM DQ Q6 Open Open (1) CLK cycle No. 1 2 3 Q1 Q2 Q3 4 5 6 7 External CLK Internal CKE DQM DQ Q6 Q4 Open (2) CLK cycle No.
W9864G2GH Operating Timing Example, continued 14.23 Self Refresh/Power Down Mode Exit Timing Asynchronous Control Input Buffer turn on tim e (Power down m ode exit tim e) is specified by t CKS (m in.) + t CK (m in.) A ) t CK < t CKS (m in.) + t CK (m in.) tCK CLK CKE t CK S(m in)+tCK(m in) NOP Com m and Command Input Buffer Enable B) t CK >= t CKS (m in.) + t CK (m in.
W9864G2GH 15. PACKAGE DIMENSIONS 15.1 86L TSOP (II)-400 mil 86 44 HE E 1 43 e b C D q A2 ZD A1 Y A L L1 SEATING PLANE Controlling Dimension: Millimeters DIMENSION (MM) SYM. MIN. NOM. A A1 A2 b 0.05 DIMENSION (INCH) MAX. MIN. NOM. MAX. 0.047 0.006 1.20 0.15 0.002 0.27 0.21 0.007 0.005 0.871 0.875 0.905 0.039 1.00 0.011 c 0.17 0.12 D 22.12 22.22 22.62 E 10.06 10.16 10.26 0.396 0.400 0.404 HE 11.56 11.76 11.96 0.455 0.463 0.471 e L L1 0.50 0.40 0.50 0.
W9864G2GH 16. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A01 8/16/2006 all CREAT NEW DATASHEET Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life.